arm: bcmbca: add bcm63148 SoC support
BCM63148 is an Broadcom B15 based DSL Broadband SoC. It is part of the BCA (Broadband Carrier Access origin) chipset family so it's added under ARCH_BCMBCA platform. This initial support includes a bare-bone implementation and dts with CPU subsystem, memory and Broadcom uart. This SoC is supported in the linux-next git repository so the dts and dtsi files are copied from linux. The u-boot image can be loaded from flash or network to the entry point address in the memory and boot from there. Signed-off-by: William Zhang <william.zhang@broadcom.com>
This commit is contained in:
William Zhang
Tom Rini
parent
4054fd7182
commit
7e3d69592b
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@ -218,6 +218,7 @@ F: arch/arm/mach-bcmbca/
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F: board/broadcom/bcmbca/
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N: bcmbca
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N: bcm[9]?47622
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N: bcm[9]?63148
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N: bcm[9]?63178
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N: bcm[9]?6756
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N: bcm[9]?6846
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@ -1182,6 +1182,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
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dtb-$(CONFIG_BCM47622) += \
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bcm947622.dtb
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dtb-$(CONFIG_BCM63148) += \
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bcm963148.dtb
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dtb-$(CONFIG_BCM63178) += \
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bcm963178.dtb
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dtb-$(CONFIG_BCM6756) += \
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103
arch/arm/dts/bcm63148.dtsi
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103
arch/arm/dts/bcm63148.dtsi
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@ -0,0 +1,103 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Broadcom Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,bcm63148", "brcm,bcmbca";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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B15_0: cpu@0 {
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device_type = "cpu";
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compatible = "brcm,brahma-b15";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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B15_1: cpu@1 {
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device_type = "cpu";
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compatible = "brcm,brahma-b15";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu: pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&B15_0>, <&B15_1>;
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};
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clocks: clocks {
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periph_clk: periph-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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axi@80030000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x80030000 0x8000>;
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x2000 0x2000>,
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<0x4000 0x2000>,
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<0x6000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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};
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bus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xfffe8000 0x8000>;
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uart0: serial@600 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x600 0x20>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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clock-names = "refclk";
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status = "disabled";
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};
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};
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};
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30
arch/arm/dts/bcm963148.dts
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30
arch/arm/dts/bcm963148.dts
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@ -0,0 +1,30 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 Broadcom Ltd.
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*/
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/dts-v1/;
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#include "bcm63148.dtsi"
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/ {
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model = "Broadcom BCM963148 Reference Board";
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compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x08000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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@ -12,6 +12,13 @@ config BCM47622
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select DM_SERIAL
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select PL01X_SERIAL
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config BCM63148
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bool "Support for Broadcom 63148 Family"
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select SYS_ARCH_TIMER
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select CPU_V7A
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select DM_SERIAL
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select BCM6345_SERIAL
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config BCM63178
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bool "Support for Broadcom 63178 Family"
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select SYS_ARCH_TIMER
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@ -41,6 +48,7 @@ config BCM6878
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select PL01X_SERIAL
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source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63148/Kconfig"
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source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
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source "arch/arm/mach-bcmbca/bcm6756/Kconfig"
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source "arch/arm/mach-bcmbca/bcm6846/Kconfig"
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@ -4,6 +4,7 @@
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#
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obj-$(CONFIG_BCM47622) += bcm47622/
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obj-$(CONFIG_BCM63148) += bcm63148/
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obj-$(CONFIG_BCM63178) += bcm63178/
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obj-$(CONFIG_BCM6756) += bcm6756/
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obj-$(CONFIG_BCM6846) += bcm6846/
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17
arch/arm/mach-bcmbca/bcm63148/Kconfig
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17
arch/arm/mach-bcmbca/bcm63148/Kconfig
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@ -0,0 +1,17 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Broadcom Ltd
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#
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if BCM63148
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config TARGET_BCM963148
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bool "Broadcom 63148 Reference Board"
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depends on ARCH_BCMBCA
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config SYS_SOC
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default "bcm63148"
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source "board/broadcom/bcmbca/Kconfig"
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endif
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5
arch/arm/mach-bcmbca/bcm63148/Makefile
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5
arch/arm/mach-bcmbca/bcm63148/Makefile
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2022 Broadcom Ltd
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#
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obj- += dummy.o
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@ -16,6 +16,13 @@ config SYS_CONFIG_NAME
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endif
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if TARGET_BCM963148
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config SYS_CONFIG_NAME
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default "bcm963148"
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endif
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if TARGET_BCM963178
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config SYS_CONFIG_NAME
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23
configs/bcm963148_defconfig
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23
configs/bcm963148_defconfig
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@ -0,0 +1,23 @@
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CONFIG_ARM=y
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CONFIG_COUNTER_FREQUENCY=50000000
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CONFIG_ARCH_BCMBCA=y
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CONFIG_SYS_TEXT_BASE=0x01000000
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_BCM63148=y
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CONFIG_TARGET_BCM963148=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_DEFAULT_DEVICE_TREE="bcm963148"
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CONFIG_IDENT_STRING=" Broadcom BCM63148"
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CONFIG_SYS_LOAD_ADDR=0x01000000
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CONFIG_ENV_VARS_UBOOT_CONFIG=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_MAXARGS=64
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CONFIG_SYS_BOOTM_LEN=0x4000000
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CONFIG_CMD_CACHE=y
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CONFIG_OF_EMBED=y
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CONFIG_CLK=y
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11
include/configs/bcm963148.h
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11
include/configs/bcm963148.h
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2022 Broadcom Ltd.
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*/
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#ifndef __BCM963148_H
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#define __BCM963148_H
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#endif
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