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Convert CONFIG_SPL_GD_ADDR to Kconfig

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This converts the following to Kconfig:
   CONFIG_SPL_GD_ADDR

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-05-27 16:19:05 -04:00
parent cfb5dd3585
commit 7f2c91e5d8
54 changed files with 55 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
board/freescale/p1010rdb/spl.c
View File

@ -63,11 +63,11 @@ void board_init_f(ulong bootflag)
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
gd = (gd_t *)CONFIG_VAL(GD_ADDR);
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;

4
board/freescale/p1_p2_rdb_pc/spl.c
View File

@ -69,11 +69,11 @@ void board_init_f(ulong bootflag)
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
gd = (gd_t *)CONFIG_VAL(GD_ADDR);
struct bd_info *bd;
memset(gd, 0, sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
bd = (struct bd_info *)(CONFIG_VAL(GD_ADDR) + sizeof(gd_t));
memset(bd, 0, sizeof(struct bd_info));
gd->bd = bd;

8
common/spl/Kconfig
View File

@ -246,6 +246,10 @@ config SPL_FLUSH_IMAGE
config SPL_SKIP_RELOCATE
bool "Skip relocating SPL"
config SPL_GD_ADDR
hex "Address to use for global data (gd) in SPL"
depends on !SPL_INIT_MINIMAL
config SPL_RELOC_TEXT_BASE
hex "Address to relocate SPL to"
default SPL_TEXT_BASE
@ -272,6 +276,10 @@ config SPL_RELOC_MALLOC_SIZE
hex "Size of malloc pool in SPL"
depends on SPL_RELOC_MALLOC
config TPL_GD_ADDR
hex "Address to use for global data (gd) in TPL"
depends on TPL
config TPL_RELOC_TEXT_BASE
hex "Address to relocate TPL to"
depends on TPL

1
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000
CONFIG_SPL_RELOC_STACK=0xd003fff0
CONFIG_TPL_GD_ADDR=0xd002c000
CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_TPL_RELOC_STACK=0xd0030000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PA_NAND_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000
CONFIG_SPL_RELOC_STACK=0xd003fff0
CONFIG_TPL_GD_ADDR=0xd002c000
CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_TPL_RELOC_STACK=0xd0030000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -29,6 +29,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000
CONFIG_SPL_RELOC_STACK=0xd003fff0
CONFIG_TPL_GD_ADDR=0xd002c000
CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_TPL_RELOC_STACK=0xd0030000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PB_NAND_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xd003d000
CONFIG_SPL_RELOC_STACK=0xd003fff0
CONFIG_TPL_GD_ADDR=0xd002c000
CONFIG_TPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_TPL_RELOC_STACK=0xd0030000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_SPL_MAX_SIZE=0x18000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xd0018000
CONFIG_SPL_RELOC_TEXT_BASE=0xd0001000
CONFIG_SPL_RELOC_STACK=0xd001c000
CONFIG_SPL_RELOC_MALLOC=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000
CONFIG_SPL_RELOC_STACK=0xf8fbfff0
CONFIG_TPL_GD_ADDR=0xf8fac000
CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000
CONFIG_TPL_RELOC_STACK=0xf8fb0000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P1020RDB-PC_NAND_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000
CONFIG_SPL_RELOC_STACK=0xf8fbfff0
CONFIG_TPL_GD_ADDR=0xf8fac000
CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000
CONFIG_TPL_RELOC_STACK=0xf8fb0000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1020RDB-PC_SDCARD_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P1020RDB-PD_NAND_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xf8fbe000
CONFIG_SPL_RELOC_STACK=0xf8fbfff0
CONFIG_TPL_GD_ADDR=0xf8fac000
CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000
CONFIG_TPL_RELOC_STACK=0xf8fb0000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P1020RDB-PD_SDCARD_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000
CONFIG_SPL_RELOC_STACK=0xf8fffff0
CONFIG_TPL_GD_ADDR=0xf8fac000
CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000
CONFIG_TPL_RELOC_STACK=0xf8fb0000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P2020RDB-PC_NAND_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_INIT_MINIMAL=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_RELOC_TEXT_BASE=0xf8ffe000
CONFIG_SPL_RELOC_STACK=0xf8fffff0
CONFIG_TPL_GD_ADDR=0xf8fac000
CONFIG_TPL_RELOC_TEXT_BASE=0xf8f81000
CONFIG_TPL_RELOC_STACK=0xf8fb0000
CONFIG_TPL_RELOC_MALLOC=y

1
configs/P2020RDB-PC_SDCARD_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_GD_ADDR=0xf8f9c000
CONFIG_SPL_RELOC_STACK=0xf8f9d000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xf8fa5000

1
configs/T1024RDB_NAND_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T1024RDB_SDCARD_defconfig
View File

@ -40,6 +40,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T1024RDB_SPIFLASH_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T1042D4RDB_NAND_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T1042D4RDB_SDCARD_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T1042D4RDB_SPIFLASH_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080QDS_NAND_defconfig
View File

@ -40,6 +40,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080QDS_SDCARD_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080RDB_NAND_defconfig
View File

@ -38,6 +38,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080RDB_SDCARD_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080RDB_SPIFLASH_defconfig
View File

@ -42,6 +42,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080RDB_revD_NAND_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080RDB_revD_SDCARD_defconfig
View File

@ -40,6 +40,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T2080RDB_revD_SPIFLASH_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

1
configs/T4240RDB_SDCARD_defconfig
View File

@ -37,6 +37,7 @@ CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000

2
include/configs/P1010RDB.h
View File

@ -390,14 +390,12 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR

1
include/configs/T102xRDB.h
View File

@ -119,7 +119,6 @@
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CONFIG_SYS_L3_SIZE (256 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT

1
include/configs/T104xRDB.h
View File

@ -106,7 +106,6 @@
*/
#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
#define CONFIG_SYS_L3_SIZE 256 << 10
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000

1
include/configs/T208xQDS.h
View File

@ -92,7 +92,6 @@
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CONFIG_SYS_L3_SIZE (512 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000

1
include/configs/T208xRDB.h
View File

@ -87,7 +87,6 @@
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CONFIG_SYS_L3_SIZE (512 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000

1
include/configs/T4240RDB.h
View File

@ -67,7 +67,6 @@
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CONFIG_SYS_L3_SIZE (512 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000

4
include/configs/openpiton-riscv64.h
View File

@ -17,10 +17,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_BOOTM_LEN SZ_256M
#ifdef CONFIG_SPL
#define CONFIG_SPL_GD_ADDR 0x85000000
#endif
/* ---------------------------------------------------------------------
* Board boot configuration
*/

2
include/configs/p1_p2_rdb_pc.h
View File

@ -336,13 +336,11 @@
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR