clk: starfive: jh7110: Add security clocks
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
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"pcie1_tl", "stg_axiahb",
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OFFSET(JH7110_STGCLK_PCIE1_TL)));
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/* Security clocks */
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clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
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starfive_clk_gate(priv->reg,
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"sec_ahb", "stg_axiahb",
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OFFSET(JH7110_STGCLK_SEC_HCLK)));
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clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
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starfive_clk_gate(priv->reg,
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"sec_misc_ahb", "stg_axiahb",
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OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
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return 0;
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}
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