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Xilinx changes for v2022.01-rc1

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zynq:
 - Enable capsule update for qspi and mmc
 - Update zed DT qspi compatible string
 
 zynqmp:
 - Add missing modeboot for EMMC
 - Add missing nand DT properties
 - List all eeproms for SC on vck190
 - Add vck190 SC psu_init
 
 clk:
 - Handle only GATE type clock for Versal
 
 watchdog:
 - Update versal driver to handle system reset
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Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.01-rc1

zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string

zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init

clk:
- Handle only GATE type clock for Versal

watchdog:
- Update versal driver to handle system reset
This commit is contained in:
Tom Rini 2021-09-30 11:29:41 -04:00
commit 8bef036836
19 changed files with 2225 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.mailmap
View File

@ -33,6 +33,7 @@ Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Markus Klotzbuecher <mk@denx.de>
Nicolas Saenz Julienne <nsaenz@kernel.org> <nsaenzjulienne@suse.de>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>

4
arch/arm/dts/armada-8040.dtsi
View File

@ -40,7 +40,7 @@
};
&cp0_pinctl {
compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
bank-name ="cp0-110";
cp0_i2c0_pins: cp0-i2c-pins-0 {
@ -75,7 +75,7 @@
};
&cp1_pinctl {
compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cps-pinctrl";
bank-name ="cp1-110";
cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {

6
arch/arm/dts/imx7d-sdb.dts
View File

@ -44,9 +44,9 @@
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi4>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/dts/zynq-zed.dts
View File

@ -53,7 +53,7 @@
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "spansion,s25fl256s", "jedec,spi-nor";
compatible = "spansion,s25fl256s1", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
m25p,fast-read;

15
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View File

@ -24,6 +24,9 @@
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
nvmem1 = &eeprom_ebm;
nvmem2 = &eeprom_fmc1;
nvmem3 = &eeprom_fmc2;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
@ -477,6 +480,10 @@
silabs,skip-recall;
};
/* and connector J212D */
eeprom_ebm: eeprom@52 { /* x-ebm module */
compatible = "st,24c128", "atmel,24c128";
reg = <0x52>;
};
};
fmc1: i2c@1 { /* FMCP1_IIC */
#address-cells = <1>;
@ -484,6 +491,10 @@
reg = <1>;
/* FIXME connection to Samtec J51C */
/* expected eeprom 0x50 FMC cards */
eeprom_fmc1: eeprom@50 {
compatible = "st,24c128", "atmel,24c128";
reg = <0x50>;
};
};
fmc2: i2c@2 { /* FMCP2_IIC */
#address-cells = <1>;
@ -491,6 +502,10 @@
reg = <2>;
/* FIXME connection to Samtec J53C */
/* expected eeprom 0x50 FMC cards */
eeprom_fmc2: eeprom@50 {
compatible = "st,24c128", "atmel,24c128";
reg = <0x50>;
};
};
i2c@3 { /* DDR4_DIMM1 */
#address-cells = <1>;

4
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -140,6 +140,8 @@
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-0";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
@ -174,6 +176,8 @@
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-1";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";

6
arch/arm/mach-bcm283x/msg.c
View File

@ -170,6 +170,12 @@ int bcm2711_notify_vl805_reset(void)
ALLOC_CACHE_ALIGN_BUFFER(struct msg_notify_vl805_reset,
msg_notify_vl805_reset, 1);
int ret;
static int done = false;
if (done)
return 0;
done = true;
BCM2835_MBOX_INIT_HDR(msg_notify_vl805_reset);
BCM2835_MBOX_INIT_TAG(&msg_notify_vl805_reset->dev_addr,

35
board/xilinx/zynq/board.c
View File

@ -13,6 +13,7 @@
#include <fdtdec.h>
#include <fpga.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <watchdog.h>
#include <wdt.h>
@ -151,3 +152,37 @@ enum env_location env_get_location(enum env_operation op, int prio)
return ENVL_NOWHERE;
}
}
#if defined(CONFIG_SET_DFU_ALT_INFO)
#define DFU_ALT_BUF_LEN SZ_1K
void set_dfu_alt_info(char *interface, char *devstr)
{
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
if (env_get("dfu_alt_info"))
return;
memset(buf, 0, sizeof(buf));
switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
case ZYNQ_BM_SD:
snprintf(buf, DFU_ALT_BUF_LEN,
"mmc 0:1=boot.bin fat 0 1;"
"u-boot.img fat 0 1");
break;
case ZYNQ_BM_QSPI:
snprintf(buf, DFU_ALT_BUF_LEN,
"sf 0:0=boot.bin raw 0 0x1500000;"
"u-boot.img raw 0x%x 0x500000",
CONFIG_SYS_SPI_U_BOOT_OFFS);
break;
default:
return;
}
env_set("dfu_alt_info", buf);
puts("DFU alt info setting: done\n");
}
#endif

2052
board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/psu_init_gpl.c Normal file
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File diff suppressed because it is too large Load Diff

1
board/xilinx/zynqmp/zynqmp.c
View File

@ -672,6 +672,7 @@ int board_late_init(void)
mode = "mmc";
bootseq = dev_seq(dev);
env_set("modeboot", "emmcboot");
break;
case SD_MODE:
puts("SD_MODE\n");

6
configs/xilinx_zynq_virt_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
@ -70,6 +71,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
@ -122,3 +125,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
CONFIG_DISPLAY=y
CONFIG_SPL_GZIP=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y

5
drivers/clk/clk_versal.c
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@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[clk->id].clk_id;
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
if (versal_clock_gate(clk_id))
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
return 0;
}
static struct clk_ops versal_clk_ops = {

2
drivers/mtd/spi/Kconfig
View File

@ -57,7 +57,7 @@ config SF_DEFAULT_CS
config SF_DEFAULT_MODE
hex "SPI Flash default mode (see include/spi.h)"
depends on SPI_FLASH || DM_SPI_FLASH
default 3
default 0
help
The default mode may be provided by the platform
to handle the common case when only a single serial

17
drivers/mtd/spi/spi-nor-core.c
View File

@ -10,6 +10,7 @@
*/
#include <common.h>
#include <flash.h>
#include <log.h>
#include <watchdog.h>
#include <dm.h>
@ -26,6 +27,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/spi-nor.h>
#include <mtd/cfi_flash.h>
#include <spi-mem.h>
#include <spi.h>
@ -3664,6 +3666,11 @@ int spi_nor_scan(struct spi_nor *nor)
struct mtd_info *mtd = &nor->mtd;
struct spi_slave *spi = nor->spi;
int ret;
int cfi_mtd_nb = 0;
#ifdef CONFIG_SYS_MAX_FLASH_BANKS
cfi_mtd_nb = CONFIG_SYS_MAX_FLASH_BANKS;
#endif
/* Reset SPI protocol for all commands. */
nor->reg_proto = SNOR_PROTO_1_1_1;
@ -3715,8 +3722,12 @@ int spi_nor_scan(struct spi_nor *nor)
if (ret)
return ret;
if (!mtd->name)
mtd->name = info->name;
if (!mtd->name) {
sprintf(nor->mtd_name, "%s%d",
MTD_DEV_TYPE(MTD_DEV_TYPE_NOR),
cfi_mtd_nb + dev_seq(nor->dev));
mtd->name = nor->mtd_name;
}
mtd->dev = nor->dev;
mtd->priv = nor;
mtd->type = MTD_NORFLASH;
@ -3821,7 +3832,7 @@ int spi_nor_scan(struct spi_nor *nor)
nor->rdsr_dummy = params.rdsr_dummy;
nor->rdsr_addr_nbytes = params.rdsr_addr_nbytes;
nor->name = mtd->name;
nor->name = info->name;
nor->size = mtd->size;
nor->erase_size = mtd->erasesize;
nor->sector_size = mtd->erasesize;

100
drivers/watchdog/xilinx_wwdt.c
View File

@ -3,7 +3,7 @@
* Xilinx window watchdog timer driver.
*
* Author(s): Michal Simek <michal.simek@xilinx.com>
* Ashok Reddy Soma <ashokred@xilinx.com>
* Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
*
* Copyright (c) 2020, Xilinx Inc.
*/
@ -23,13 +23,22 @@
/* Generic Control/Status Register Masks */
#define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */
/* Register offsets for the Wdt device */
#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */
#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */
#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */
#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */
#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */
#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */
/* Register offsets for the WWDT device */
#define XWT_WWDT_MWR_OFFSET 0x00
#define XWT_WWDT_ESR_OFFSET 0x04
#define XWT_WWDT_FCR_OFFSET 0x08
#define XWT_WWDT_FWR_OFFSET 0x0c
#define XWT_WWDT_SWR_OFFSET 0x10
#define XWT_WWDT_CNT_MIN 1
#define XWT_WWDT_CNT_MAX 0xffffffff
/* Master Write Control Register Masks */
#define XWT_WWDT_MWR_MASK BIT(0)
/* Enable and Status Register Masks */
#define XWT_WWDT_ESR_WINT_MASK BIT(16)
#define XWT_WWDT_ESR_WSW_MASK BIT(8)
#define XWT_WWDT_ESR_WEN_MASK BIT(0)
struct xlnx_wwdt_priv {
bool enable_once;
@ -43,16 +52,23 @@ struct xlnx_wwdt_plat {
static int xlnx_wwdt_reset(struct udevice *dev)
{
u32 esr;
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK);
regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
esr |= XWT_WWDT_ESR_WINT_MASK;
esr &= ~XWT_WWDT_ESR_WSW_MASK;
regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
esr |= XWT_WWDT_ESR_WSW_MASK;
regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
return 0;
}
static int xlnx_wwdt_stop(struct udevice *dev)
{
u32 csr;
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
if (wdt->enable_once) {
@ -60,10 +76,9 @@ static int xlnx_wwdt_stop(struct udevice *dev)
return -EBUSY;
}
/* Disable the generic watchdog timer */
regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
csr &= ~(XWT_WWCSR_GWEN_MASK);
regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
/* Disable the window watchdog timer */
regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
clk_disable(&wdt->clk);
@ -72,11 +87,11 @@ static int xlnx_wwdt_stop(struct udevice *dev)
return 0;
}
static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
static int xlnx_wwdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
int ret;
u32 csr;
u64 count;
u32 esr;
u64 count, timeout;
unsigned long clock_f;
struct xlnx_wwdt_priv *wdt = dev_get_priv(dev);
@ -88,40 +103,52 @@ static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags)
dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f);
/* Convert timeout from msec to sec */
timeout = timeout_ms / 1000;
/* Calculate timeout count */
count = timeout * clock_f;
/* Count should be at least 1 */
if (count < XWT_WWDT_CNT_MIN) {
debug("%s: watchdog won't fire with 0 ticks\n", __func__);
count = XWT_WWDT_CNT_MIN;
}
/* Limit the count to maximum possible value */
if (count > XWT_WWDT_CNT_MAX) {
debug("%s: maximum watchdog timeout exceeded\n", __func__);
count = XWT_WWDT_CNT_MAX;
}
ret = clk_enable(&wdt->clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
/*
* Timeout count is half as there are two windows
* first window overflow is ignored (interrupt),
* reset is only generated at second window overflow
*/
count = count >> 1;
/* Disable the window watchdog timer */
regmap_write(wdt->regs, XWT_WWDT_MWR_OFFSET, XWT_WWDT_MWR_MASK);
regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, ~(u32)XWT_WWDT_ESR_WEN_MASK);
/* Disable the generic watchdog timer */
regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
csr &= ~(XWT_WWCSR_GWEN_MASK);
regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
/* Set first window and second window registers with timeout */
regmap_write(wdt->regs, XWT_WWDT_FWR_OFFSET, 0); /* No pre-timeout */
regmap_write(wdt->regs, XWT_WWDT_SWR_OFFSET, (u32)count);
regmap_write(wdt->regs, XWT_WWDT_FCR_OFFSET, 0);
/* Set compare and offset registers for generic watchdog timeout */
regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count);
regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0);
regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count);
/* Enable the generic watchdog timer */
regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr);
csr |= (XWT_WWCSR_GWEN_MASK);
regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr);
/* Enable the window watchdog timer */
regmap_read(wdt->regs, XWT_WWDT_ESR_OFFSET, &esr);
esr |= XWT_WWDT_ESR_WEN_MASK;
regmap_write(wdt->regs, XWT_WWDT_ESR_OFFSET, esr);
return 0;
}
static int xlnx_wwdt_expire_now(struct udevice *dev, ulong flags)
{
return xlnx_wwdt_start(dev, XWT_WWDT_CNT_MIN, flags);
}
static int xlnx_wwdt_probe(struct udevice *dev)
{
int ret;
@ -160,6 +187,7 @@ static const struct wdt_ops xlnx_wwdt_ops = {
.start = xlnx_wwdt_start,
.reset = xlnx_wwdt_reset,
.stop = xlnx_wwdt_stop,
.expire_now = xlnx_wwdt_expire_now,
};
static const struct udevice_id xlnx_wwdt_ids[] = {

3
include/dm/device.h
View File

@ -207,8 +207,9 @@ struct udevice_rt {
u32 flags_;
};
/* Maximum sequence number supported */
/* Maximum sequence number supported and associated string length */
#define DM_MAX_SEQ 999
#define DM_MAX_SEQ_STR 3
/* Returns the operations for a device */
#define device_get_ops(dev) (dev->driver->ops)

2
include/linux/mtd/spi-nor.h
View File

@ -7,6 +7,7 @@
#ifndef __LINUX_MTD_SPI_NOR_H
#define __LINUX_MTD_SPI_NOR_H
#include <mtd.h>
#include <linux/bitops.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/mtd.h>
@ -561,6 +562,7 @@ struct spi_nor {
int (*ready)(struct spi_nor *nor);
void *priv;
char mtd_name[MTD_NAME_SIZE(MTD_DEV_TYPE_NOR)];
/* Compatibility for spi_flash, remove once sf layer is merged with mtd */
const char *name;
u32 size;

5
include/mtd.h
View File

@ -6,10 +6,15 @@
#ifndef _MTD_H_
#define _MTD_H_
#include <dm/device.h>
#include <jffs2/load_kernel.h>
#include <linux/mtd/mtd.h>
int mtd_probe_devices(void);
void board_mtdparts_default(const char **mtdids, const char **mtdparts);
/* compute the max size for the string associated to a dev type */
#define MTD_NAME_SIZE(type) (sizeof(MTD_DEV_TYPE(type)) + DM_MAX_SEQ_STR)
#endif /* _MTD_H_ */

8
include/mtd/cfi_flash.h
View File

@ -157,11 +157,17 @@ struct cfi_pri_hdr {
* Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
*/
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks)
#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
/* map to cfi_flash_num_flash_banks only when supported */
#if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \
(!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD_SUPPORT))
#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks)
/* board code can update this variable before CFI detection */
extern int cfi_flash_num_flash_banks;
#else
#define CONFIG_SYS_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
#endif
#else
#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
#endif