clk: starfive: jh7110: Add watchdog clocks
Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev)
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starfive_clk_gate(priv->reg,
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"i2c5_apb", "apb0",
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OFFSET(JH7110_SYSCLK_I2C5_APB)));
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/* Watchdog clocks */
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clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
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starfive_clk_gate(priv->reg,
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"wdt_apb", "apb0",
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OFFSET(JH7110_SYSCLK_WDT_APB)));
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clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
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starfive_clk_gate(priv->reg,
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"wdt_core", "oscillator",
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OFFSET(JH7110_SYSCLK_WDT_CORE)));
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/* enable noc_bus_stg_axi clock */
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if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
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