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imx: cx9020: migrate cx9020 to CONFIG_DM_ETH

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Acked-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
This commit is contained in:
Steffen Dirkwinkel 2019-10-23 07:40:40 +02:00 committed by Stefano Babic
parent d98929d636
commit 9c2b1b0f03
3 changed files with 22 additions and 15 deletions
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31
arch/arm/dts/imx53-cx9020.dts
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@ -99,17 +99,6 @@
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
@ -148,6 +137,21 @@
>;
};
pinctrl_fec0: fec0grp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
@ -209,5 +213,10 @@
pinctrl-names = "default";
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
pinctrl-0 = <&pinctrl_fec0>;
status = "okay";
fixed-link { /* RMII fixed link to KZ8863 */
speed = <100>;
full-duplex;
};
};

2
configs/mx53cx9020_defconfig
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@ -31,8 +31,10 @@ CONFIG_FPGA_CYCLON2=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_ETH=y
CONFIG_MTD=y
CONFIG_FEC_MXC=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y

4
include/configs/mx53cx9020.h
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@ -35,10 +35,6 @@
/* bootz: zImage/initrd.img support */
/* Eth Configs */
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1