imx: imx8mm: Add support for Kontron Electronics SL/BL i.MX8M-Mini boards (N801x)
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC. The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2.0, HDMI/LVDS, SD card, CAN, RS485 and much more. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
This commit is contained in:
Frieder Schrempf
Stefano Babic
parent
23ce06b246
commit
9cab87f184
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@ -872,6 +872,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-evk.dtb \
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imx8mm-icore-mx8mm-ctouch2.dtb \
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imx8mm-icore-mx8mm-edimm2.2.dtb \
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imx8mm-kontron-n801x-s.dtb \
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imx8mm-kontron-n801x-s-lvds.dtb \
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imx8mm-venice.dtb \
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imx8mm-venice-gw71xx-0x.dtb \
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imx8mm-venice-gw72xx-0x.dtb \
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116
arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts
Normal file
116
arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts
Normal file
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@ -0,0 +1,116 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Kontron Electronics GmbH
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*/
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#include "imx8mm-kontron-n801x-s.dts"
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/ {
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model = "Kontron i.MX8MM N801X S LVDS";
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compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
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power-supply = <®_vdd_24v>;
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brightness-levels = <0 100>;
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num-interpolated-steps = <100>;
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default-brightness-level = <100>;
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status = "okay";
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};
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reg_panel_pwr: regpanel-pwr {
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compatible = "regulator-fixed";
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regulator-name = "reg_panel_pwr";
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regulator-always-on;
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gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_panel_rst: regpanel-rst {
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compatible = "regulator-fixed";
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regulator-name = "reg_panel_rst";
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regulator-always-on;
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gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_panel_stby: regpanel-stby {
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compatible = "regulator-fixed";
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regulator-name = "reg_panel_stby";
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regulator-always-on;
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gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_panel_hinv: regpanel-hinv {
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compatible = "regulator-fixed";
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regulator-name = "reg_panel_hinv";
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regulator-always-on;
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gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_panel_vinv: regpanel-vinv {
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compatible = "regulator-fixed";
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regulator-name = "reg_panel_vinv";
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gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_vdd_24v: regulator-24v {
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compatible = "regulator-fixed";
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regulator-name = "reg-vdd-24v";
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regulator-min-microvolt = <24000000>;
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regulator-max-microvolt = <24000000>;
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regulator-boot-on;
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regulator-always-on;
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status = "okay";
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};
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};
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&i2c2 {
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status = "okay";
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gt911@5d {
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compatible = "goodix,gt928";
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reg = <0x5d>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_touch>;
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interrupt-parent = <&gpio3>;
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interrupts = <22 8>;
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reset-gpios = <&gpio3 23 0>;
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irq-gpios = <&gpio3 22 0>;
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};
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_panel: panelgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
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MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
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MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
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MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
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MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
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>;
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};
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pinctrl_pwm1: pwm1grp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
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>;
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};
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pinctrl_touch: touchgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
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MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
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>;
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};
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};
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274
arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi
Normal file
274
arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi
Normal file
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@ -0,0 +1,274 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Kontron Electronics GmbH
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*/
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#include "imx8mm-u-boot.dtsi"
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/ {
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aliases {
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usb0 = &usbotg1;
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usb1 = &usbotg2;
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};
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binman: binman {
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multiple-images;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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u-boot,dm-spl;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&fec1 {
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phy-mode = "rgmii-rxid";
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};
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&i2c1 {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&i2c2 {
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status = "okay";
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&pinctrl_ecspi1 {
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u-boot,dm-spl;
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};
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&pinctrl_i2c1 {
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u-boot,dm-spl;
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};
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&pinctrl_pmic {
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u-boot,dm-spl;
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
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/* Disable Pullup for SD_VSEL */
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MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
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>;
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};
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&pinctrl_uart3 {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&pinctrl_usdhc1 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc1_100mhz {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc1_200mhz {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2 {
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u-boot,dm-spl;
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};
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&pca9450 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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u-boot,dm-spl;
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};
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&ecspi1 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&uart3 {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&usdhc1 {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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};
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&wdog1 {
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u-boot,dm-spl;
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};
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&binman {
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u-boot-spl-ddr {
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filename = "u-boot-spl-ddr.bin";
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pad-byte = <0xff>;
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align-size = <4>;
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align = <4>;
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u-boot-spl {
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align-end = <4>;
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};
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blob_1: blob-ext@1 {
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filename = "lpddr4_pmu_train_1d_imem.bin";
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size = <0x8000>;
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};
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blob_2: blob-ext@2 {
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filename = "lpddr4_pmu_train_1d_dmem.bin";
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size = <0x4000>;
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};
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blob_3: blob-ext@3 {
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filename = "lpddr4_pmu_train_2d_imem.bin";
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size = <0x8000>;
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};
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blob_4: blob-ext@4 {
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filename = "lpddr4_pmu_train_2d_dmem.bin";
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size = <0x4000>;
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};
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};
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spl {
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filename = "spl.bin";
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mkimage {
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args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
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blob {
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filename = "u-boot-spl-ddr.bin";
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};
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};
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};
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itb {
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filename = "u-boot.itb";
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fit {
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description = "Configuration to load ATF before U-Boot";
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#address-cells = <1>;
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fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
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images {
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uboot {
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description = "U-Boot (64-bit)";
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type = "standalone";
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arch = "arm64";
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compression = "none";
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load = <CONFIG_SYS_TEXT_BASE>;
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uboot_blob: blob-ext {
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filename = "u-boot-nodtb.bin";
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};
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};
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atf {
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description = "ARM Trusted Firmware";
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type = "firmware";
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arch = "arm64";
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compression = "none";
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load = <0x920000>;
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entry = <0x920000>;
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atf_blob: blob-ext {
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filename = "bl31.bin";
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};
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};
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fdt {
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description = "NAME";
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type = "flat_dt";
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compression = "none";
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uboot_fdt_blob: blob-ext {
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filename = "u-boot.dtb";
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};
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};
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};
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configurations {
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default = "conf";
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conf {
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description = "NAME";
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firmware = "uboot";
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loadables = "atf";
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fdt = "fdt";
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};
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};
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};
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};
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imx-boot {
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filename = "flash.bin";
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pad-byte = <0x00>;
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spl: blob-ext@1 {
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offset = <0x0>;
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filename = "spl.bin";
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};
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uboot: blob-ext@2 {
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offset = <0x57c00>;
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filename = "u-boot.itb";
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};
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};
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u-boot-update {
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filename = "firmware-update.itb";
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fit {
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description = "Configuration for firmware update file";
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images {
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flash-bin {
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description = "U-Boot flash image";
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type = "firmware";
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os = "u-boot";
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arch = "arm";
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compress = "none";
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load = <0>; /* unused */
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blob {
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filename = "flash.bin";
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};
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};
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};
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};
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};
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};
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388
arch/arm/dts/imx8mm-kontron-n801x-s.dts
Normal file
388
arch/arm/dts/imx8mm-kontron-n801x-s.dts
Normal file
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@ -0,0 +1,388 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright (C) 2019 Kontron Electronics GmbH
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*/
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/dts-v1/;
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#include "imx8mm-kontron-n801x-som.dtsi"
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#include <dt-bindings/net/mscc-phy-vsc8531.h>
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/ {
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model = "Kontron i.MX8MM N801X S";
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compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
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aliases {
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ethernet1 = &usbnet;
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};
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/* fixed crystal dedicated to mcp2515 */
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osc_can: clock-osc-can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <16000000>;
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clock-output-names = "osc-can";
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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led1 {
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label = "led1";
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gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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led2 {
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label = "led2";
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gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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};
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led3 {
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label = "led3";
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gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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};
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led4 {
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label = "led4";
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gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
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};
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led5 {
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label = "led5";
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gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
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};
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led6 {
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label = "led6";
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gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
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};
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};
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pwm-beeper {
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compatible = "pwm-beeper";
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pwms = <&pwm2 0 5000 0>;
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};
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reg_rst_eth2: regulator-rst-eth2 {
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compatible = "regulator-fixed";
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regulator-name = "rst-usb-eth2";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_eth2>;
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gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_vdd_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "vdd-5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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can0: can@0 {
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compatible = "microchip,mcp2515";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can>;
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clocks = <&osc_can>;
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interrupt-parent = <&gpio4>;
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interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
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spi-max-frequency = <10000000>;
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vdd-supply = <®_vdd_3v3>;
|
||||
xceiver-supply = <®_vdd_5v>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi3>;
|
||||
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-connection-type = "rgmii-rxid";
|
||||
phy-handle = <ðphy>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0007.0570";
|
||||
reg = <0>;
|
||||
reset-assert-us = <100>;
|
||||
reset-deassert-us = <100>;
|
||||
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
|
||||
vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
|
||||
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
|
||||
vsc8531,led-0-combine-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
dsi_mux_sel: dsi_mux_sel {
|
||||
gpio-hog;
|
||||
gpios = <14 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "dsi-mux-sel";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dsi_sel>;
|
||||
};
|
||||
|
||||
dsi_mux_oe {
|
||||
gpio-hog;
|
||||
gpios = <15 GPIO_ACTIVE_LOW>;
|
||||
output-high;
|
||||
line-name = "dsi-mux-oe";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dsi_oe>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
status = "okay";
|
||||
|
||||
rtc@32 {
|
||||
compatible = "epson,rx8900";
|
||||
reg = <0x32>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "otg";
|
||||
over-current-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
usb1@1 {
|
||||
compatible = "usb424,9514";
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usbnet: usbether@1 {
|
||||
compatible = "usb424,ec00";
|
||||
reg = <1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
vmmc-supply = <®_vdd_3v3>;
|
||||
vqmmc-supply = <®_nvcc_sd>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio>;
|
||||
|
||||
pinctrl_can: cangrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_dsi_sel: dsiselgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_dsi_oe: dsioegrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
|
||||
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
|
||||
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
|
||||
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
|
||||
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
|
||||
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
|
||||
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
|
||||
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_led: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
|
||||
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
|
||||
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
|
||||
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
|
||||
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
|
||||
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
|
||||
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio: gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
|
||||
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
|
||||
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
|
||||
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_eth2: usbeth2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
|
||||
>;
|
||||
};
|
||||
};
|
||||
299
arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
Normal file
299
arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
Normal file
|
|
@ -0,0 +1,299 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR MIT
|
||||
/*
|
||||
* Copyright (C) 2019 Kontron Electronics GmbH
|
||||
*/
|
||||
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron i.MX8MM N801X SoM";
|
||||
compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
/*
|
||||
* There are multiple SoM flavors with different DDR sizes.
|
||||
* The smallest is 1GB. For larger sizes the bootloader will
|
||||
* update the reg property.
|
||||
*/
|
||||
reg = <0x0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart3;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <®_vdd_arm>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <®_vdd_arm>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <®_vdd_arm>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <®_vdd_arm>;
|
||||
};
|
||||
|
||||
&ddrc {
|
||||
operating-points-v2 = <&ddrc_opp_table>;
|
||||
|
||||
ddrc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-25M {
|
||||
opp-hz = /bits/ 64 <25000000>;
|
||||
};
|
||||
|
||||
opp-100M {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
|
||||
opp-750M {
|
||||
opp-hz = /bits/ 64 <750000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
|
||||
spi-max-frequency = <80000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pca9450: pmic@25 {
|
||||
compatible = "nxp,pca9450a";
|
||||
reg = <0x25>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
regulators {
|
||||
reg_vdd_soc: BUCK1 {
|
||||
regulator-name = "buck1";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <850000>;
|
||||
nxp,dvs-standby-voltage = <800000>;
|
||||
};
|
||||
|
||||
reg_vdd_arm: BUCK2 {
|
||||
regulator-name = "buck2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
|
||||
reg_vdd_dram: BUCK3 {
|
||||
regulator-name = "buck3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_3v3: BUCK4 {
|
||||
regulator-name = "buck4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_1v8: BUCK5 {
|
||||
regulator-name = "buck5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_nvcc_dram: BUCK6 {
|
||||
regulator-name = "buck6";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_nvcc_snvs: LDO1 {
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_snvs: LDO2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdda: LDO3 {
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_phy: LDO4 {
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_nvcc_sd: LDO5 {
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart3 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
vmmc-supply = <®_vdd_3v3>;
|
||||
vqmmc-supply = <®_vdd_1v8>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
|
||||
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
@ -75,6 +75,13 @@ config TARGET_IMX8MM_VENICE
|
|||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_KONTRON_MX8MM
|
||||
bool "Kontron Electronics N80xx"
|
||||
select BINMAN
|
||||
select IMX8MM
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MN_EVK
|
||||
bool "imx8mn LPDDR4 EVK board"
|
||||
select BINMAN
|
||||
|
|
@ -157,6 +164,7 @@ source "board/freescale/imx8mn_evk/Kconfig"
|
|||
source "board/freescale/imx8mp_evk/Kconfig"
|
||||
source "board/gateworks/venice/Kconfig"
|
||||
source "board/google/imx8mq_phanbell/Kconfig"
|
||||
source "board/kontron/sl-mx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mp/Kconfig"
|
||||
source "board/ronetix/imx8mq-cm/Kconfig"
|
||||
|
|
|
|||
15
board/kontron/sl-mx8mm/Kconfig
Normal file
15
board/kontron/sl-mx8mm/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_KONTRON_MX8MM
|
||||
|
||||
config SYS_BOARD
|
||||
string
|
||||
default "sl-mx8mm"
|
||||
|
||||
config SYS_VENDOR
|
||||
string
|
||||
default "kontron"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
string
|
||||
default "kontron-sl-mx8mm"
|
||||
|
||||
endif
|
||||
8
board/kontron/sl-mx8mm/MAINTAINERS
Normal file
8
board/kontron/sl-mx8mm/MAINTAINERS
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
Kontron SL/BL i.MX8M Mini Boards (N801x)
|
||||
M: Frieder Schrempf <frieder.schrempf@kontron.de>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/imx8mm-kontron-n801x-*
|
||||
F: board/kontron/sl-mx8mm
|
||||
F: configs/kontron-sl-mx8mm_defconfig
|
||||
F: doc/board/kontron/sl-mx8mm.rst
|
||||
F: include/configs/kontron-sl-mx8mm.h
|
||||
9
board/kontron/sl-mx8mm/Makefile
Normal file
9
board/kontron/sl-mx8mm/Makefile
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
# (C) Copyright 2019 Kontron Electronics GmbH
|
||||
|
||||
obj-y := sl-mx8mm.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
9
board/kontron/sl-mx8mm/imximage.cfg
Normal file
9
board/kontron/sl-mx8mm/imximage.cfg
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Kontron Electronics GmbH
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
|
||||
BOOT_FROM sd
|
||||
LOADER u-boot-spl-ddr.bin 0x7E1000
|
||||
1844
board/kontron/sl-mx8mm/lpddr4_timing.c
Normal file
1844
board/kontron/sl-mx8mm/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load Diff
99
board/kontron/sl-mx8mm/sl-mx8mm.c
Normal file
99
board/kontron/sl-mx8mm/sl-mx8mm.c
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Kontron Electronics GmbH
|
||||
*/
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <fdt_support.h>
|
||||
#include <linux/errno.h>
|
||||
#include <net.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_phys_sdram_size(phys_size_t *size)
|
||||
{
|
||||
u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
|
||||
|
||||
if (ddr_size == 4) {
|
||||
*size = 0x100000000;
|
||||
} else if (ddr_size == 3) {
|
||||
*size = 0xc0000000;
|
||||
} else if (ddr_size == 2) {
|
||||
*size = 0x80000000;
|
||||
} else if (ddr_size == 1) {
|
||||
*size = 0x40000000;
|
||||
} else {
|
||||
printf("Unknown DDR type!!!\n");
|
||||
*size = 0x40000000;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the SoM is mounted on a baseboard with a USB ethernet controller,
|
||||
* there might be an additional MAC address programmed to the MAC OTP fuses.
|
||||
* Although the i.MX8MM has only one MAC, the MAC0, MAC1 and MAC2 registers
|
||||
* in the OTP fuses can still be used to store two separate addresses.
|
||||
* Try to read the secondary address from MAC1 and MAC2 and adjust the
|
||||
* devicetree so Linux can pick up the MAC address.
|
||||
*/
|
||||
int fdt_set_usb_eth_addr(void *blob)
|
||||
{
|
||||
u32 value = readl(OCOTP_BASE_ADDR + 0x660);
|
||||
unsigned char mac[6];
|
||||
int node, ret;
|
||||
|
||||
mac[0] = value >> 24;
|
||||
mac[1] = value >> 16;
|
||||
mac[2] = value >> 8;
|
||||
mac[3] = value;
|
||||
|
||||
value = readl(OCOTP_BASE_ADDR + 0x650);
|
||||
mac[4] = value >> 24;
|
||||
mac[5] = value >> 16;
|
||||
|
||||
node = fdt_path_offset(blob, fdt_get_alias(blob, "ethernet1"));
|
||||
if (node < 0) {
|
||||
/*
|
||||
* There is no node for the USB ethernet in the devicetree. Just skip.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (is_zero_ethaddr(mac)) {
|
||||
printf("\nNo MAC address for USB ethernet set in OTP fuses!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!is_valid_ethaddr(mac)) {
|
||||
printf("\nInvalid MAC address for USB ethernet set in OTP fuses!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fdt_setprop(blob, node, "local-mac-address", &mac, 6);
|
||||
if (ret)
|
||||
ret = fdt_setprop(blob, node, "mac-address", &mac, 6);
|
||||
|
||||
if (ret)
|
||||
printf("\nMissing mac-address or local-mac-address property in dt, skip setting MAC address for USB ethernet\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
int ret = fdt_set_usb_eth_addr(blob);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
321
board/kontron/sl-mx8mm/spl.c
Normal file
321
board/kontron/sl-mx8mm/spl.c
Normal file
|
|
@ -0,0 +1,321 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2019 Kontron Electronics GmbH
|
||||
*/
|
||||
|
||||
#include <asm/arch/imx8mm_pins.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <hang.h>
|
||||
#include <i2c.h>
|
||||
#include <init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/pca9450.h>
|
||||
#include <power/pmic.h>
|
||||
#include <spl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
enum {
|
||||
BOARD_TYPE_KTN_N801X,
|
||||
BOARD_TYPE_KTN_N801X_LVDS,
|
||||
BOARD_TYPE_MAX
|
||||
};
|
||||
|
||||
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
||||
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
|
||||
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
|
||||
|
||||
static iomux_v3_cfg_t const i2c1_pads[] = {
|
||||
IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
|
||||
IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const i2c2_pads[] = {
|
||||
IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
|
||||
IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const touch_gpio[] = {
|
||||
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = {
|
||||
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
||||
};
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
switch (boot_dev_spl) {
|
||||
case USB_BOOT:
|
||||
return BOOT_DEVICE_BOARD;
|
||||
case SPI_NOR_BOOT:
|
||||
return BOOT_DEVICE_SPI;
|
||||
case SD1_BOOT:
|
||||
case MMC1_BOOT:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
case SD2_BOOT:
|
||||
case MMC2_BOOT:
|
||||
return BOOT_DEVICE_MMC2;
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
bool check_ram_available(long size)
|
||||
{
|
||||
long sz = get_ram_size((long *)PHYS_SDRAM, size);
|
||||
|
||||
if (sz == size)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
u32 size = 0;
|
||||
|
||||
/*
|
||||
* Try the default DDR settings in lpddr4_timing.c to
|
||||
* comply with the Micron 4GB DDR.
|
||||
*/
|
||||
if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) {
|
||||
size = 4;
|
||||
} else {
|
||||
/*
|
||||
* Overwrite some values to comply with the Micron 1GB/2GB DDRs.
|
||||
*/
|
||||
dram_timing.ddrc_cfg[2].val = 0xa1080020;
|
||||
dram_timing.ddrc_cfg[37].val = 0x1f;
|
||||
|
||||
dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
|
||||
dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
|
||||
dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
|
||||
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
|
||||
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
|
||||
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
|
||||
dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
|
||||
dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
|
||||
|
||||
if (!ddr_init(&dram_timing)) {
|
||||
if (check_ram_available(SZ_2G))
|
||||
size = 2;
|
||||
else if (check_ram_available(SZ_1G))
|
||||
size = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (size == 0) {
|
||||
printf("Failed to initialize DDR RAM!\n");
|
||||
size = 1;
|
||||
}
|
||||
|
||||
printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
|
||||
writel(size, M4_BOOTROM_BASE_ADDR);
|
||||
}
|
||||
|
||||
static void touch_reset(void)
|
||||
{
|
||||
/*
|
||||
* Toggle the reset of the touch panel.
|
||||
*/
|
||||
imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
|
||||
|
||||
gpio_request(TOUCH_RESET_GPIO, "touch_reset");
|
||||
gpio_direction_output(TOUCH_RESET_GPIO, 0);
|
||||
mdelay(20);
|
||||
gpio_direction_output(TOUCH_RESET_GPIO, 1);
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
static int i2c_detect(u8 bus, u16 addr)
|
||||
{
|
||||
struct udevice *udev;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Try to probe the touch controller to check if an LVDS panel is
|
||||
* connected.
|
||||
*/
|
||||
ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
|
||||
if (ret == 0)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int do_board_detect(void)
|
||||
{
|
||||
bool lvds = false;
|
||||
|
||||
/*
|
||||
* Check the I2C touch controller to detect a LVDS panel.
|
||||
*/
|
||||
imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
|
||||
touch_reset();
|
||||
|
||||
if (i2c_detect(1, 0x5d) == 0) {
|
||||
printf("Touch controller detected, assuming LVDS panel...\n");
|
||||
lvds = true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check the I2C PMIC to detect the deprecated SoM with DA9063.
|
||||
*/
|
||||
imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
|
||||
|
||||
if (i2c_detect(0, 0x58) == 0) {
|
||||
printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
|
||||
printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
|
||||
printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
|
||||
}
|
||||
|
||||
if (lvds)
|
||||
gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
|
||||
else
|
||||
gd->board_type = BOARD_TYPE_KTN_N801X;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
|
||||
!strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
|
||||
return 0;
|
||||
|
||||
if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
|
||||
!strncmp(name, "imx8mm-kontron-n801x-s", 22))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
puts("Normal Boot\n");
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_CLK,
|
||||
"clock-controller@30380000",
|
||||
&dev);
|
||||
if (ret < 0)
|
||||
printf("Failed to find clock node. Check device tree\n");
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret = pmic_get("pmic@25", &dev);
|
||||
|
||||
if (ret == -ENODEV)
|
||||
puts("No pmic found\n");
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
|
||||
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/* increase VDD_DRAM to 0.95V for 1.5GHz DDR */
|
||||
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
|
||||
|
||||
/* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
|
||||
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
|
||||
|
||||
/* set WDOG_B_CFG to cold reset */
|
||||
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(2);
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
ret = spl_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
/* PMIC initialization */
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* Detect the board type */
|
||||
do_board_detect();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
u32 bootdev = spl_boot_device();
|
||||
|
||||
/*
|
||||
* The default boot fuse settings use the SD card (MMC2) as primary
|
||||
* boot device, but allow SPI NOR as a fallback boot device.
|
||||
* We can't detect the fallback case and spl_boot_device() will return
|
||||
* BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
|
||||
* Therefore we try to load U-Boot proper vom SPI NOR after loading
|
||||
* from MMC has failed.
|
||||
*/
|
||||
spl_boot_list[0] = bootdev;
|
||||
|
||||
switch (bootdev) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
case BOOT_DEVICE_MMC2:
|
||||
spl_boot_list[1] = BOOT_DEVICE_SPI;
|
||||
break;
|
||||
}
|
||||
}
|
||||
140
configs/kontron-sl-mx8mm_defconfig
Normal file
140
configs/kontron-sl-mx8mm_defconfig
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x1f0000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
|
||||
CONFIG_SPL_TEXT_BASE=0x7E1000
|
||||
CONFIG_TARGET_KONTRON_MX8MM=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kontron/sl-mx8mm/imximage.cfg"
|
||||
CONFIG_BOARD_TYPES=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
# CONFIG_SPL_FIT_IMAGE_TINY is not set
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_DM_SPI_FLASH=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
# CONFIG_CMD_LZMADEC is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_WDT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_RTC=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_BUS=y
|
||||
CONFIG_ENV_SPI_BUS=0
|
||||
CONFIG_USE_ENV_SPI_MAX_HZ=y
|
||||
CONFIG_ENV_SPI_MAX_HZ=80000000
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_BOOTCOUNT_ENV=y
|
||||
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_SPL_CLK_IMX8MM=y
|
||||
CONFIG_CLK_IMX8MM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=80000000
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MSCC=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DM_ETH_PHY=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_DM_PMIC_PCA9450=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_RV8803=y
|
||||
CONFIG_CONS_INDEX=2
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MXC_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_TMU=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
# CONFIG_WATCHDOG_AUTOSTART is not set
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
# CONFIG_HEXDUMP is not set
|
||||
CONFIG_EFI_SET_TIME=y
|
||||
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
|
||||
CONFIG_EFI_CAPSULE_ON_DISK=y
|
||||
CONFIG_EFI_IGNORE_OSINDICATIONS=y
|
||||
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
|
||||
|
|
@ -8,3 +8,4 @@ Kontron
|
|||
|
||||
sl28
|
||||
sl-mx6ul
|
||||
sl-mx8mm
|
||||
|
|
|
|||
85
doc/board/kontron/sl-mx8mm.rst
Normal file
85
doc/board/kontron/sl-mx8mm.rst
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Kontron Electronics SL i.MX8MM SoM
|
||||
==================================
|
||||
|
||||
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module
|
||||
with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
|
||||
|
||||
The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
|
||||
HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Get and Build the Trusted Firmware-A (TF-A)
|
||||
- Get the DDR firmware
|
||||
- Build U-Boot
|
||||
- Boot
|
||||
|
||||
Get and Build the Trusted Firmware-A (TF-A)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Note: builddir is U-Boot build directory (source directory for in-tree builds)
|
||||
|
||||
There are two sources for the TF-A. Mainline and NXP. Get the one you prefer
|
||||
(support and features might differ).
|
||||
|
||||
**NXP's imx-atf**
|
||||
|
||||
1. Get TF-A from: https://source.codeaurora.org/external/imx/imx-atf, branch: imx_5.4.70_2.3.0
|
||||
2. Apply the patch to select the correct UART for the console, otherwise the TF-A will lock up during boot.
|
||||
3. Build
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ make PLAT=imx8mm bl31
|
||||
$ cp build/imx8mm/release/bl31.bin $(builddir)
|
||||
|
||||
**Mainline TF-A**
|
||||
|
||||
1. Get TF-A from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/, tag: v2.4
|
||||
2. Build
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- IMX_BOOT_UART_BASE="0x30880000" bl31
|
||||
$ cp build/imx8mm/release/bl31.bin $(builddir)
|
||||
|
||||
Get the DDR firmware
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9.bin
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
^^^^^^^^^^^^
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ make kontron-sl-mx8mm_defconfig
|
||||
$ export ATF_LOAD_ADDR=0x920000
|
||||
$ make
|
||||
|
||||
Burn the flash.bin to SD card at an offset of 33 KiB:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 conv=notrunc
|
||||
|
||||
Boot
|
||||
^^^^
|
||||
|
||||
Put the SD card in the slot on the board and apply power.
|
||||
|
||||
Further Information
|
||||
-------------------
|
||||
|
||||
The bootloader configuration is setup to be used with kernel FIT images. Legacy
|
||||
images might not be working out of the box.
|
||||
|
||||
Please see https://docs.kontron-electronics.de for further vendor documentation.
|
||||
87
include/configs/kontron-sl-mx8mm.h
Normal file
87
include/configs/kontron-sl-mx8mm.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2019 Kontron Electronics GmbH
|
||||
*
|
||||
* Configuration settings for the Kontron SL/BL i.MX8M-Mini boards and modules (N81xx).
|
||||
*/
|
||||
#ifndef __KONTRON_MX8MM_CONFIG_H
|
||||
#define __KONTRON_MX8MM_CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <config.h>
|
||||
#endif
|
||||
|
||||
/* RAM */
|
||||
#define PHYS_SDRAM DDR_CSD1_BASE_ADDR
|
||||
#define PHYS_SDRAM_SIZE (SZ_4G)
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_64M
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Board and environment settings */
|
||||
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
|
||||
#define CONFIG_HOSTNAME "kontron-mx8mm"
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(PXE, pxe, na)
|
||||
#include <config_distro_bootcmd.h>
|
||||
/* Do not try to probe USB net adapters for net boot */
|
||||
#undef BOOTENV_RUN_NET_USB_START
|
||||
#define BOOTENV_RUN_NET_USB_START
|
||||
#else
|
||||
#define BOOTENV
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_64M
|
||||
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
|
||||
#define CONFIG_FSL_USDHC
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_STACK 0x91fff0
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x910000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
|
||||
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
||||
#define CONFIG_MALLOC_F_ADDR 0x930000
|
||||
#endif
|
||||
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"kernel_addr_r=0x42000000\0" \
|
||||
"fdt_addr_r=0x44000000\0" \
|
||||
"ramdisk_addr_r=0x46400000\0" \
|
||||
"pxefile_addr_r=0x46000000\0" \
|
||||
"scriptaddr=0x46000000\0" \
|
||||
"dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \
|
||||
"bootdelay=3\0" \
|
||||
"hostname=" CONFIG_HOSTNAME "\0" \
|
||||
BOOTENV
|
||||
|
||||
#endif /* __KONTRON_MX8MM_CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user