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ARM: dts: stm32mp15: update DDR node

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Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.

With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c ("ram:
stm32mp1: compute DDR size from DDRCTL registers").

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay 2022-09-21 09:37:13 +02:00 committed by Patrice Chotard
parent 86d5a06ae3
commit 9f7c58dc0d
4 changed files with 16 additions and 16 deletions
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16
arch/arm/dts/stm32mp15-ddr.dtsi
View File

@ -4,7 +4,22 @@
*/
#include <linux/stringify.h>
#ifdef CONFIG_SPL
&ddr {
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
config-DDR_MEM_COMPATIBLE {
u-boot,dm-pre-reloc;
@ -119,6 +134,7 @@
status = "okay";
};
};
#endif
#undef DDR_MEM_COMPATIBLE
#undef DDR_MEM_NAME

14
arch/arm/dts/stm32mp15-u-boot.dtsi
View File

@ -53,20 +53,6 @@
reg = <0x5a003000 0x550
0x5a004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
};

1
arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
View File

@ -5,7 +5,6 @@
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-scmi-u-boot.dtsi"
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
aliases {

1
arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
View File

@ -5,7 +5,6 @@
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-scmi-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {