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riscv: Rename Andes PLIC to PLICSW

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As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Yu Chien Peter Lin 2022-10-25 23:03:50 +08:00 committed by Leo Yu-Chi Liang
parent c8d9ff634f
commit a5dfa3b8a0
10 changed files with 29 additions and 29 deletions
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6
arch/riscv/Kconfig
View File

@ -199,7 +199,7 @@ config SIFIVE_CACHE
help
This enables the operations to configure SiFive cache
config ANDES_PLIC
config ANDES_PLICSW
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
@ -207,8 +207,8 @@ config ANDES_PLIC
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
help
The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt.
The Andes PLICSW block holds memory-mapped claim and pending
registers associated with software interrupt.
config SMP
bool "Symmetric Multi-Processing"

2
arch/riscv/cpu/ax25/Kconfig
View File

@ -4,7 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply SPL_CPU
imply SPL_OPENSBI

2
arch/riscv/dts/ae350-u-boot.dtsi
View File

@ -36,7 +36,7 @@
soc {
u-boot,dm-spl;
plic1: interrupt-controller@e6400000 {
plicsw: interrupt-controller@e6400000 {
u-boot,dm-spl;
};

6
arch/riscv/dts/ae350_32.dts
View File

@ -146,8 +146,8 @@
&CPU3_intc 11 &CPU3_intc 9>;
};
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe6400000 0x400000>;
@ -159,7 +159,7 @@
};
plmt0@e6000000 {
compatible = "riscv,plmt0";
compatible = "andestech,plmt0";
interrupts-extended = <&CPU0_intc 7
&CPU1_intc 7
&CPU2_intc 7

6
arch/riscv/dts/ae350_64.dts
View File

@ -146,8 +146,8 @@
&CPU3_intc 11 &CPU3_intc 9>;
};
plic1: interrupt-controller@e6400000 {
compatible = "riscv,plic1";
plicsw: interrupt-controller@e6400000 {
compatible = "andestech,plicsw";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;
@ -159,7 +159,7 @@
};
plmt0@e6000000 {
compatible = "riscv,plmt0";
compatible = "andestech,plmt0";
interrupts-extended = <&CPU0_intc 7
&CPU1_intc 7
&CPU2_intc 7

4
arch/riscv/include/asm/global_data.h
View File

@ -21,8 +21,8 @@ struct arch_global_data {
#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
void __iomem *clint; /* clint base address */
#endif
#ifdef CONFIG_ANDES_PLIC
void __iomem *plic; /* plic base address */
#ifdef CONFIG_ANDES_PLICSW
void __iomem *plicsw; /* plic base address */
#endif
#if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];

2
arch/riscv/include/asm/syscon.h
View File

@ -13,7 +13,7 @@
enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */
RISCV_SYSCON_PLICSW, /* Andes PLICSW */
};
#endif /* _ASM_SYSCON_H */

2
arch/riscv/lib/Makefile
View File

@ -13,7 +13,7 @@ obj-y += cache.o
obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o

26
arch/riscv/lib/andes_plic.c → arch/riscv/lib/andes_plicsw.c
View File

@ -37,8 +37,8 @@ static int enable_ipi(int hart)
unsigned int en;
en = ENABLE_HART_IPI << hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart));
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
return 0;
}
@ -46,14 +46,14 @@ static int enable_ipi(int hart)
int riscv_init_ipi(void)
{
int ret;
long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
ofnode node;
struct udevice *dev;
u32 reg;
if (IS_ERR(base))
return PTR_ERR(base);
gd->arch.plic = base;
gd->arch.plicsw = base;
ret = uclass_find_first_device(UCLASS_CPU, &dev);
if (ret)
@ -88,7 +88,7 @@ int riscv_send_ipi(int hart)
{
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
gd->arch.boot_hart));
return 0;
@ -98,8 +98,8 @@ int riscv_clear_ipi(int hart)
{
u32 source_id;
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
return 0;
}
@ -108,21 +108,21 @@ int riscv_get_ipi(int hart, int *pending)
{
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
gd->arch.boot_hart));
*pending = !!(*pending & ipi);
return 0;
}
static const struct udevice_id andes_plic_ids[] = {
{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
static const struct udevice_id andes_plicsw_ids[] = {
{ .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW },
{ }
};
U_BOOT_DRIVER(andes_plic) = {
.name = "andes_plic",
U_BOOT_DRIVER(andes_plicsw) = {
.name = "andes_plicsw",
.id = UCLASS_SYSCON,
.of_match = andes_plic_ids,
.of_match = andes_plicsw_ids,
.flags = DM_FLAG_PRE_RELOC,
};

2
drivers/timer/andes_plmt_timer.c
View File

@ -56,7 +56,7 @@ static int andes_plmt_probe(struct udevice *dev)
}
static const struct udevice_id andes_plmt_ids[] = {
{ .compatible = "riscv,plmt0" },
{ .compatible = "andestech,plmt0" },
{ }
};