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Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi

Browse Source 
This is mostly about support for the Allwinner R528/T113s SoC, which is
reportedly the same die as the Allwinner D1, but with the two
Arm Cortex-A7 cores activated instead of the RISC-V one.
Using sunxi code outside of arch/arm proved to be difficult, so apart
from enabling this Arm SoC, the patches also prepare for more refactoring
to get the D1 nicely supported some day:
- We get rid of some Kconfig (hard-)coded GPIO pins, responsible for
  enabling regulators.
- The GPIO code is moved out of arch/arm, into drivers/gpio.
- Some definitions are moved out of header files under asm/arch.
- Some T113s/D1 specific definitions are guarded by a generic Kconfig
  symbol (CONFIG_SUNXI_GEN_NCAT2).
- The DRAM controller initialisation code is located under drivers/ram.
- The base SoC .dtsi files are shared (under arch/riscv, as in Linux).

Of course there are also the usual new SoC specific patches, like clock
and pinmux descriptions, alongside a rework of the pinctrl code, since
Allwinner changed the GPIO register layout, for the first time since
sunxi's inception.
On top of this the PSCI code sees some update, to provide SMP services
for R528/T113s boards. Many thanks to Sam for providing this code and
staying strong through the review cycles.
The final patch enables support for one popular board, I hope to see
more DTs and defconfigs contributed in the future!

Many thanks to all the various contributors, testers and reviewers,
that series was a real team effort!
This commit is contained in:
Tom Rini 2023-10-23 09:04:55 -04:00
commit a8f6dab0d4
131 changed files with 4239 additions and 599 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/Kconfig
View File

@ -1135,7 +1135,6 @@ config ARCH_SUNXI
select DM_MMC if MMC
select DM_SCSI if SCSI
select DM_SERIAL
select GPIO_EXTRA_HEADER
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
@ -1159,6 +1158,8 @@ config ARCH_SUNXI
imply CMD_GPT
imply CMD_UBI if MTD_RAW_NAND
imply DISTRO_DEFAULTS
imply DM_REGULATOR
imply DM_REGULATOR_FIXED
imply FAT_WRITE
imply FIT
imply OF_LIBFDT_OVERLAY

3
arch/arm/cpu/armv7/Kconfig
View File

@ -61,8 +61,9 @@ config ARMV7_SECURE_MAX_SIZE
config ARM_GIC_BASE_ADDRESS
hex
depends on ARMV7_NONSEC
depends on ARCH_EXYNOS5
depends on ARCH_EXYNOS5 || MACH_SUN8I_R528
default 0x10480000 if ARCH_EXYNOS5
default 0x03020000 if MACH_SUN8I_R528
help
Override the GIC base address if the Arm Cortex defined
CBAR/PERIPHBASE system register holds the wrong value.

196
arch/arm/cpu/armv7/sunxi/psci.c
View File

@ -11,8 +11,6 @@
#include <asm/cache.h>
#include <asm/arch/cpu.h>
#include <asm/arch/cpucfg.h>
#include <asm/arch/prcm.h>
#include <asm/armv7.h>
#include <asm/gic.h>
#include <asm/io.h>
@ -27,6 +25,17 @@
#define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
#define GICC_BASE (SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
/*
* Offsets into the CPUCFG block applicable to most SUNXIs.
*/
#define SUNXI_CPU_RST(cpu) (0x40 + (cpu) * 0x40 + 0x0)
#define SUNXI_CPU_STATUS(cpu) (0x40 + (cpu) * 0x40 + 0x8)
#define SUNXI_GEN_CTRL (0x184)
#define SUNXI_PRIV0 (0x1a4)
#define SUN7I_CPU1_PWR_CLAMP (0x1b0)
#define SUN7I_CPU1_PWROFF (0x1b4)
#define SUNXI_DBG_CTRL1 (0x1e4)
/*
* R40 is different from other single cluster SoCs.
*
@ -38,6 +47,24 @@
#define SUN8I_R40_PWR_CLAMP(cpu) (0x120 + (cpu) * 0x4)
#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0 (0xbc)
/*
* R528 is also different, as it has both cores powered up (but held in reset
* state) after the SoC is reset. Like the R40, it uses a "soft" entry point
* address register, but unlike the R40, it uses a newer "CPUX" block to manage
* CPU state, rather than the older CPUCFG system.
*/
#define SUN8I_R528_SOFT_ENTRY (0x1c8)
#define SUN8I_R528_C0_RST_CTRL (0x0000)
#define SUN8I_R528_C0_CTRL_REG0 (0x0010)
#define SUN8I_R528_C0_CPU_STATUS (0x0080)
#define SUN8I_R528_C0_STATUS_STANDBYWFI (16)
/* Only newer cores have this additional IP block. */
#ifndef SUNXI_R_CPUCFG_BASE
#define SUNXI_R_CPUCFG_BASE 0
#endif
static void __secure cp15_write_cntp_tval(u32 tval)
{
asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@ -76,11 +103,8 @@ static void __secure __mdelay(u32 ms)
isb();
}
static void __secure clamp_release(u32 __maybe_unused *clamp)
static void __secure clamp_release(u32 *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
defined(CONFIG_MACH_SUN8I_R40)
u32 tmp = 0x1ff;
do {
tmp >>= 1;
@ -88,24 +112,54 @@ static void __secure clamp_release(u32 __maybe_unused *clamp)
} while (tmp);
__mdelay(10);
#endif
}
static void __secure clamp_set(u32 __maybe_unused *clamp)
static void __secure clamp_set(u32 *clamp)
{
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_H3) || \
defined(CONFIG_MACH_SUN8I_R40)
writel(0xff, clamp);
#endif
}
static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
int cpu)
static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
{
if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
writel((u32)entry,
SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
} else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
writel((u32)entry,
SUNXI_R_CPUCFG_BASE + SUN8I_R528_SOFT_ENTRY);
} else {
writel((u32)entry, SUNXI_CPUCFG_BASE + SUNXI_PRIV0);
}
}
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
u32 *clamp = NULL;
u32 *pwroff;
/* sun7i (A20) is different from other single cluster SoCs */
if (IS_ENABLED(CONFIG_MACH_SUN7I)) {
clamp = (void *)SUNXI_CPUCFG_BASE + SUN7I_CPU1_PWR_CLAMP;
pwroff = (void *)SUNXI_CPUCFG_BASE + SUN7I_CPU1_PWROFF;
cpu = 0;
} else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40)) {
clamp = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWR_CLAMP(cpu);
pwroff = (void *)SUNXI_CPUCFG_BASE + SUN8I_R40_PWROFF;
} else if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
/* R528 leaves both cores powered up, manages them via reset */
return;
} else {
if (IS_ENABLED(CONFIG_MACH_SUN6I) ||
IS_ENABLED(CONFIG_MACH_SUN8I_H3))
clamp = (void *)SUNXI_PRCM_BASE + 0x140 + cpu * 0x4;
pwroff = (void *)SUNXI_PRCM_BASE + 0x100;
}
if (on) {
/* Release power clamp */
clamp_release(clamp);
if (clamp)
clamp_release(clamp);
/* Clear power gating */
clrbits_le32(pwroff, BIT(cpu));
@ -114,82 +168,80 @@ static void __secure sunxi_power_switch(u32 *clamp, u32 *pwroff, bool on,
setbits_le32(pwroff, BIT(cpu));
/* Activate power clamp */
clamp_set(clamp);
if (clamp)
clamp_set(clamp);
}
}
#ifdef CONFIG_MACH_SUN8I_R40
/* secondary core entry address is programmed differently on R40 */
static void __secure sunxi_set_entry_address(void *entry)
static void __secure sunxi_cpu_set_reset(int cpu, bool reset)
{
writel((u32)entry,
SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
if (reset)
clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
BIT(cpu));
else
setbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_RST_CTRL,
BIT(cpu));
return;
}
writel(reset ? 0b00 : 0b11, SUNXI_CPUCFG_BASE + SUNXI_CPU_RST(cpu));
}
#else
static void __secure sunxi_set_entry_address(void *entry)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
writel((u32)entry, &cpucfg->priv0);
static void __secure sunxi_cpu_set_locking(int cpu, bool lock)
{
if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
/* Not required on R528 */
return;
}
if (lock)
clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_DBG_CTRL1, BIT(cpu));
else
setbits_le32(SUNXI_CPUCFG_BASE + SUNXI_DBG_CTRL1, BIT(cpu));
}
#endif
#ifdef CONFIG_MACH_SUN7I
/* sun7i (A20) is different from other single cluster SoCs */
static void __secure sunxi_cpu_set_power(int __always_unused cpu, bool on)
static bool __secure sunxi_cpu_poll_wfi(int cpu)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
return !!(readl(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CPU_STATUS) &
BIT(SUN8I_R528_C0_STATUS_STANDBYWFI + cpu));
}
sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
on, 0);
return !!(readl(SUNXI_CPUCFG_BASE + SUNXI_CPU_STATUS(cpu)) & BIT(2));
}
#elif defined CONFIG_MACH_SUN8I_R40
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu),
(void *)cpucfg + SUN8I_R40_PWROFF,
on, cpu);
static void __secure sunxi_cpu_invalidate_cache(int cpu)
{
if (IS_ENABLED(CONFIG_MACH_SUN8I_R528)) {
clrbits_le32(SUNXI_CPUCFG_BASE + SUN8I_R528_C0_CTRL_REG0,
BIT(cpu));
return;
}
clrbits_le32(SUNXI_CPUCFG_BASE + SUNXI_GEN_CTRL, BIT(cpu));
}
#else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */
static void __secure sunxi_cpu_set_power(int cpu, bool on)
{
struct sunxi_prcm_reg *prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
on, cpu);
}
#endif /* CONFIG_MACH_SUN7I */
void __secure sunxi_cpu_power_off(u32 cpuid)
static void __secure sunxi_cpu_power_off(u32 cpuid)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = cpuid & 0x3;
/* Wait for the core to enter WFI */
while (1) {
if (readl(&cpucfg->cpu[cpu].status) & BIT(2))
break;
while (!sunxi_cpu_poll_wfi(cpu))
__mdelay(1);
}
/* Assert reset on target CPU */
writel(0, &cpucfg->cpu[cpu].rst);
sunxi_cpu_set_reset(cpu, true);
/* Lock CPU (Disable external debug access) */
clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
sunxi_cpu_set_locking(cpu, true);
/* Power down CPU */
sunxi_cpu_set_power(cpuid, false);
/* Unlock CPU (Disable external debug access) */
setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
/* Unlock CPU (Reenable external debug access) */
sunxi_cpu_set_locking(cpu, false);
}
static u32 __secure cp15_read_scr(void)
@ -246,33 +298,31 @@ out:
int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
u32 context_id)
{
struct sunxi_cpucfg_reg *cpucfg =
(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
u32 cpu = (mpidr & 0x3);
/* store target PC and context id */
psci_save(cpu, pc, context_id);
/* Set secondary core power on PC */
sunxi_set_entry_address(&psci_cpu_entry);
sunxi_cpu_set_entry(cpu, &psci_cpu_entry);
/* Assert reset on target CPU */
writel(0, &cpucfg->cpu[cpu].rst);
sunxi_cpu_set_reset(cpu, true);
/* Invalidate L1 cache */
clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu));
sunxi_cpu_invalidate_cache(cpu);
/* Lock CPU (Disable external debug access) */
clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
sunxi_cpu_set_locking(cpu, true);
/* Power up target CPU */
sunxi_cpu_set_power(cpu, true);
/* De-assert reset on target CPU */
writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
sunxi_cpu_set_reset(cpu, false);
/* Unlock CPU (Disable external debug access) */
setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
/* Unlock CPU (Reenable external debug access) */
sunxi_cpu_set_locking(cpu, false);
return ARM_PSCI_RET_SUCCESS;
}

1
arch/arm/cpu/armv7/sunxi/sram.c
View File

@ -12,6 +12,7 @@
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
void sunxi_sram_init(void)
{

1
arch/arm/cpu/armv8/fel_utils.S
View File

@ -10,6 +10,7 @@
#include <config.h>
#include <asm/system.h>
#include <linux/linkage.h>
#include <asm/arch/cpu.h>
/*
* We don't overwrite save_boot_params() here, to save the FEL state upon

2
arch/arm/dts/Makefile
View File

@ -776,6 +776,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-s3-pinecube.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN8I_R528) += \
sun8i-t113s-mangopi-mq-r-t113.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
sun50i-h5-emlid-neutis-n5-devboard.dtb \

7
arch/arm/dts/axp209.dtsi
View File

@ -48,6 +48,13 @@
* http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
*/
/ {
pmic-temp {
compatible = "iio-hwmon";
io-channels = <&axp_adc 4>; /* Internal temperature */
};
};
&axp209 {
compatible = "x-powers,axp209";
interrupt-controller;

3
arch/arm/dts/sun50i-a64.dtsi
View File

@ -93,6 +93,7 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@ -407,7 +408,7 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";

2
arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Corentin LABBE <clabbe@baylibre.com>
*/

134
arch/arm/dts/sun50i-h616-orangepi-zero.dtsi Normal file
View File

@ -0,0 +1,134 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Arm Ltd.
*
* DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3.
* Excludes PMIC nodes and properties, since they are different between the two.
*/
#include "sun50i-h616.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
ethernet0 = &emac0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
default-state = "on";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
};
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the USB-C socket */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_vcc5v>;
enable-active-high;
gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
};
};
&ehci1 {
status = "okay";
};
/* USB 2 & 3 are on headers only. */
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
status = "okay";
};
&mdio0 {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
* is not implemented: both CC pins are pulled to GND.
* The VBUS pins power the device, so a fixed peripheral mode
* is the best choice.
* The board can be powered via GPIOs, in this case port0 *can*
* act as a host (with a cable/adapter ignoring CC), as VBUS is
* then provided by the GPIOs. Any user of this setup would
* need to adjust the DT accordingly: dr_mode set to "host",
* enabling OHCI0 and EHCI0.
*/
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

121
arch/arm/dts/sun50i-h616-orangepi-zero2.dts
View File

@ -1,99 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2020 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/leds/common.h>
#include "sun50i-h616-orangepi-zero.dtsi"
/ {
model = "OrangePi Zero2";
compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
aliases {
ethernet0 = &emac0;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
default-state = "on";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
};
};
reg_vcc5v: vcc5v {
/* board wide 5V supply directly from the USB-C socket */
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&reg_vcc5v>;
enable-active-high;
gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
};
};
&ehci1 {
status = "okay";
};
/* USB 2 & 3 are on headers only. */
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dcdce>;
allwinner,rx-delay-ps = <3100>;
allwinner,tx-delay-ps = <700>;
status = "okay";
};
&mdio0 {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
vmmc-supply = <&reg_dcdce>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_rsb {
@ -211,44 +135,3 @@
vcc-ph-supply = <&reg_aldo1>;
vcc-pi-supply = <&reg_aldo1>;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbotg {
/*
* PHY0 pins are connected to a USB-C socket, but a role switch
* is not implemented: both CC pins are pulled to GND.
* The VBUS pins power the device, so a fixed peripheral mode
* is the best choice.
* The board can be powered via GPIOs, in this case port0 *can*
* act as a host (with a cable/adapter ignoring CC), as VBUS is
* then provided by the GPIOs. Any user of this setup would
* need to adjust the DT accordingly: dr_mode set to "host",
* enabling OHCI0 and EHCI0.
*/
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

2
arch/arm/dts/sun50i-h616-x96-mate.dts
View File

@ -1,4 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Arm Ltd.
*/

94
arch/arm/dts/sun50i-h618-orangepi-zero3.dts Normal file
View File

@ -0,0 +1,94 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Arm Ltd.
*/
/dts-v1/;
#include "sun50i-h616-orangepi-zero.dtsi"
/ {
model = "OrangePi Zero3";
compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618";
};
&emac0 {
phy-supply = <&reg_dldo1>;
};
&ext_rgmii_phy {
motorcomm,clk-out-frequency-hz = <125000000>;
};
&mmc0 {
/*
* The schematic shows the card detect pin wired up to PF6, via an
* inverter, but it just doesn't work.
*/
broken-cd;
vmmc-supply = <&reg_dldo1>;
};
&r_i2c {
status = "okay";
axp313: pmic@36 {
compatible = "x-powers,axp313a";
reg = <0x36>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
vin1-supply = <&reg_vcc5v>;
vin2-supply = <&reg_vcc5v>;
vin3-supply = <&reg_vcc5v>;
regulators {
/* Supplies VCC-PLL, so needs to be always on. */
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc1v8";
};
/* Supplies VCC-IO, so needs to be always on. */
reg_dldo1: dldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc3v3";
};
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <990000>;
regulator-name = "vdd-gpu-sys";
};
reg_dcdc2: dcdc2 {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpu";
};
reg_dcdc3: dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-dram";
};
};
};
};
&pio {
vcc-pc-supply = <&reg_dldo1>;
vcc-pf-supply = <&reg_dldo1>;
vcc-pg-supply = <&reg_aldo1>;
vcc-ph-supply = <&reg_dldo1>;
vcc-pi-supply = <&reg_dldo1>;
};

6
arch/arm/dts/sun5i-r8-chip.dts
View File

@ -255,6 +255,12 @@
pinctrl-0 = <&uart3_pg_pins>,
<&uart3_cts_rts_pg_pins>;
status = "okay";
bluetooth {
compatible = "realtek,rtl8723bs-bt";
device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_HIGH>;
host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
};
};
&usb_otg {

11
arch/arm/dts/sun5i.dtsi
View File

@ -286,7 +286,7 @@
clock-names = "ahb",
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon-pixel-clock";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
status = "disabled";
@ -517,6 +517,15 @@
bias-pull-up;
};
/omit-if-no-ref/
mmc2_4bit_pe_pins: mmc2-4bit-pe-pins {
pins = "PE4", "PE5", "PE6", "PE7",
"PE8", "PE9";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13",

137
arch/arm/dts/sun7i-a20-icnova-a20-adb4006.dts Normal file
View File

@ -0,0 +1,137 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// Copyright (C) 2023 In-Circuit GmbH
/dts-v1/;
#include "sun7i-a20-icnova-a20.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
model = "In-Circuit ICnova A20 ADB4006";
compatible = "incircuit,icnova-a20-adb4006", "incircuit,icnova-a20",
"allwinner,sun7i-a20";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_YELLOW>;
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* PH21 */
default-state = "on";
};
led-1 {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_RED>;
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */
linux,default-trigger = "heartbeat";
};
};
};
&ahci {
target-supply = <&reg_ahci_5v>;
status = "okay";
};
&codec {
status = "okay";
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&otg_sram {
status = "okay";
};
&reg_ahci_5v {
status = "okay";
};
&ac_power_supply {
status = "okay";
};
&reg_usb1_vbus {
status = "okay";
};
&reg_usb2_vbus {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};

62
arch/arm/dts/sun7i-a20-icnova-a20.dtsi Normal file
View File

@ -0,0 +1,62 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
// Copyright (C) 2023 In-Circuit GmbH
#include "sun7i-a20.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
};
&i2c0 {
status = "okay";
axp209: pmic@34 {
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
#include "axp209.dtsi"
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
regulator-name = "vdd-int-dll";
};
&reg_ldo1 {
regulator-name = "vdd-rtc";
};
&reg_ldo2 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};

2
arch/arm/dts/sun8i-a23-a33.dtsi
View File

@ -190,7 +190,7 @@
clock-names = "ahb",
"tcon-ch0",
"lvds-alt";
clock-output-names = "tcon-pixel-clock";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_LCD>,
<&ccu RST_BUS_LVDS>;

2
arch/arm/dts/sun8i-a83t.dtsi
View File

@ -456,7 +456,7 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";

35
arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2022 Arm Ltd.
#include <dt-bindings/interrupt-controller/irq.h>
/dts-v1/;
#include "sun8i-t113s.dtsi"
#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
/ {
model = "MangoPi MQ-R-T113";
compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s";
aliases {
ethernet0 = &rtl8189ftv;
};
};
&cpu0 {
cpu-supply = <&reg_vcc_core>;
};
&cpu1 {
cpu-supply = <&reg_vcc_core>;
};
&mmc1 {
rtl8189ftv: wifi@1 {
reg = <1>;
interrupt-parent = <&pio>;
interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */
interrupt-names = "host-wake";
};
};

59
arch/arm/dts/sun8i-t113s.dtsi Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2022 Arm Ltd.
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
#include <../../riscv/dts/sunxi-d1-t113.dtsi>
/ {
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
};
};
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>,
<0x03022000 0x2000>,
<0x03024000 0x2000>,
<0x03026000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
};

2
arch/arm/dts/sun8i-v3s.dtsi
View File

@ -191,7 +191,7 @@
<&ccu CLK_TCON0>;
clock-names = "ahb",
"tcon-ch0";
clock-output-names = "tcon-pixel-clock";
clock-output-names = "tcon-data-clock";
#clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>;
reset-names = "lcd";

126
arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi Normal file
View File

@ -0,0 +1,126 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2022 Arm Ltd.
/*
* Common peripherals and configurations for MangoPi MQ-R boards.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
serial3 = &uart3;
};
chosen {
stdout-path = "serial3:115200n8";
};
leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_STATUS;
gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */
};
};
/* board wide 5V supply directly from the USB-C socket */
reg_vcc5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "vcc-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
/* SY8008 DC/DC regulator on the board */
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&reg_vcc5v>;
};
/* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
reg_vcc_core: regulator-core {
compatible = "regulator-fixed";
regulator-name = "vcc-core";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
vin-supply = <&reg_vcc5v>;
};
/* XC6206 LDO on the board */
reg_avdd2v8: regulator-avdd {
compatible = "regulator-fixed";
regulator-name = "avdd2v8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
vin-supply = <&reg_3v3>;
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
};
};
&dcxo {
clock-frequency = <24000000>;
};
&ehci1 {
status = "okay";
};
&mmc0 {
pinctrl-0 = <&mmc0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-0 = <&mmc1_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3v3>;
non-removable;
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
};
&ohci1 {
status = "okay";
};
&pio {
vcc-pb-supply = <&reg_3v3>;
vcc-pd-supply = <&reg_3v3>;
vcc-pe-supply = <&reg_avdd2v8>;
vcc-pf-supply = <&reg_3v3>;
vcc-pg-supply = <&reg_3v3>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pb_pins>;
status = "okay";
};
/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */
&usb_otg {
dr_mode = "peripheral";
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc5v>;
status = "okay";
};

7
arch/arm/dts/sunxi-u-boot.dtsi
View File

@ -23,6 +23,13 @@
};
};
/* Let U-Boot be the firmware layer that controls the watchdog. */
#ifdef CONFIG_MACH_SUN8I_R528
&wdt {
status = "okay";
};
#endif
&binman {
u-boot-sunxi-with-spl {
filename = "u-boot-sunxi-with-spl.bin";

2
arch/arm/include/asm/arch-sunxi/boot0.h
View File

@ -3,6 +3,8 @@
* Configuration settings for the Allwinner A64 (sun50i) CPU
*/
#include <asm/arch/cpu.h>
#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
/* reserve space for BOOT0 header information */
b reset

3
arch/arm/include/asm/arch-sunxi/clock.h
View File

@ -9,6 +9,7 @@
#define _SUNXI_CLOCK_H
#include <linux/types.h>
#include <asm/arch/cpu.h>
#define CLK_GATE_OPEN 0x1
#define CLK_GATE_CLOSE 0x0
@ -16,7 +17,7 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN8I_A83T)
#include <asm/arch/clock_sun8i_a83t.h>
#elif defined(CONFIG_SUN50I_GEN_H6)
#elif defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
#include <asm/arch/clock_sun50i_h6.h>
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV)

12
arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
View File

@ -228,6 +228,7 @@ struct sunxi_ccm_reg {
/* pll1 bit field */
#define CCM_PLL1_CTRL_EN BIT(31)
#define CCM_PLL1_LDO_EN BIT(30)
#define CCM_PLL1_LOCK_EN BIT(29)
#define CCM_PLL1_LOCK BIT(28)
#define CCM_PLL1_OUT_EN BIT(27)
@ -248,6 +249,8 @@ struct sunxi_ccm_reg {
#define CCM_PLL6_CTRL_EN BIT(31)
#define CCM_PLL6_LOCK_EN BIT(29)
#define CCM_PLL6_LOCK BIT(28)
#define CCM_PLL6_CTRL_P0_SHIFT 16
#define CCM_PLL6_CTRL_P0_MASK (0x7 << CCM_PLL6_CTRL_P0_SHIFT)
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
#define CCM_PLL6_CTRL_DIV1_SHIFT 0
@ -263,7 +266,7 @@ struct sunxi_ccm_reg {
#define CCM_CPU_AXI_AXI_MASK 0x3
#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301
#ifdef CONFIG_MACH_SUN50I_H6
#ifdef CONFIG_MACH_SUN50I_H6 /* H6 */
#define CCM_PLL6_DEFAULT 0xa0006300
/* psi_ahb1_ahb2 bit field */
@ -274,7 +277,7 @@ struct sunxi_ccm_reg {
/* apb1 bit field */
#define CCM_APB1_DEFAULT 0x03000102
#elif CONFIG_MACH_SUN50I_H616
#elif CONFIG_MACH_SUN50I_H616 /* H616 */
#define CCM_PLL6_DEFAULT 0xa8003100
/* psi_ahb1_ahb2 bit field */
@ -285,6 +288,11 @@ struct sunxi_ccm_reg {
/* apb1 bit field */
#define CCM_APB1_DEFAULT 0x03000102
#elif CONFIG_MACH_SUN8I_R528 /* R528 */
#define CCM_PLL6_DEFAULT 0xe8216300
#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000002
//#define CCM_AHB3_DEFAULT 0x03000002
#define CCM_APB1_DEFAULT 0x03000102
#endif
/* apb2 bit field */

2
arch/arm/include/asm/arch-sunxi/cpu.h
View File

@ -10,6 +10,8 @@
#include <asm/arch/cpu_sun9i.h>
#elif defined(CONFIG_SUN50I_GEN_H6)
#include <asm/arch/cpu_sun50i_h6.h>
#elif defined(CONFIG_SUNXI_GEN_NCAT2)
#include <asm/arch/cpu_sunxi_ncat2.h>
#else
#include <asm/arch/cpu_sun4i.h>
#endif

17
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
View File

@ -91,7 +91,6 @@
#define SUNXI_CCM_BASE 0x01c20000
#define SUNXI_INTC_BASE 0x01c20400
#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
#ifndef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_PWM_BASE 0x01c20e00
@ -129,20 +128,6 @@ defined(CONFIG_MACH_SUN50I)
#define SUNXI_CPUCFG_BASE 0x01c25c00
#endif
#ifdef CONFIG_MACH_SUNIV
#define SUNXI_UART0_BASE 0x01c25000
#define SUNXI_UART1_BASE 0x01c25400
#define SUNXI_UART2_BASE 0x01c25800
#else
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
#endif
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
#define SUNXI_UART6_BASE 0x01c29800
#define SUNXI_UART7_BASE 0x01c29c00
#define SUNXI_PS2_0_BASE 0x01c2a000
#define SUNXI_PS2_1_BASE 0x01c2a400
@ -209,8 +194,6 @@ defined(CONFIG_MACH_SUN50I)
#endif
#define SUNXI_R_TWI_BASE 0x01f02400
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUN6I_P2WI_BASE 0x01f03400
#define SUNXI_RSB_BASE 0x01f03400

7
arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
View File

@ -22,7 +22,6 @@
#define SUNXI_SIDC_BASE 0x03006000
#define SUNXI_SID_BASE 0x03006200
#define SUNXI_TIMER_BASE 0x03009000
#define SUNXI_PIO_BASE 0x0300B000
#define SUNXI_PSI_BASE 0x0300C000
#define SUNXI_GIC400_BASE 0x03020000
@ -43,10 +42,6 @@
#define SUNXI_DRAM_PHY0_BASE 0x04800000
#endif
#define SUNXI_UART0_BASE 0x05000000
#define SUNXI_UART1_BASE 0x05000400
#define SUNXI_UART2_BASE 0x05000800
#define SUNXI_UART3_BASE 0x05000C00
#define SUNXI_TWI0_BASE 0x05002000
#define SUNXI_TWI1_BASE 0x05002400
#define SUNXI_TWI2_BASE 0x05002800
@ -68,8 +63,6 @@
#define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_PRCM_BASE 0x07010000
#define SUNXI_R_WDOG_BASE 0x07020400
#define SUNXI_R_PIO_BASE 0x07022000
#define SUNXI_R_UART_BASE 0x07080000
#define SUNXI_R_TWI_BASE 0x07081400
#ifndef __ASSEMBLY__

9
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
View File

@ -81,18 +81,11 @@
/* APB0 Module */
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
/* APB1 Module */
#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400)
#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800)
#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00)
#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000)
#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400)
#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
@ -101,8 +94,6 @@
/* RCPUS Module */
#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
/* Misc. */

39
arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h Normal file
View File

@ -0,0 +1,39 @@
/*
* (C) Copyright 2022 Arm Limited
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_CPU_SUNXI_NCAT2_H
#define _SUNXI_CPU_SUNXI_NCAT2_H
#define SUNXI_CCM_BASE 0x02001000
#define SUNXI_TIMER_BASE 0x02050000
#define SUNXI_TWI0_BASE 0x02502000
#define SUNXI_TWI1_BASE 0x02502400
#define SUNXI_TWI2_BASE 0x02502800
#define SUNXI_TWI3_BASE 0x02502C00
#define SUNXI_SRAMC_BASE 0x03000000
/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
#define SUNXI_SIDC_BASE 0x03006000
#define SUNXI_SID_BASE 0x03006200
#define SUNXI_GIC400_BASE 0x03020000
#define SUNXI_MMC0_BASE 0x04020000
#define SUNXI_MMC1_BASE 0x04021000
#define SUNXI_MMC2_BASE 0x04022000
#define SUNXI_R_CPUCFG_BASE 0x07000400
#define SUNXI_PRCM_BASE 0x07010000
#define SUNXI_CPUCFG_BASE 0x09010000
#ifndef __ASSEMBLY__
void sunxi_board_init(void);
void sunxi_reset(void);
int sunxi_get_sid(unsigned int *sid);
#endif
#endif /* _SUNXI_CPU_SUNXI_NCAT2_H */

67
arch/arm/include/asm/arch-sunxi/cpucfg.h
View File

@ -1,67 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Sunxi A31 CPUCFG register definition.
*
* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
*/
#ifndef _SUNXI_CPUCFG_H
#define _SUNXI_CPUCFG_H
#include <linux/compiler.h>
#include <linux/types.h>
#ifndef __ASSEMBLY__
struct __packed sunxi_cpucfg_cpu {
u32 rst; /* base + 0x0 */
u32 ctrl; /* base + 0x4 */
u32 status; /* base + 0x8 */
u8 res[0x34]; /* base + 0xc */
};
struct __packed sunxi_cpucfg_reg {
u8 res0[0x40]; /* 0x000 */
struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
u8 res1[0x44]; /* 0x140 */
u32 gen_ctrl; /* 0x184 */
u32 l2_status; /* 0x188 */
u8 res2[0x4]; /* 0x18c */
u32 event_in; /* 0x190 */
u8 res3[0xc]; /* 0x194 */
u32 super_standy_flag; /* 0x1a0 */
u32 priv0; /* 0x1a4 */
u32 priv1; /* 0x1a8 */
u8 res4[0x4]; /* 0x1ac */
u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */
u32 cpu1_pwroff; /* 0x1b4 sun7i only */
u8 res5[0x2c]; /* 0x1b8 */
u32 dbg_ctrl1; /* 0x1e4 */
u8 res6[0x18]; /* 0x1e8 */
u32 idle_cnt0_low; /* 0x200 */
u32 idle_cnt0_high; /* 0x204 */
u32 idle_cnt0_ctrl; /* 0x208 */
u8 res8[0x4]; /* 0x20c */
u32 idle_cnt1_low; /* 0x210 */
u32 idle_cnt1_high; /* 0x214 */
u32 idle_cnt1_ctrl; /* 0x218 */
u8 res9[0x4]; /* 0x21c */
u32 idle_cnt2_low; /* 0x220 */
u32 idle_cnt2_high; /* 0x224 */
u32 idle_cnt2_ctrl; /* 0x228 */
u8 res10[0x4]; /* 0x22c */
u32 idle_cnt3_low; /* 0x230 */
u32 idle_cnt3_high; /* 0x234 */
u32 idle_cnt3_ctrl; /* 0x238 */
u8 res11[0x4]; /* 0x23c */
u32 idle_cnt4_low; /* 0x240 */
u32 idle_cnt4_high; /* 0x244 */
u32 idle_cnt4_ctrl; /* 0x248 */
u8 res12[0x34]; /* 0x24c */
u32 cnt64_ctrl; /* 0x280 */
u32 cnt64_low; /* 0x284 */
u32 cnt64_high; /* 0x288 */
};
#endif /* __ASSEMBLY__ */
#endif /* _SUNXI_CPUCFG_H */

2
arch/arm/include/asm/arch-sunxi/mmc.h
View File

@ -45,7 +45,7 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res2[26];
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
u32 res3[17];
u32 samp_dl;
u32 res4[46];

2
arch/arm/include/asm/arch-sunxi/prcm.h
View File

@ -9,7 +9,7 @@
#define _SUNXI_PRCM_H
/* prcm regs definition */
#if defined(CONFIG_SUN50I_GEN_H6)
#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
#include <asm/arch/prcm_sun50i.h>
#else
#include <asm/arch/prcm_sun6i.h>

32
arch/arm/include/asm/arch-sunxi/serial.h Normal file
View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* hardcoded UART base addresses for early SPL use
*
* Copyright (c) 2022 Arm Ltd.
*/
#ifndef SUNXI_SERIAL_MEMMAP_H
#define SUNXI_SERIAL_MEMMAP_H
#if defined(CONFIG_MACH_SUN9I)
#define SUNXI_UART0_BASE 0x07000000
#define SUNXI_R_UART_BASE 0x08002800
#elif defined(CONFIG_SUN50I_GEN_H6)
#define SUNXI_UART0_BASE 0x05000000
#define SUNXI_R_UART_BASE 0x07080000
#elif defined(CONFIG_MACH_SUNIV)
#define SUNXI_UART0_BASE 0x01c25000
#define SUNXI_R_UART_BASE 0
#elif defined(CONFIG_SUNXI_GEN_NCAT2)
#define SUNXI_UART0_BASE 0x02500000
#define SUNXI_R_UART_BASE 0 // 0x07080000 (?>
#else
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_R_UART_BASE 0x01f02800
#endif
#define SUNXI_UART1_BASE (SUNXI_UART0_BASE + 0x400)
#define SUNXI_UART2_BASE (SUNXI_UART0_BASE + 0x800)
#define SUNXI_UART3_BASE (SUNXI_UART0_BASE + 0xc00)
#endif /* SUNXI_SERIAL_MEMMAP_H */

2
arch/arm/include/asm/arch-sunxi/timer.h
View File

@ -76,7 +76,7 @@ struct sunxi_timer_reg {
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif

42
arch/arm/mach-sunxi/Kconfig
View File

@ -121,7 +121,7 @@ config AXP_PMIC_BUS
config SUNXI_SRAM_ADDRESS
hex
default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
default 0x20000 if SUN50I_GEN_H6
default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
default 0x0
---help---
Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
@ -183,6 +183,14 @@ config SUN50I_GEN_H6
Select this for sunxi SoCs which have H6 like peripherals, clocks
and memory map.
config SUNXI_GEN_NCAT2
bool
select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
---help---
Select this for sunxi SoCs which have D1 like peripherals, clocks
and memory map.
config SUNXI_DRAM_DW
bool
---help---
@ -338,6 +346,19 @@ config MACH_SUN8I_R40
select SUNXI_DRAM_DW_32BIT
imply SPL_SYS_I2C_LEGACY
config MACH_SUN8I_R528
bool "sun8i (Allwinner R528)"
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
select SPL_ARMV7_SET_CORTEX_SMPEN
select SUNXI_GEN_NCAT2
select SUNXI_NEW_PINCTRL
select MMC_SUNXI_HAS_NEW_MODE
select SUPPORT_SPL
select DRAM_SUN20I_D1
config MACH_SUN8I_V3S
bool "sun8i (Allwinner V3/V3s/S3/S3L)"
select CPU_V7A
@ -648,6 +669,7 @@ config SYS_CLK_FREQ
default 1008000000 if MACH_SUN9I
default 888000000 if MACH_SUN50I_H6
default 1008000000 if MACH_SUN50I_H616
default 1008000000 if MACH_SUN8I_R528
config SYS_CONFIG_NAME
default "suniv" if MACH_SUNIV
@ -656,6 +678,7 @@ config SYS_CONFIG_NAME
default "sun6i" if MACH_SUN6I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
default "sun8i" if MACH_SUN8I_R528
default "sun9i" if MACH_SUN9I
default "sun50i" if MACH_SUN50I
default "sun50i" if MACH_SUN50I_H6
@ -695,13 +718,6 @@ config OLD_SUNXI_KERNEL_COMPAT
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
config MACPWR
string "MAC power pin"
default ""
help
Set the pin used to power the MAC. This takes a string in the format
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config MMC1_PINS_PH
bool "Pins for mmc1 are on Port H"
depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40
@ -811,6 +827,7 @@ config VIDEO_SUNXI
depends on !MACH_SUN9I
depends on !MACH_SUN50I
depends on !SUN50I_GEN_H6
depends on !SUNXI_GEN_NCAT2
select VIDEO
select DISPLAY
imply VIDEO_DT_SIMPLEFB
@ -1008,14 +1025,6 @@ config VIDEO_LCD_TL059WV5C0
endchoice
config SATAPWR
string "SATA power pin"
default ""
help
Set the pins used to power the SATA. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
port H.
config GMAC_TX_DELAY
int "GMAC Transmit Clock Delay Chain"
default 0
@ -1032,6 +1041,7 @@ config SPL_STACK_R_ADDR
default 0x2fe00000 if MACH_SUN9I
default 0x4fe00000 if MACH_SUN50I
default 0x4fe00000 if SUN50I_GEN_H6
default 0x4fe00000 if SUNXI_GEN_NCAT2
config SPL_SPI_SUNXI
bool "Support for SPI Flash on Allwinner SoCs in SPL"

2
arch/arm/mach-sunxi/Makefile
View File

@ -10,7 +10,6 @@ obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
obj-$(CONFIG_SUN6I_PRCM) += prcm.o
obj-$(CONFIG_AXP_PMIC_BUS) += pmic_bus.o
obj-$(CONFIG_MACH_SUNIV) += clock_sun6i.o
@ -26,6 +25,7 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
endif
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o
obj-$(CONFIG_SUN50I_GEN_H6) += clock_sun50i_h6.o
obj-$(CONFIG_SUNXI_GEN_NCAT2) += clock_sun50i_h6.o
ifndef CONFIG_ARM64
obj-y += timer.o
endif

31
arch/arm/mach-sunxi/board.c
View File

@ -17,6 +17,7 @@
#include <i2c.h>
#include <serial.h>
#include <spl.h>
#include <sunxi_gpio.h>
#include <asm/cache.h>
#include <asm/gpio.h>
#include <asm/io.h>
@ -146,6 +147,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
@ -162,6 +167,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528)
sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7);
sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7);
sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
@ -175,13 +184,19 @@ static int gpio_init(void)
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
#ifdef CONFIG_SUN50I_GEN_H6
/* Update PIO power bias configuration by copy hardware detected value */
val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
#endif
/*
* Update PIO power bias configuration by copying the hardware
* detected value.
*/
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) {
val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
}
if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) {
val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
}
return 0;
}
@ -480,7 +495,7 @@ void reset_cpu(void)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
#if defined(CONFIG_MACH_SUN50I_H6)
/* WDOG is broken for some H6 rev. use the R_WDOG instead */
static const struct sunxi_wdog *wdog =

45
arch/arm/mach-sunxi/clock_sun50i_h6.c
View File

@ -18,8 +18,11 @@ void clock_init_safe(void)
setbits_le32(&prcm->res_cal_ctrl, 2);
}
clrbits_le32(&prcm->res_cal_ctrl, 1);
setbits_le32(&prcm->res_cal_ctrl, 1);
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
clrbits_le32(&prcm->res_cal_ctrl, 1);
setbits_le32(&prcm->res_cal_ctrl, 1);
}
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) {
/* set key field for ldo enable */
@ -38,7 +41,9 @@ void clock_init_safe(void)
CCM_CPU_AXI_DEFAULT_FACTORS);
writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
#ifdef CCM_AHB3_DEFAULT
writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
#endif
writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
/*
@ -86,11 +91,13 @@ void clock_set_pll1(unsigned int clk)
writel(val, &ccm->cpu_axi_cfg);
/* clk = 24*n/p, p is ignored if clock is >288MHz */
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
#ifdef CONFIG_MACH_SUN50I_H616
CCM_PLL1_OUT_EN |
#endif
CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg);
val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2;
val |= CCM_PLL1_CTRL_N(clk / 24000000);
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
val |= CCM_PLL1_OUT_EN;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN;
writel(val, &ccm->pll1_cfg);
while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
/* Switch CPU to PLL1 */
@ -105,16 +112,26 @@ unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) ? 4 : 2;
uint32_t rval = readl(&ccm->pll6_cfg);
int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
/* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
return 24000000 / m * n / div1 / div2;
CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
int div1, m;
if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
CCM_PLL6_CTRL_P0_SHIFT) + 1;
m = 1;
} else {
div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
m = 4;
else
m = 2;
}
return 24000000U * n / m / div1 / div2;
}
int clock_twi_onoff(int port, int state)

2
arch/arm/mach-sunxi/cpu_info.c
View File

@ -93,6 +93,8 @@ int print_cpuinfo(void)
printf("CPU: Allwinner R40 (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_V3S
printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
#elif defined CONFIG_MACH_SUN8I_R528
puts("CPU: Allwinner R528 (SUN8I)\n");
#elif defined CONFIG_MACH_SUN9I
puts("CPU: Allwinner A80 (SUN9I)\n");
#elif defined CONFIG_MACH_SUN50I

2
arch/arm/mach-sunxi/dram_suniv.c
View File

@ -13,10 +13,10 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <hang.h>
#include <sunxi_gpio.h>
#define SDR_T_CAS (0x2)
#define SDR_T_RAS (0x8)

1
arch/arm/mach-sunxi/gtbus_sun9i.c
View File

@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gtbus_sun9i.h>
#include <asm/arch/sys_proto.h>

78
arch/arm/mach-sunxi/pinmux.c
View File

@ -1,78 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2011
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
{
u32 index = GPIO_CFG_INDEX(bank_offset);
u32 offset = GPIO_CFG_OFFSET(bank_offset);
clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
}
void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
sunxi_gpio_set_cfgbank(pio, pin, val);
}
int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
{
u32 index = GPIO_CFG_INDEX(bank_offset);
u32 offset = GPIO_CFG_OFFSET(bank_offset);
u32 cfg;
cfg = readl(&pio->cfg[index]);
cfg >>= offset;
return cfg & 0xf;
}
int sunxi_gpio_get_cfgpin(u32 pin)
{
u32 bank = GPIO_BANK(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
return sunxi_gpio_get_cfgbank(pio, pin);
}
void sunxi_gpio_set_drv(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
sunxi_gpio_set_drv_bank(pio, pin, val);
}
void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
{
u32 index = GPIO_DRV_INDEX(bank_offset);
u32 offset = GPIO_DRV_OFFSET(bank_offset);
clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
}
void sunxi_gpio_set_pull(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
sunxi_gpio_set_pull_bank(pio, pin, val);
}
void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
{
u32 index = GPIO_PULL_INDEX(bank_offset);
u32 offset = GPIO_PULL_OFFSET(bank_offset);
clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset);
}

1
arch/arm/mach-sunxi/spl_spi_sunxi.c
View File

@ -13,6 +13,7 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <sunxi_gpio.h>
#ifdef CONFIG_SPL_OS_BOOT
#error CONFIG_SPL_OS_BOOT is not supported yet

1
arch/arm/mach-sunxi/timer.c
View File

@ -10,6 +10,7 @@
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/timer.h>
#include <linux/delay.h>

15
arch/riscv/dts/sunxi-d1-t113.dtsi Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
/ {
soc {
dsp_wdt: watchdog@1700400 {
compatible = "allwinner,sun20i-d1-wdt";
reg = <0x1700400 0x20>;
interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
status = "reserved";
};
};
};

927
arch/riscv/dts/sunxi-d1s-t113.dtsi Normal file
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@ -0,0 +1,927 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
#include <dt-bindings/clock/sun20i-d1-ccu.h>
#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
dcxo: dcxo-clk {
compatible = "fixed-clock";
clock-output-names = "dcxo";
#clock-cells = <0>;
};
de: display-engine {
compatible = "allwinner,sun20i-d1-display-engine";
allwinner,pipelines = <&mixer0>, <&mixer1>;
status = "disabled";
};
soc {
compatible = "simple-bus";
ranges;
dma-noncoherent;
#address-cells = <1>;
#size-cells = <1>;
pio: pinctrl@2000000 {
compatible = "allwinner,sun20i-d1-pinctrl";
reg = <0x2000000 0x800>;
interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB0>,
<&dcxo>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#gpio-cells = <3>;
#interrupt-cells = <3>;
/omit-if-no-ref/
can0_pins: can0-pins {
pins = "PB2", "PB3";
function = "can0";
};
/omit-if-no-ref/
can1_pins: can1-pins {
pins = "PB4", "PB5";
function = "can1";
};
/omit-if-no-ref/
clk_pg11_pin: clk-pg11-pin {
pins = "PG11";
function = "clk";
};
/omit-if-no-ref/
dsi_4lane_pins: dsi-4lane-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7", "PD8", "PD9";
drive-strength = <30>;
function = "dsi";
};
/omit-if-no-ref/
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
"PD18", "PD19", "PD20", "PD21";
function = "lcd0";
};
/omit-if-no-ref/
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
function = "mmc0";
};
/omit-if-no-ref/
mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
function = "mmc1";
};
/omit-if-no-ref/
mmc2_pins: mmc2-pins {
pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
function = "mmc2";
};
/omit-if-no-ref/
rgmii_pe_pins: rgmii-pe-pins {
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
"PE5", "PE6", "PE7", "PE8", "PE9",
"PE11", "PE12", "PE13", "PE14", "PE15";
function = "emac";
};
/omit-if-no-ref/
rmii_pe_pins: rmii-pe-pins {
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
"PE5", "PE6", "PE7", "PE8", "PE9";
function = "emac";
};
/omit-if-no-ref/
spi0_pins: spi0-pins {
pins = "PC2", "PC3", "PC4", "PC5";
function = "spi0";
};
/omit-if-no-ref/
uart1_pg6_pins: uart1-pg6-pins {
pins = "PG6", "PG7";
function = "uart1";
};
/omit-if-no-ref/
uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
pins = "PG8", "PG9";
function = "uart1";
};
/omit-if-no-ref/
uart3_pb_pins: uart3-pb-pins {
pins = "PB6", "PB7";
function = "uart3";
};
};
ccu: clock-controller@2001000 {
compatible = "allwinner,sun20i-d1-ccu";
reg = <0x2001000 0x1000>;
clocks = <&dcxo>,
<&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpadc: adc@2009000 {
compatible = "allwinner,sun20i-d1-gpadc";
reg = <0x2009000 0x400>;
clocks = <&ccu CLK_BUS_GPADC>;
resets = <&ccu RST_BUS_GPADC>;
interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#io-channel-cells = <1>;
};
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
reg = <0x2031000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMIC>,
<&ccu CLK_DMIC>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_DMIC>;
dmas = <&dma 8>;
dma-names = "rx";
status = "disabled";
#sound-dai-cells = <0>;
};
i2s1: i2s@2033000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2033000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S1>,
<&ccu CLK_I2S1>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S1>;
dmas = <&dma 4>, <&dma 4>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
i2s2: i2s@2034000 {
compatible = "allwinner,sun20i-d1-i2s",
"allwinner,sun50i-r329-i2s";
reg = <0x2034000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2S2>,
<&ccu CLK_I2S2>;
clock-names = "apb", "mod";
resets = <&ccu RST_BUS_I2S2>;
dmas = <&dma 5>, <&dma 5>;
dma-names = "rx", "tx";
status = "disabled";
#sound-dai-cells = <0>;
};
timer: timer@2050000 {
compatible = "allwinner,sun20i-d1-timer",
"allwinner,sun8i-a23-timer";
reg = <0x2050000 0xa0>;
interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
<SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>;
};
wdt: watchdog@20500a0 {
compatible = "allwinner,sun20i-d1-wdt-reset",
"allwinner,sun20i-d1-wdt";
reg = <0x20500a0 0x20>;
interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
status = "reserved";
};
uart0: serial@2500000 {
compatible = "snps,dw-apb-uart";
reg = <0x2500000 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
dmas = <&dma 14>, <&dma 14>;
dma-names = "tx", "rx";
status = "disabled";
};
uart1: serial@2500400 {
compatible = "snps,dw-apb-uart";
reg = <0x2500400 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
dmas = <&dma 15>, <&dma 15>;
dma-names = "tx", "rx";
status = "disabled";
};
uart2: serial@2500800 {
compatible = "snps,dw-apb-uart";
reg = <0x2500800 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
dmas = <&dma 16>, <&dma 16>;
dma-names = "tx", "rx";
status = "disabled";
};
uart3: serial@2500c00 {
compatible = "snps,dw-apb-uart";
reg = <0x2500c00 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
dmas = <&dma 17>, <&dma 17>;
dma-names = "tx", "rx";
status = "disabled";
};
uart4: serial@2501000 {
compatible = "snps,dw-apb-uart";
reg = <0x2501000 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
dmas = <&dma 18>, <&dma 18>;
dma-names = "tx", "rx";
status = "disabled";
};
uart5: serial@2501400 {
compatible = "snps,dw-apb-uart";
reg = <0x2501400 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_UART5>;
resets = <&ccu RST_BUS_UART5>;
dmas = <&dma 19>, <&dma 19>;
dma-names = "tx", "rx";
status = "disabled";
};
i2c0: i2c@2502000 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
dmas = <&dma 43>, <&dma 43>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@2502400 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502400 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
dmas = <&dma 44>, <&dma 44>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@2502800 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502800 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
dmas = <&dma 45>, <&dma 45>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@2502c00 {
compatible = "allwinner,sun20i-d1-i2c",
"allwinner,sun8i-v536-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x2502c00 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
dmas = <&dma 46>, <&dma 46>;
dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
can0: can@2504000 {
compatible = "allwinner,sun20i-d1-can";
reg = <0x02504000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CAN0>;
resets = <&ccu RST_BUS_CAN0>;
pinctrl-names = "default";
pinctrl-0 = <&can0_pins>;
status = "disabled";
};
can1: can@2504400 {
compatible = "allwinner,sun20i-d1-can";
reg = <0x02504400 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CAN1>;
resets = <&ccu RST_BUS_CAN1>;
pinctrl-names = "default";
pinctrl-0 = <&can1_pins>;
status = "disabled";
};
syscon: syscon@3000000 {
compatible = "allwinner,sun20i-d1-system-control";
reg = <0x3000000 0x1000>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
};
dma: dma-controller@3002000 {
compatible = "allwinner,sun20i-d1-dma";
reg = <0x3002000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
clock-names = "bus", "mbus";
resets = <&ccu RST_BUS_DMA>;
dma-channels = <16>;
dma-requests = <48>;
#dma-cells = <1>;
};
sid: efuse@3006000 {
compatible = "allwinner,sun20i-d1-sid";
reg = <0x3006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
crypto: crypto@3040000 {
compatible = "allwinner,sun20i-d1-crypto";
reg = <0x3040000 0x800>;
interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>,
<&ccu CLK_CE>,
<&ccu CLK_MBUS_CE>,
<&rtc CLK_IOSC>;
clock-names = "bus", "mod", "ram", "trng";
resets = <&ccu RST_BUS_CE>;
};
mbus: dram-controller@3102000 {
compatible = "allwinner,sun20i-d1-mbus";
reg = <0x3102000 0x1000>,
<0x3103000 0x1000>;
reg-names = "mbus", "dram";
interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
dma-ranges = <0 0x40000000 0x80000000>;
#address-cells = <1>;
#size-cells = <1>;
#interconnect-cells = <1>;
};
mmc0: mmc@4020000 {
compatible = "allwinner,sun20i-d1-mmc";
reg = <0x4020000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
cap-sd-highspeed;
max-frequency = <150000000>;
no-mmc;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc1: mmc@4021000 {
compatible = "allwinner,sun20i-d1-mmc";
reg = <0x4021000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
cap-sd-highspeed;
max-frequency = <150000000>;
no-mmc;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@4022000 {
compatible = "allwinner,sun20i-d1-emmc",
"allwinner,sun50i-a100-emmc";
reg = <0x4022000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
cap-mmc-highspeed;
max-frequency = <150000000>;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
no-sd;
no-sdio;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi0: spi@4025000 {
compatible = "allwinner,sun20i-d1-spi",
"allwinner,sun50i-r329-spi";
reg = <0x04025000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
dmas = <&dma 22>, <&dma 22>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_SPI0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@4026000 {
compatible = "allwinner,sun20i-d1-spi-dbi",
"allwinner,sun50i-r329-spi-dbi",
"allwinner,sun50i-r329-spi";
reg = <0x04026000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
resets = <&ccu RST_BUS_SPI1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usb_otg: usb@4100000 {
compatible = "allwinner,sun20i-d1-musb",
"allwinner,sun8i-a33-musb";
reg = <0x4100000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
clocks = <&ccu CLK_BUS_OTG>;
resets = <&ccu RST_BUS_OTG>;
extcon = <&usbphy 0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
usbphy: phy@4100400 {
compatible = "allwinner,sun20i-d1-usb-phy";
reg = <0x4100400 0x100>,
<0x4101800 0x100>,
<0x4200800 0x100>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1";
clocks = <&dcxo>,
<&dcxo>;
clock-names = "usb0_phy",
"usb1_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>;
reset-names = "usb0_reset",
"usb1_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci0: usb@4101000 {
compatible = "allwinner,sun20i-d1-ehci",
"generic-ehci";
reg = <0x4101000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_BUS_EHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>,
<&ccu RST_BUS_EHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci0: usb@4101400 {
compatible = "allwinner,sun20i-d1-ohci",
"generic-ohci";
reg = <0x4101400 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ehci1: usb@4200000 {
compatible = "allwinner,sun20i-d1-ehci",
"generic-ehci";
reg = <0x4200000 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_BUS_EHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>,
<&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@4200400 {
compatible = "allwinner,sun20i-d1-ohci",
"generic-ohci";
reg = <0x4200400 0x100>;
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
emac: ethernet@4500000 {
compatible = "allwinner,sun20i-d1-emac",
"allwinner,sun50i-a64-emac";
reg = <0x4500000 0x10000>;
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
syscon = <&syscon>;
status = "disabled";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
};
display_clocks: clock-controller@5000000 {
compatible = "allwinner,sun20i-d1-de2-clk",
"allwinner,sun50i-h5-de2-clk";
reg = <0x5000000 0x10000>;
clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@5100000 {
compatible = "allwinner,sun20i-d1-de2-mixer-0";
reg = <0x5100000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER0>,
<&display_clocks CLK_MIXER0>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon_top_mixer0: endpoint {
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
};
};
};
};
mixer1: mixer@5200000 {
compatible = "allwinner,sun20i-d1-de2-mixer-1";
reg = <0x5200000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER1>,
<&display_clocks CLK_MIXER1>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer1_out: port@1 {
reg = <1>;
mixer1_out_tcon_top_mixer1: endpoint {
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
};
};
};
};
dsi: dsi@5450000 {
compatible = "allwinner,sun20i-d1-mipi-dsi",
"allwinner,sun50i-a100-mipi-dsi";
reg = <0x5450000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&tcon_top CLK_TCON_TOP_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
port {
dsi_in_tcon_lcd0: endpoint {
remote-endpoint = <&tcon_lcd0_out_dsi>;
};
};
};
dphy: phy@5451000 {
compatible = "allwinner,sun20i-d1-mipi-dphy",
"allwinner,sun50i-a100-mipi-dphy";
reg = <0x5451000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_MIPI_DSI>,
<&ccu CLK_MIPI_DSI>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_MIPI_DSI>;
#phy-cells = <0>;
};
tcon_top: tcon-top@5460000 {
compatible = "allwinner,sun20i-d1-tcon-top";
reg = <0x5460000 0x1000>;
clocks = <&ccu CLK_BUS_DPSS_TOP>,
<&ccu CLK_TCON_TV>,
<&ccu CLK_TVE>,
<&ccu CLK_TCON_LCD0>;
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
resets = <&ccu RST_BUS_DPSS_TOP>;
#clock-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_in: port@0 {
reg = <0>;
tcon_top_mixer0_in_mixer0: endpoint {
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
};
};
tcon_top_mixer0_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
};
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
};
};
tcon_top_mixer1_in: port@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer1_in_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
};
};
tcon_top_mixer1_out: port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
};
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
reg = <2>;
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
};
};
tcon_top_hdmi_in: port@4 {
reg = <4>;
tcon_top_hdmi_in_tcon_tv0: endpoint {
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
};
};
tcon_top_hdmi_out: port@5 {
reg = <5>;
};
};
};
tcon_lcd0: lcd-controller@5461000 {
compatible = "allwinner,sun20i-d1-tcon-lcd";
reg = <0x5461000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_LCD0>,
<&ccu CLK_TCON_LCD0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_TCON_LCD0>,
<&ccu RST_BUS_LVDS0>;
reset-names = "lcd", "lvds";
#clock-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
};
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
};
};
tcon_lcd0_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
tcon_lcd0_out_dsi: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in_tcon_lcd0>;
};
};
};
};
tcon_tv0: lcd-controller@5470000 {
compatible = "allwinner,sun20i-d1-tcon-tv";
reg = <0x5470000 0x1000>;
interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON_TV>,
<&tcon_top CLK_TCON_TOP_TV0>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON_TV>;
reset-names = "lcd";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
};
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
reg = <1>;
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
};
};
tcon_tv0_out: port@1 {
reg = <1>;
tcon_tv0_out_tcon_top_hdmi: endpoint {
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
};
};
};
};
ppu: power-controller@7001000 {
compatible = "allwinner,sun20i-d1-ppu";
reg = <0x7001000 0x1000>;
clocks = <&r_ccu CLK_BUS_R_PPU>;
resets = <&r_ccu RST_BUS_R_PPU>;
#power-domain-cells = <1>;
};
r_ccu: clock-controller@7010000 {
compatible = "allwinner,sun20i-d1-r-ccu";
reg = <0x7010000 0x400>;
clocks = <&dcxo>,
<&rtc CLK_OSC32K>,
<&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0_DIV3>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
rtc: rtc@7090000 {
compatible = "allwinner,sun20i-d1-rtc",
"allwinner,sun50i-r329-rtc";
reg = <0x7090000 0x400>;
interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_BUS_R_RTC>,
<&dcxo>,
<&r_ccu CLK_R_AHB>;
clock-names = "bus", "hosc", "ahb";
#clock-cells = <1>;
};
};
};

5
board/sunxi/MAINTAINERS
View File

@ -291,6 +291,11 @@ M: Aleksei Mamlin <mamlinav@gmail.com>
S: Maintained
F: configs/Marsboard_A10_defconfig
MANGOPI MQ-R BOARD
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: configs/mangopi_mq_r_defconfig
MELE I7 BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained

34
board/sunxi/board.c
View File

@ -38,6 +38,7 @@
#include <asm/armv7.h>
#endif
#include <asm/gpio.h>
#include <sunxi_gpio.h>
#include <asm/io.h>
#include <u-boot/crc.h>
#include <env_internal.h>
@ -187,7 +188,7 @@ enum env_location env_get_location(enum env_operation op, int prio)
/* add board specific code here */
int board_init(void)
{
__maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
__maybe_unused int id_pfr1, ret;
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
@ -224,29 +225,6 @@ int board_init(void)
if (ret)
return ret;
/* strcmp() would look better, but doesn't get optimised away. */
if (CONFIG_SATAPWR[0]) {
satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
if (satapwr_pin >= 0) {
gpio_request(satapwr_pin, "satapwr");
gpio_direction_output(satapwr_pin, 1);
/*
* Give the attached SATA device time to power-up
* to avoid link timeouts
*/
mdelay(500);
}
}
if (CONFIG_MACPWR[0]) {
macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
if (macpwr_pin >= 0) {
gpio_request(macpwr_pin, "macpwr");
gpio_direction_output(macpwr_pin, 1);
}
}
#if CONFIG_IS_ENABLED(DM_I2C)
/*
* Temporary workaround for enabling I2C clocks until proper sunxi DM
@ -254,7 +232,6 @@ int board_init(void)
*/
i2c_init_board();
#endif
eth_init_board();
return 0;
@ -482,6 +459,13 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
#elif defined(CONFIG_MACH_SUN8I_R528)
/* SDC2: PC2-PC7 */
for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
#else
puts("ERROR: No pinmux setup defined for MMC2!\n");
#endif

2
board/sunxi/chip.c
View File

@ -12,7 +12,7 @@
#include <w1-eeprom.h>
#include <dm/device-internal.h>
#include <asm/arch/gpio.h>
#include <sunxi_gpio.h>
#include <extension_board.h>

3
common/spl/Kconfig
View File

@ -265,7 +265,7 @@ config SPL_TEXT_BASE
default 0x402F0400 if AM33XX
default 0x40301350 if OMAP54XX
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
default 0x20060 if SUN50I_GEN_H6
default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2
default 0x00060 if ARCH_SUNXI
default 0xfffc0000 if ARCH_ZYNQMP
default 0x0
@ -371,6 +371,7 @@ config SPL_STACK
default 0x91ffb8 if ARCH_MX6 && !MX6_OCRAM_256KB
default 0x118000 if MACH_SUN50I_H6
default 0x58000 if MACH_SUN50I_H616
default 0x40000 if MACH_SUN8I_R528
default 0x54000 if MACH_SUN50I || MACH_SUN50I_H5
default 0x18000 if MACH_SUN9I
default 0x8000 if ARCH_SUNXI

1
configs/A10-OLinuXino-Lime_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
CONFIG_SYS_CLK_FREQ=912000000
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/A20-OLinuXino-Lime2-eMMC_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/A20-OLinuXino-Lime2_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/A20-OLinuXino-Lime_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/A20-OLinuXino_MICRO_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/A20-Olimex-SOM-EVB_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/A20-Olimex-SOM204-EVB_defconfig
View File

@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=384
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/Bananapi_M2_Ultra_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_MACPWR="PA17"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH23"
CONFIG_USB2_VBUS_PIN="PH23"

1
configs/Bananapi_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y

1
configs/Bananapro_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_VIDEO_COMPOSITE=y

1
configs/Cubieboard2_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/Cubieboard_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/Cubietruck_defconfig
View File

@ -8,7 +8,6 @@ CONFIG_USB0_VBUS_PIN="PH17"
CONFIG_USB0_VBUS_DET="PH22"
CONFIG_USB0_ID_DET="PH19"
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PH12"
CONFIG_GMAC_TX_DELAY=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/Itead_Ibox_A20_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_SATAPWR="PB8"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

2
configs/Lamobo_R1_defconfig
View File

@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_SATAPWR="PB3"
CONFIG_GMAC_TX_DELAY=4
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/Linksprite_pcDuino3_Nano_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_SATAPWR="PH2"
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/Linksprite_pcDuino3_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
CONFIG_SATAPWR="PH2"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/Mele_A1000_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_MACPWR="PH15"
CONFIG_VIDEO_VGA=y
CONFIG_VIDEO_COMPOSITE=y
CONFIG_AHCI=y

1
configs/Orangepi_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_VIDEO_VGA=y

1
configs/Orangepi_mini_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"

1
configs/Sinovoip_BPI_M3_defconfig
View File

@ -12,7 +12,6 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_USB0_ID_DET="PH11"
CONFIG_USB1_VBUS_PIN="PD24"
CONFIG_AXP_GPIO=y
CONFIG_SATAPWR="PD25"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y
CONFIG_PHY_REALTEK=y

1
configs/bananapi_m1_plus_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi-m1-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_GMAC_TX_DELAY=3
CONFIG_AHCI=y

1
configs/bananapi_m2_plus_h3_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/bananapi_m2_plus_h5_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/i12-tvbox_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
CONFIG_SPL=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH21"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/jesurun_q5_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
CONFIG_SPL=y
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_MACPWR="PH19"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

15
configs/mangopi_mq_r_defconfig Normal file
View File

@ -0,0 +1,15 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mq-r-t113"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_R528=y
CONFIG_DRAM_CLK=792
CONFIG_DRAM_ZQ=8092667
CONFIG_SUNXI_MINIMUM_DRAM_MB=128
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_DRAM_SUNXI_ODT_EN=0
CONFIG_DRAM_SUNXI_TPR0=0x004a2195
CONFIG_DRAM_SUNXI_TPR11=0x340000
CONFIG_DRAM_SUNXI_TPR12=0x46
CONFIG_DRAM_SUNXI_TPR13=0x34000100
CONFIG_CONS_INDEX=4

1
configs/mixtile_loftq_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
CONFIG_SPL=y
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MACPWR="PA21"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_USB2_VBUS_PIN=""

1
configs/nanopi_m1_plus_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/nanopi_neo_plus2_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/nanopi_r1s_h5_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
# CONFIG_DRAM_ODT_EN is not set
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y

1
configs/orangepi_pc2_defconfig
View File

@ -5,7 +5,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

1
configs/orangepi_plus2e_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus2e"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y

3
configs/orangepi_plus_defconfig
View File

@ -4,10 +4,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_MACPWR="PD6"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_SATAPWR="PG11"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
@ -16,3 +14,4 @@ CONFIG_SUN8I_EMAC=y
CONFIG_SY8106A_POWER=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB3_VBUS_PIN="PG11"

1
configs/orangepi_win_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_MACPWR="PD14"
CONFIG_SPL_SPI_SUNXI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPI_FLASH_WINBOND=y

1
configs/pine_h64_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-pine-h64"
CONFIG_SPL=y
CONFIG_MACH_SUN50I_H6=y
CONFIG_SUNXI_DRAM_H6_LPDDR3=y
CONFIG_MACPWR="PC16"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB3_VBUS_PIN="PL5"
CONFIG_SPL_SPI_SUNXI=y

1
configs/zeropi_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_MACPWR="PD6"
# CONFIG_VIDEO_DE2 is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_CONSOLE_MUX=y

1
drivers/Makefile
View File

@ -57,6 +57,7 @@ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
obj-$(CONFIG_DRAM_SUN20I_D1) += ram/
obj-$(CONFIG_SPL_DM_RESET) += reset/
obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/

9
drivers/ata/ahci_sunxi.c
View File

@ -7,6 +7,7 @@
#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/delay.h>
#include <power/regulator.h>
#define AHCI_PHYCS0R 0x00c0
#define AHCI_PHYCS1R 0x00c4
@ -74,6 +75,7 @@ static int sunxi_ahci_phy_init(u8 *reg_base)
static int sunxi_sata_probe(struct udevice *dev)
{
struct udevice *reg_dev;
ulong base;
u8 *reg;
int ret;
@ -89,6 +91,13 @@ static int sunxi_sata_probe(struct udevice *dev)
debug("%s: Failed to init phy (err=%d)\n", __func__, ret);
return ret;
}
ret = device_get_supply_regulator(dev, "target-supply", &reg_dev);
if (ret == 0) {
regulator_set_enable(reg_dev, true);
mdelay(500);
}
ret = ahci_probe_scsi(dev, base);
if (ret) {
debug("%s: Failed to probe (err=%d)\n", __func__, ret);

7
drivers/clk/sunxi/Kconfig
View File

@ -87,6 +87,13 @@ config CLK_SUN8I_H3
This enables common clock driver support for platforms based
on Allwinner H3/H5 SoC.
config CLK_SUN20I_D1
bool "Clock driver for Allwinner D1"
default MACH_SUN8I_R528
help
This enables common clock driver support for platforms based
on Allwinner D1 SoC.
config CLK_SUN50I_H6
bool "Clock driver for Allwinner H6"
default MACH_SUN50I_H6

1
drivers/clk/sunxi/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o

84
drivers/clk/sunxi/clk_d1.c Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#include <linux/bitops.h>
static struct ccu_clk_gate d1_gates[] = {
[CLK_APB0] = GATE_DUMMY,
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
[CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
[CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
[CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
[CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
[CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
[CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
[CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
[CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
[CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
[CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
[CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
[CLK_RISCV] = GATE(0xd04, BIT(31)),
};
static struct ccu_reset d1_resets[] = {
[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
[RST_BUS_UART0] = RESET(0x90c, BIT(16)),
[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
[RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
[RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
[RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
[RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
[RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
[RST_USB_PHY0] = RESET(0xa70, BIT(30)),
[RST_USB_PHY1] = RESET(0xa74, BIT(30)),
[RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
[RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
[RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
[RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
[RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
};
const struct ccu_desc d1_ccu_desc = {
.gates = d1_gates,
.resets = d1_resets,
.num_gates = ARRAY_SIZE(d1_gates),
.num_resets = ARRAY_SIZE(d1_resets),
};

5
drivers/clk/sunxi/clk_sunxi.c
View File

@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_desc;
extern const struct ccu_desc a80_ccu_desc;
extern const struct ccu_desc a80_mmc_clk_desc;
extern const struct ccu_desc a83t_ccu_desc;
extern const struct ccu_desc d1_ccu_desc;
extern const struct ccu_desc f1c100s_ccu_desc;
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
@ -195,6 +196,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
{ .compatible = "allwinner,sun50i-h5-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN20I_D1
{ .compatible = "allwinner,sun20i-d1-ccu",
.data = (ulong)&d1_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6
{ .compatible = "allwinner,sun50i-h6-ccu",
.data = (ulong)&h6_ccu_desc },

7
drivers/gpio/Kconfig
View File

@ -372,6 +372,13 @@ config SUNXI_GPIO
help
Support the GPIO device in Allwinner SoCs.
config SUNXI_NEW_PINCTRL
bool
depends on SUNXI_GPIO
---help---
The Allwinner D1 and other new SoCs use a different register map
for the GPIO block, which we need to know about in the SPL.
config XILINX_GPIO
bool "Xilinx GPIO driver"
depends on DM_GPIO

1
drivers/gpio/axp_gpio.c
View File

@ -14,6 +14,7 @@
#include <dm/lists.h>
#include <dm/root.h>
#include <errno.h>
#include <sunxi_gpio.h>
static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);

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