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sunxi: Enable additional UART2 pinmux on PORTG.

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This patch enables additional pinmux for UART2 on PORT G PG17/PG18. This
is available on certain sun8i devices, e.g. T113

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2024-01-11 00:11:11 +08:00
parent 89e8047f7a
commit aca390cb24
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
4 changed files with 14 additions and 0 deletions
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5
arch/arm/mach-sunxi/Kconfig
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@ -729,6 +729,11 @@ config UART0_PORT_F
at the same time, the system can be only booted in the FEL mode.
Only enable this if you really know what you are doing.
config UART2_PORT_G
bool "UART2 on Port G"
---help---
Select this option for boards where UART2 uses the Port G pinmux.
config UART2_PORT_E
bool "UART2 on PE2 and PE3 pins"
---help---

6
arch/arm/mach-sunxi/board.c
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@ -172,6 +172,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 3);
sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 3);
sunxi_gpio_set_pull(SUNXI_GPE(2), SUNXI_GPIO_PULL_UP);
#elif IS_ENABLED(CONFIG_UART2_PORT_G)
sunxi_gpio_set_cfgpin(SUNXI_GPG(17), SUN8I_R528_GPG_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPG(18), SUN8I_R528_GPG_UART2);
sunxi_gpio_set_pull(SUNXI_GPG(18), SUNXI_GPIO_PULL_UP);
#else
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 7);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 7);
@ -476,6 +480,8 @@ void board_init_f(ulong dummy)
{
sunxi_sram_init();
spl_early_init();
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
/* Enable non-secure access to some peripherals */
tzpc_init();

2
drivers/pinctrl/sunxi/pinctrl-sunxi.c
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@ -615,6 +615,8 @@ static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
{ "uart1", 2 }, /* PG6-PG7 */
#if IS_ENABLED(CONFIG_UART2_PORT_E)
{ "uart2", 3 }, /* PE2-PE3 */
#elif IS_ENABLED(CONFIG_UART2_PORT_G)
{ "uart2", 2 }, /* PG17-PG18 */
#else
{ "uart2", 7 }, /* PB0-PB1 */
#endif

1
include/sunxi_gpio.h
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@ -142,6 +142,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN8I_GPG_UART1 2
#define SUN8I_R528_GPG_UART2 2
#define SUN5I_GPG_UART1 4
#define SUN6I_GPH_PWM 2