clk: qcom: add support for power domains uclass
Now sub-drivers for particular SoCs can register them as power domain drivers. This is needed for upcoming SM8150 support, because it needs to power up the Ethernet module. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> [caleb: make ARCH_SNAPDRAGON select POWER_DOMAIN] Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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@ -1078,6 +1078,7 @@ config ARCH_SNAPDRAGON
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select DM_GPIO
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select DM_SERIAL
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select DM_RESET
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select POWER_DOMAIN
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select GPIO_EXTRA_HEADER
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select MSM_SMEM
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select OF_CONTROL
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@ -2,7 +2,7 @@ if ARCH_SNAPDRAGON || ARCH_IPQ40XX
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config CLK_QCOM
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bool
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depends on CLK && DM_RESET
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depends on CLK && DM_RESET && POWER_DOMAIN
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def_bool n
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menu "Qualcomm clock drivers"
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@ -22,7 +22,9 @@
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <linux/iopoll.h>
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#include <reset-uclass.h>
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#include <power-domain-uclass.h>
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#include "clock-qcom.h"
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@ -30,6 +32,13 @@
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#define CBCR_BRANCH_ENABLE_BIT BIT(0)
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#define CBCR_BRANCH_OFF_BIT BIT(31)
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#define GDSC_SW_COLLAPSE_MASK BIT(0)
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#define GDSC_POWER_DOWN_COMPLETE BIT(15)
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#define GDSC_POWER_UP_COMPLETE BIT(16)
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#define GDSC_PWR_ON_MASK BIT(31)
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#define CFG_GDSCR_OFFSET 0x4
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#define GDSC_STATUS_POLL_TIMEOUT_US 1500
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/* Enable clock controlled by CBC soft macro */
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void clk_enable_cbc(phys_addr_t cbcr)
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{
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@ -223,7 +232,7 @@ U_BOOT_DRIVER(qcom_clk) = {
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int qcom_cc_bind(struct udevice *parent)
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{
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struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(parent);
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struct udevice *clkdev, *rstdev;
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struct udevice *clkdev = NULL, *rstdev = NULL, *pwrdev;
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struct driver *drv;
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int ret;
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@ -238,20 +247,41 @@ int qcom_cc_bind(struct udevice *parent)
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if (ret)
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return ret;
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/* Bail out early if resets are not specified for this platform */
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if (!data->resets)
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return ret;
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if (data->resets) {
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/* Get a handle to the common reset handler */
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drv = lists_driver_lookup_name("qcom_reset");
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if (!drv) {
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ret = -ENOENT;
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goto unbind_clkdev;
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}
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/* Get a handle to the common reset handler */
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drv = lists_driver_lookup_name("qcom_reset");
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if (!drv)
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return -ENOENT;
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/* Register the reset controller */
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ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
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dev_ofnode(parent), &rstdev);
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if (ret)
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goto unbind_clkdev;
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}
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/* Register the reset controller */
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ret = device_bind_with_driver_data(parent, drv, "qcom_reset", (ulong)data,
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dev_ofnode(parent), &rstdev);
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if (ret)
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device_unbind(clkdev);
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if (data->power_domains) {
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/* Get a handle to the common power domain handler */
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drv = lists_driver_lookup_name("qcom_power");
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if (!drv) {
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ret = -ENOENT;
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goto unbind_rstdev;
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}
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/* Register the power domain controller */
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ret = device_bind_with_driver_data(parent, drv, "qcom_power", (ulong)data,
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dev_ofnode(parent), &pwrdev);
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if (ret)
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goto unbind_rstdev;
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}
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return 0;
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unbind_rstdev:
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device_unbind(rstdev);
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unbind_clkdev:
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device_unbind(clkdev);
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return ret;
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}
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@ -306,3 +336,79 @@ U_BOOT_DRIVER(qcom_reset) = {
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.ops = &qcom_reset_ops,
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.probe = qcom_reset_probe,
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};
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static int qcom_power_set(struct power_domain *pwr, bool on)
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{
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struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
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void __iomem *base = dev_get_priv(pwr->dev);
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const struct qcom_power_map *map;
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u32 value;
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int ret;
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if (pwr->id >= data->num_power_domains)
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return -ENODEV;
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map = &data->power_domains[pwr->id];
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if (!map->reg)
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return -ENODEV;
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value = readl(base + map->reg);
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if (on)
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value &= ~GDSC_SW_COLLAPSE_MASK;
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else
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value |= GDSC_SW_COLLAPSE_MASK;
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writel(value, base + map->reg);
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if (on)
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ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
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value,
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(value & GDSC_POWER_UP_COMPLETE) ||
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(value & GDSC_PWR_ON_MASK),
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GDSC_STATUS_POLL_TIMEOUT_US);
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else
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ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
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value,
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(value & GDSC_POWER_DOWN_COMPLETE) ||
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!(value & GDSC_PWR_ON_MASK),
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GDSC_STATUS_POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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printf("WARNING: GDSC %lu is stuck during power on/off\n",
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pwr->id);
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return ret;
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}
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static int qcom_power_on(struct power_domain *pwr)
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{
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return qcom_power_set(pwr, true);
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}
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static int qcom_power_off(struct power_domain *pwr)
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{
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return qcom_power_set(pwr, false);
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}
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static const struct power_domain_ops qcom_power_ops = {
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.on = qcom_power_on,
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.off = qcom_power_off,
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};
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static int qcom_power_probe(struct udevice *dev)
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{
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/* Set our priv pointer to the base address */
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dev_set_priv(dev, (void *)dev_read_addr(dev));
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return 0;
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}
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U_BOOT_DRIVER(qcom_power) = {
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.name = "qcom_power",
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.id = UCLASS_POWER_DOMAIN,
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.ops = &qcom_power_ops,
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.probe = qcom_power_probe,
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};
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@ -59,9 +59,15 @@ struct qcom_reset_map {
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u8 bit;
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};
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struct qcom_power_map {
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unsigned int reg;
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};
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struct clk;
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struct msm_clk_data {
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const struct qcom_power_map *power_domains;
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unsigned long num_power_domains;
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const struct qcom_reset_map *resets;
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unsigned long num_resets;
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const struct gate_clk *clks;
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