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STM32 MCU:

Browse Source 
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
   _ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
 
 STM32 MPU:
   _ alignment with kernel DT v6.6-rc1
   _ add RNG support for stm32mp13
   _ add USB, USB boot and stm32prog command support for stm32mp13
   _ add support of USART1 clock for stm32mp1
   _ only print RAM and board code with SPL_DISPLAY_PRINT flag for
     stm32mp1
   _ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
     for stm32mp15xx DHCOR
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Merge tag 'u-boot-stm32-20231004' of https://source.denx.de/u-boot/custodians/u-boot-stm

STM32 MCU:
  _ alignment with kernel DT v6.5 for stm32f429 and stm32f746
  _ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco

STM32 MPU:
  _ alignment with kernel DT v6.6-rc1
  _ add RNG support for stm32mp13
  _ add USB, USB boot and stm32prog command support for stm32mp13
  _ add support of USART1 clock for stm32mp1
  _ only print RAM and board code with SPL_DISPLAY_PRINT flag for
    stm32mp1
  _ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
    for stm32mp15xx DHCOR

[ Fix merge conflict at board/st/common/stm32mp_dfu.c ]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2023-10-04 10:49:30 -04:00
commit b83e285866
53 changed files with 1534 additions and 3837 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -622,7 +622,7 @@ F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32-reset.c
F: drivers/rng/optee_rng.c
F: drivers/rng/stm32mp1_rng.c
F: drivers/rng/stm32_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_qspi.c

30
arch/arm/dts/stm32f4-pinctrl.dtsi
View File

@ -412,6 +412,36 @@
slew-rate = <2>;
};
};
can1_pins_a: can1-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
bias-pull-up;
};
};
can2_pins_a: can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
bias-pull-up;
};
};
can2_pins_b: can2-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
bias-pull-up;
};
};
};
};
};

30
arch/arm/dts/stm32f429.dtsi
View File

@ -321,6 +321,36 @@
status = "disabled";
};
can1: can@40006400 {
compatible = "st,stm32f4-bxcan";
reg = <0x40006400 0x200>;
interrupts = <19>, <20>, <21>, <22>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
st,can-primary;
st,gcan = <&gcan>;
status = "disabled";
};
gcan: gcan@40006600 {
compatible = "st,stm32f4-gcan", "syscon";
reg = <0x40006600 0x200>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
};
can2: can@40006800 {
compatible = "st,stm32f4-bxcan";
reg = <0x40006800 0x200>;
interrupts = <63>, <64>, <65>, <66>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
st,can-secondary;
st,gcan = <&gcan>;
status = "disabled";
};
dac: dac@40007400 {
compatible = "st,stm32f4-dac-core";
reg = <0x40007400 0x400>;

126
arch/arm/dts/stm32f7-pinctrl.dtsi
View File

@ -172,6 +172,16 @@
};
};
i2c3_pins_a: i2c3-0 {
pins {
pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
<STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
@ -284,6 +294,122 @@
slew-rate = <2>;
};
};
can1_pins_a: can1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
bias-pull-up;
};
};
can1_pins_b: can1-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
bias-pull-up;
};
};
can1_pins_c: can1-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
bias-pull-up;
};
};
can1_pins_d: can1-3 {
pins1 {
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
bias-pull-up;
};
};
can2_pins_a: can2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
bias-pull-up;
};
};
can2_pins_b: can2-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
bias-pull-up;
};
};
can3_pins_a: can3-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
};
pins2 {
pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
bias-pull-up;
};
};
can3_pins_b: can3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
bias-pull-up;
};
};
ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
<STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
<STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
<STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
<STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
<STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
<STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
<STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
slew-rate = <2>;
};
};
};
};
};

103
arch/arm/dts/stm32f746-disco-u-boot.dtsi
View File

@ -23,12 +23,6 @@
spi0 = &qspi;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpiok 3 0>;
status = "okay";
};
button1 {
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
@ -38,44 +32,11 @@
compatible = "st,led1";
led-gpio = <&gpioi 1 0>;
};
};
panel-rgb@0 {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpioi 12 0>;
status = "okay";
display-timings {
timing@0 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <2>;
hback-porch = <2>;
hsync-len = <41>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
soc {
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;
resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
pinctrl-0 = <&ltdc_pins>;
status = "okay";
bootph-all;
};
};
&ltdc {
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
bootph-all;
};
&fmc {
@ -102,6 +63,28 @@
};
};
&panel_rgb {
compatible = "simple-panel";
display-timings {
timing@0 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <2>;
hback-porch = <2>;
hsync-len = <41>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
&pinctrl {
ethernet_mii: mii@0 {
pins {
@ -166,40 +149,6 @@
};
};
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
<STM32_PINMUX('G',12, AF9)>, /* B4 */
<STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
<STM32_PINMUX('I',10, AF14)>, /* HSYNC */
<STM32_PINMUX('I',14, AF14)>, /* CLK */
<STM32_PINMUX('I',15, AF14)>, /* R0 */
<STM32_PINMUX('J', 0, AF14)>, /* R1 */
<STM32_PINMUX('J', 1, AF14)>, /* R2 */
<STM32_PINMUX('J', 2, AF14)>, /* R3 */
<STM32_PINMUX('J', 3, AF14)>, /* R4 */
<STM32_PINMUX('J', 4, AF14)>, /* R5 */
<STM32_PINMUX('J', 5, AF14)>, /* R6 */
<STM32_PINMUX('J', 6, AF14)>, /* R7 */
<STM32_PINMUX('J', 7, AF14)>, /* G0 */
<STM32_PINMUX('J', 8, AF14)>, /* G1 */
<STM32_PINMUX('J', 9, AF14)>, /* G2 */
<STM32_PINMUX('J',10, AF14)>, /* G3 */
<STM32_PINMUX('J',11, AF14)>, /* G4 */
<STM32_PINMUX('J',13, AF14)>, /* B1 */
<STM32_PINMUX('J',14, AF14)>, /* B2 */
<STM32_PINMUX('J',15, AF14)>, /* B3 */
<STM32_PINMUX('K', 0, AF14)>, /* G5 */
<STM32_PINMUX('K', 1, AF14)>, /* G6 */
<STM32_PINMUX('K', 2, AF14)>, /* G7 */
<STM32_PINMUX('K', 4, AF14)>, /* B5 */
<STM32_PINMUX('K', 5, AF14)>, /* B6 */
<STM32_PINMUX('K', 6, AF14)>, /* B7 */
<STM32_PINMUX('K', 7, AF14)>; /* DE */
slew-rate = <2>;
};
};
qspi_pins: qspi@0 {
pins {
pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */

69
arch/arm/dts/stm32f746-disco.dts
View File

@ -7,8 +7,9 @@
/dts-v1/;
#include "stm32f746.dtsi"
#include "stm32f746-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "STMicroelectronics STM32F746-DISCO board";
@ -24,6 +25,19 @@
reg = <0xC0000000 0x800000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
no-map;
size = <0x80000>;
linux,dma-default;
};
};
aliases {
serial0 = &usart1;
};
@ -43,12 +57,31 @@
regulator-always-on;
};
mmc_vcard: mmc_vcard {
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "mmc_vcard";
regulator-name = "vcc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
backlight: backlight {
compatible = "gpio-backlight";
gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
panel_rgb: panel-rgb {
compatible = "rocktech,rk043fn48h";
power-supply = <&vcc_3v3>;
backlight = <&backlight>;
enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
status = "okay";
port {
panel_in_rgb: endpoint {
remote-endpoint = <&ltdc_out_rgb>;
};
};
};
};
&clk_hse {
@ -63,9 +96,37 @@
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_pins_a>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5306";
reg = <0x38>;
interrupt-parent = <&gpioi>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
};
};
&ltdc {
pinctrl-0 = <&ltdc_pins_a>;
pinctrl-names = "default";
status = "okay";
port {
ltdc_out_rgb: endpoint {
remote-endpoint = <&panel_in_rgb>;
};
};
};
&sdio1 {
status = "okay";
vmmc-supply = <&mmc_vcard>;
vmmc-supply = <&vcc_3v3>;
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "opendrain";
pinctrl-0 = <&sdio_pins_a>;

59
arch/arm/dts/stm32f746.dtsi
View File

@ -221,6 +221,23 @@
status = "disabled";
};
can3: can@40003400 {
compatible = "st,stm32f4-bxcan";
reg = <0x40003400 0x200>;
interrupts = <104>, <105>, <106>, <107>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
st,gcan = <&gcan3>;
status = "disabled";
};
gcan3: gcan@40003600 {
compatible = "st,stm32f4-gcan", "syscon";
reg = <0x40003600 0x200>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
};
usart2: serial@40004400 {
compatible = "st,stm32f7-uart";
reg = <0x40004400 0x400>;
@ -301,6 +318,36 @@
status = "disabled";
};
can1: can@40006400 {
compatible = "st,stm32f4-bxcan";
reg = <0x40006400 0x200>;
interrupts = <19>, <20>, <21>, <22>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
st,can-primary;
st,gcan = <&gcan1>;
status = "disabled";
};
gcan1: gcan@40006600 {
compatible = "st,stm32f4-gcan", "syscon";
reg = <0x40006600 0x200>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
};
can2: can@40006800 {
compatible = "st,stm32f4-bxcan";
reg = <0x40006800 0x200>;
interrupts = <63>, <64>, <65>, <66>;
interrupt-names = "tx", "rx0", "rx1", "sce";
resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
st,can-secondary;
st,gcan = <&gcan1>;
status = "disabled";
};
cec: cec@40006c00 {
compatible = "st,stm32-cec";
reg = <0x40006C00 0x400>;
@ -471,6 +518,16 @@
};
};
ltdc: display-controller@40016800 {
compatible = "st,stm32-ltdc";
reg = <0x40016800 0x200>;
interrupts = <88>, <89>;
resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
clocks = <&rcc 1 CLK_LCD>;
clock-names = "lcd";
status = "disabled";
};
pwrcfg: power-config@40007000 {
compatible = "st,stm32-power-config", "syscon";
reg = <0x40007000 0x400>;
@ -479,7 +536,7 @@
crc: crc@40023000 {
compatible = "st,stm32f7-crc";
reg = <0x40023000 0x400>;
clocks = <&rcc 0 12>;
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
status = "disabled";
};

60
arch/arm/dts/stm32mp131.dtsi
View File

@ -33,6 +33,8 @@
optee {
method = "smc";
compatible = "linaro,optee-tz";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi: scmi {
@ -50,6 +52,28 @@
reg = <0x16>;
#reset-cells = <1>;
};
scmi_voltd: protocol@17 {
reg = <0x17>;
scmi_regu: regulators {
#address-cells = <1>;
#size-cells = <0>;
scmi_reg11: regulator@0 {
reg = <VOLTD_SCMI_REG11>;
regulator-name = "reg11";
};
scmi_reg18: regulator@1 {
reg = <VOLTD_SCMI_REG18>;
regulator-name = "reg18";
};
scmi_usb33: regulator@2 {
reg = <VOLTD_SCMI_USB33>;
regulator-name = "usb33";
};
};
};
};
};
@ -76,28 +100,6 @@
always-on;
};
/* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
reg11: reg11 {
compatible = "regulator-fixed";
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
reg18: reg18 {
compatible = "regulator-fixed";
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
usb33: usb33 {
compatible = "regulator-fixed";
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -799,7 +801,7 @@
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
dr_mode = "otg";
otg-rev = <0x200>;
usb33d-supply = <&usb33>;
usb33d-supply = <&scmi_usb33>;
status = "disabled";
};
@ -1208,6 +1210,14 @@
};
};
rng: rng@54004000 {
compatible = "st,stm32mp13-rng";
reg = <0x54004000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
status = "disabled";
};
mdma: dma-controller@58000000 {
compatible = "st,stm32h7-mdma";
reg = <0x58000000 0x1000>;
@ -1329,8 +1339,8 @@
reg = <0x5a006000 0x1000>;
clocks = <&rcc USBPHY_K>;
resets = <&rcc USBPHY_R>;
vdda1v1-supply = <&reg11>;
vdda1v8-supply = <&reg18>;
vdda1v1-supply = <&scmi_reg11>;
vdda1v8-supply = <&scmi_reg18>;
status = "disabled";
usbphyc_port0: usb-phy@0 {

4
arch/arm/dts/stm32mp135f-dk-u-boot.dtsi
View File

@ -38,3 +38,7 @@
bootph-all;
};
};
&usbotg_hs {
u-boot,force-b-session-valid;
};

68
arch/arm/dts/stm32mp135f-dk.dts
View File

@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
#include "stm32mp135.dtsi"
#include "stm32mp13xf.dtsi"
#include "stm32mp13-pinctrl.dtsi"
@ -65,45 +66,13 @@
default-state = "off";
};
};
v3v3_sw: v3v3-sw {
compatible = "regulator-fixed";
regulator-name = "v3v3_sw";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_adc: vdd-adc {
compatible = "regulator-fixed";
regulator-name = "vdd_adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sd: vdd-sd {
compatible = "regulator-fixed";
regulator-name = "vdd_sd";
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
vdd_usb: vdd-usb {
compatible = "regulator-fixed";
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&adc_1 {
pinctrl-names = "default";
pinctrl-0 = <&adc1_usb_cc_pins_a>;
vdda-supply = <&vdd_adc>;
vref-supply = <&vdd_adc>;
vdda-supply = <&scmi_vdd_adc>;
vref-supply = <&scmi_vdd_adc>;
status = "okay";
adc1: adc@0 {
status = "okay";
@ -195,6 +164,29 @@
status = "okay";
};
&scmi_regu {
scmi_vdd_adc: regulator@10 {
reg = <VOLTD_SCMI_STPMIC1_LDO1>;
regulator-name = "vdd_adc";
};
scmi_vdd_usb: regulator@13 {
reg = <VOLTD_SCMI_STPMIC1_LDO4>;
regulator-name = "vdd_usb";
};
scmi_vdd_sd: regulator@14 {
reg = <VOLTD_SCMI_STPMIC1_LDO5>;
regulator-name = "vdd_sd";
};
scmi_v1v8_periph: regulator@15 {
reg = <VOLTD_SCMI_STPMIC1_LDO6>;
regulator-name = "v1v8_periph";
};
scmi_v3v3_sw: regulator@19 {
reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
regulator-name = "v3v3_sw";
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
@ -204,7 +196,7 @@
disable-wp;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vmmc-supply = <&scmi_vdd_sd>;
status = "okay";
};
@ -321,7 +313,7 @@
hub@1 {
compatible = "usb424,2514";
reg = <1>;
vdd-supply = <&v3v3_sw>;
vdd-supply = <&scmi_v3v3_sw>;
};
};
@ -342,7 +334,7 @@
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
phy-supply = <&scmi_vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;
@ -356,7 +348,7 @@
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
phy-supply = <&scmi_vdd_usb>;
st,current-boost-microamp = <1000>;
st,decrease-hs-slew-rate;
st,tune-hs-dc-level = <2>;

364
arch/arm/dts/stm32mp15-pinctrl.dtsi
View File

@ -6,6 +6,17 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
adc1_ain_pins_a: adc1-ain-0 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */
<STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */
<STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */
<STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */
<STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */
};
};
adc1_in6_pins_a: adc1-in6-0 {
pins {
pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
@ -341,6 +352,96 @@
};
};
ethernet0_rgmii_pins_d: rgmii-3 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins3 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
};
ethernet0_rgmii_sleep_pins_d: rgmii-sleep-3 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
};
};
ethernet0_rgmii_pins_e: rgmii-4 {
pins1 {
pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
};
ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 {
pins1 {
pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
<STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
};
};
ethernet0_rmii_pins_a: rmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
@ -1104,6 +1205,20 @@
};
};
pwm1_pins_c: pwm1-2 {
pins {
pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */
drive-push-pull;
slew-rate = <0>;
};
};
pwm1_sleep_pins_c: pwm1-sleep-2 {
pins {
pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */
};
};
pwm2_pins_a: pwm2-0 {
pins {
pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
@ -1230,6 +1345,26 @@
};
};
pwm8_pins_b: pwm8-1 {
pins {
pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */
<STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */
<STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */
<STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */
drive-push-pull;
slew-rate = <0>;
};
};
pwm8_sleep_pins_b: pwm8-sleep-1 {
pins {
pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */
<STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */
<STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */
<STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */
};
};
pwm12_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
@ -1441,6 +1576,30 @@
};
};
sai2b_pins_d: sai2b-3 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, AF10)>, /* SAI2_SCK_B */
<STM32_PINMUX('C', 0, AF8)>, /* SAI2_FS_B */
<STM32_PINMUX('H', 3, AF10)>; /* SAI2_MCLK_B */
slew-rate = <0>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_d: sai2b-sleep-3 {
pins1 {
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* SAI2_SCK_B */
<STM32_PINMUX('C', 0, ANALOG)>, /* SAI2_FS_B */
<STM32_PINMUX('H', 3, ANALOG)>, /* SAI2_MCLK_B */
<STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};
};
sai4a_pins_a: sai4a-0 {
pins {
pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
@ -1522,6 +1681,60 @@
};
};
sdmmc1_b4_pins_b: sdmmc1-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <2>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_b4_od_pins_b: sdmmc1-b4-od-1 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, AF8)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
slew-rate = <1>;
drive-push-pull;
bias-disable;
};
pins2 {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
slew-rate = <2>;
drive-push-pull;
bias-disable;
};
pins3 {
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <1>;
drive-open-drain;
bias-disable;
};
};
sdmmc1_b4_sleep_pins_b: sdmmc1-b4-sleep-1 {
pins {
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
<STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
};
};
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@ -1531,7 +1744,7 @@
drive-push-pull;
bias-pull-up;
};
pins2{
pins2 {
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up;
};
@ -1566,7 +1779,7 @@
drive-push-pull;
bias-pull-up;
};
pins2{
pins2 {
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up;
};
@ -1759,6 +1972,27 @@
};
};
sdmmc2_d47_pins_e: sdmmc2-d47-4 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
slew-rate = <1>;
drive-push-pull;
bias-pull-up;
};
};
sdmmc2_d47_sleep_pins_e: sdmmc2-d47-sleep-4 {
pins {
pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
<STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
<STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
};
};
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
@ -1925,6 +2159,20 @@
};
};
spi2_pins_c: spi2-2 {
pins1 {
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */
<STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
bias-disable;
drive-push-pull;
};
pins2 {
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
bias-pull-down;
};
};
spi4_pins_a: spi4-0 {
pins {
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
@ -1939,6 +2187,21 @@
};
};
spi5_pins_a: spi5-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */
<STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */
bias-disable;
};
};
stusb1600_pins_a: stusb1600-0 {
pins {
pinmux = <STM32_PINMUX('I', 11, GPIO)>;
@ -2124,6 +2387,33 @@
};
};
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 12, AF7)>; /* USART1_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
bias-disable;
};
};
usart1_idle_pins_a: usart1-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 11, AF7)>; /* USART1_CTS_NSS */
};
};
usart1_sleep_pins_a: usart1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* USART1_RTS */
<STM32_PINMUX('A', 11, ANALOG)>; /* USART1_CTS_NSS */
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@ -2226,6 +2516,23 @@
};
};
usart3_idle_pins_a: usart3-idle-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>; /* USART3_TX */
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
bias-disable;
};
};
usart3_sleep_pins_a: usart3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
<STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
};
};
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@ -2385,6 +2692,21 @@
};
};
usart3_pins_f: usart3-5 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
<STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
bias-disable;
};
};
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
@ -2463,4 +2785,42 @@
bias-disable;
};
};
spi1_sleep_pins_a: spi1-sleep-0 {
pins {
pinmux = <STM32_PINMUX('Z', 0, ANALOG)>, /* SPI1_SCK */
<STM32_PINMUX('Z', 1, ANALOG)>, /* SPI1_MISO */
<STM32_PINMUX('Z', 2, ANALOG)>; /* SPI1_MOSI */
};
};
usart1_pins_b: usart1-1 {
pins1 {
pinmux = <STM32_PINMUX('Z', 7, AF7)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_idle_pins_b: usart1-idle-1 {
pins1 {
pinmux = <STM32_PINMUX('Z', 7, ANALOG)>; /* USART1_TX */
};
pins2 {
pinmux = <STM32_PINMUX('Z', 6, AF7)>; /* USART1_RX */
bias-disable;
};
};
usart1_sleep_pins_b: usart1-sleep-1 {
pins {
pinmux = <STM32_PINMUX('Z', 7, ANALOG)>, /* USART1_TX */
<STM32_PINMUX('Z', 6, ANALOG)>; /* USART1_RX */
};
};
};

7
arch/arm/dts/stm32mp15-scmi.dtsi
View File

@ -34,22 +34,21 @@
#address-cells = <1>;
#size-cells = <0>;
scmi_reg11: reg11@0 {
scmi_reg11: regulator@0 {
reg = <0>;
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
scmi_reg18: reg18@1 {
voltd-name = "reg18";
scmi_reg18: regulator@1 {
reg = <1>;
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
scmi_usb33: usb33@2 {
scmi_usb33: regulator@2 {
reg = <2>;
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;

34
arch/arm/dts/stm32mp151.dtsi
View File

@ -1111,6 +1111,8 @@
adc1: adc@0 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
@ -1122,12 +1124,24 @@
adc2: adc@100 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
dmas = <&dmamux1 10 0x400 0x01>;
dma-names = "rx";
nvmem-cells = <&vrefint>;
nvmem-cell-names = "vrefint";
status = "disabled";
channel@13 {
reg = <13>;
label = "vrefint";
};
channel@14 {
reg = <14>;
label = "vddcore";
};
};
};
@ -1162,14 +1176,6 @@
status = "disabled";
};
hwspinlock: hwspinlock@4c000000 {
compatible = "st,stm32-hwspinlock";
#hwlock-cells = <1>;
reg = <0x4c000000 0x400>;
clocks = <&rcc HSEM>;
clock-names = "hwspinlock";
};
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
@ -1559,11 +1565,6 @@
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
};
};
iwdg2: watchdog@5a002000 {
@ -1650,9 +1651,12 @@
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
part_number_otp: part_number_otp@4 {
part_number_otp: part-number-otp@4 {
reg = <0x4 0x1>;
};
vrefint: vrefin-cal@52 {
reg = <0x52 0x2>;
};
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
@ -1853,8 +1857,8 @@
<0x30000000 0x40000>,
<0x38000000 0x10000>;
resets = <&rcc MCU_R>;
reset-names = "mcu_rst";
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;

15
arch/arm/dts/stm32mp157.dtsi
View File

@ -22,15 +22,26 @@
reg = <0x5a000000 0x800>;
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
clock-names = "pclk", "ref", "px_clk";
phy-dsi-supply = <&reg18>;
resets = <&rcc DSI_R>;
reset-names = "apb";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
};
};
};
};
};

7
arch/arm/dts/stm32mp157a-dk1-scmi.dts
View File

@ -55,8 +55,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

3
arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
View File

@ -81,6 +81,9 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in>;

7
arch/arm/dts/stm32mp157c-dk2-scmi.dts
View File

@ -61,8 +61,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

30
arch/arm/dts/stm32mp157c-dk2.dts
View File

@ -31,24 +31,9 @@
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
phy-dsi-supply = <&reg18>;
ports {
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_ep1_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
panel@0 {
compatible = "orisetech,otm8009a";
@ -65,6 +50,14 @@
};
};
&dsi_in {
remote-endpoint = <&ltdc_ep1_out>;
};
&dsi_out {
remote-endpoint = <&panel_in>;
};
&i2c1 {
touchscreen@38 {
compatible = "focaltech,ft6236";
@ -82,6 +75,9 @@
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;

7
arch/arm/dts/stm32mp157c-ed1-scmi.dts
View File

@ -60,8 +60,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

24
arch/arm/dts/stm32mp157c-ed1.dts
View File

@ -103,21 +103,23 @@
vref-supply = <&vdda>;
status = "disabled";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
/* 16.5 ck_cycles sampling time */
st,min-sample-time-nsecs = <400>;
status = "okay";
channel@0 {
reg = <0>;
/* 16.5 ck_cycles sampling time */
st,min-sample-time-ns = <400>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <400>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <400>;
};
};
};
&cpu0{
cpu-supply = <&vddcore>;
};
&cpu1{
cpu-supply = <&vddcore>;
};
&crc1 {
status = "okay";
};

7
arch/arm/dts/stm32mp157c-ev1-scmi.dts
View File

@ -66,8 +66,11 @@
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&mlahb {
resets = <&scmi_reset RST_SCMI_MCU>;
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&rcc {

34
arch/arm/dts/stm32mp157c-ev1.dts
View File

@ -100,26 +100,11 @@
};
&dsi {
phy-dsi-supply = <&reg18>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ports {
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ltdc_ep0_out>;
};
};
port@1 {
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&dsi_panel_in>;
};
};
};
panel-dsi@0 {
panel@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
@ -135,6 +120,14 @@
};
};
&dsi_in {
remote-endpoint = <&ltdc_ep0_out>;
};
&dsi_out {
remote-endpoint = <&dsi_panel_in>;
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
@ -185,7 +178,9 @@
reg = <0x3c>;
clocks = <&clk_ext_camera>;
clock-names = "xclk";
AVDD-supply = <&v2v8>;
DOVDD-supply = <&v2v8>;
DVDD-supply = <&v2v8>;
powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
rotation = <180>;
@ -239,8 +234,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};

42
arch/arm/dts/stm32mp15xx-dkx.dtsi
View File

@ -93,28 +93,39 @@
&adc {
pinctrl-names = "default";
pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
pinctrl-0 = <&adc12_usb_cc_pins_a>;
vdd-supply = <&vdd>;
vdda-supply = <&vdd>;
vref-supply = <&vrefbuf>;
status = "disabled";
status = "okay";
adc1: adc@0 {
status = "okay";
/*
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
* Use arbitrary margin here (e.g. 5us).
*/
st,min-sample-time-nsecs = <5000>;
/* AIN connector, USB Type-C CC1 & CC2 */
st,adc-channels = <0 1 6 13 18 19>;
status = "okay";
channel@18 {
reg = <18>;
st,min-sample-time-ns = <5000>;
};
channel@19 {
reg = <19>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
/* AIN connector, USB Type-C CC1 & CC2 */
st,adc-channels = <0 1 2 6 18 19>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
/* USB Type-C CC1 & CC2 */
channel@18 {
reg = <18>;
st,min-sample-time-ns = <5000>;
};
channel@19 {
reg = <19>;
st,min-sample-time-ns = <5000>;
};
};
};
@ -133,14 +144,6 @@
status = "okay";
};
&cpu0{
cpu-supply = <&vddcore>;
};
&cpu1{
cpu-supply = <&vddcore>;
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_a>;
@ -443,7 +446,7 @@
i2s2_port: port {
i2s2_endpoint: endpoint {
remote-endpoint = <&sii9022_tx_endpoint>;
format = "i2s";
dai-format = "i2s";
mclk-fs = <256>;
};
};
@ -465,8 +468,7 @@
status = "okay";
port {
ltdc_ep0_out: endpoint@0 {
reg = <0>;
ltdc_ep0_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};

5
board/dhelectronics/dh_stm32mp1/board.c
View File

@ -230,8 +230,9 @@ static void board_get_coding_straps(void)
gpio_free_list_nodev(gpio, ret);
printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
somcode, ddr3code, brdcode);
if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
somcode, ddr3code, brdcode);
}
int board_stm32mp1_ddr_config_name_match(struct udevice *dev,

1
board/st/common/Makefile
View File

@ -8,6 +8,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
ifeq ($(CONFIG_ARCH_STM32MP),y)
obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o
obj-$(CONFIG_$(SPL_)DFU_VIRT) += stm32mp_dfu_virt.o
endif
obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o

102
board/st/common/stm32mp_dfu.c
View File

@ -148,108 +148,14 @@ void set_dfu_alt_info(char *interface, char *devstr)
board_get_alt_info_mtd(mtd, buf);
}
if (IS_ENABLED(CONFIG_DFU_VIRT) &&
IS_ENABLED(CMD_STM32PROG_USB)) {
strncat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
if (IS_ENABLED(CONFIG_DFU_VIRT)) {
/* virtual device id 0 is aligned with stm32mp_dfu_virt.c */
strlcat(buf, "&virt 0=OTP", DFU_ALT_BUF_LEN);
if (IS_ENABLED(CONFIG_PMIC_STPMIC1))
strncat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
strlcat(buf, "&virt 1=PMIC", DFU_ALT_BUF_LEN);
}
env_set("dfu_alt_info", buf);
puts("DFU alt info setting: done\n");
}
#if CONFIG_IS_ENABLED(DFU_VIRT)
#include <dfu.h>
#include <power/stpmic1.h>
static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret)
return ret;
ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
if (ret >= 0) {
*size = ret;
ret = 0;
}
return 0;
}
static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
{
int ret;
#ifdef CONFIG_PMIC_STPMIC1
struct udevice *dev;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stpmic1_nvm),
&dev);
if (ret)
return ret;
ret = misc_read(dev, 0xF8 + offset, buffer, *size);
if (ret >= 0) {
*size = ret;
ret = 0;
}
if (ret == -EACCES) {
*size = 0;
ret = 0;
}
#else
log_err("PMIC update not supported");
ret = -EOPNOTSUPP;
#endif
return ret;
}
int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len)
{
switch (dfu->data.virt.dev_num) {
case 0x0:
return dfu_otp_read(offset, buf, len);
case 0x1:
return dfu_pmic_read(offset, buf, len);
}
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_read_medium_virt(dfu, offset, buf, len);
*len = 0;
return 0;
}
int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len)
{
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_write_medium_virt(dfu, offset, buf, len);
return -EOPNOTSUPP;
}
int __weak dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
{
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_get_medium_size_virt(dfu, size);
*size = SZ_1K;
return 0;
}
#endif

99
board/st/common/stm32mp_dfu_virt.c Normal file
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
#include <dfu.h>
#include <dm.h>
#include <misc.h>
#include <asm/arch/stm32prog.h>
#include <power/stpmic1.h>
static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret)
return ret;
ret = misc_read(dev, offset + STM32_BSEC_OTP_OFFSET, buffer, *size);
if (ret >= 0) {
*size = ret;
ret = 0;
}
return 0;
}
static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
{
int ret;
struct udevice *dev;
if (!IS_ENABLED(CONFIG_PMIC_STPMIC1)) {
log_err("PMIC update not supported");
return -EOPNOTSUPP;
}
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(stpmic1_nvm),
&dev);
if (ret)
return ret;
ret = misc_read(dev, 0xF8 + offset, buffer, *size);
if (ret >= 0) {
*size = ret;
ret = 0;
}
if (ret == -EACCES) {
*size = 0;
ret = 0;
}
return ret;
}
int dfu_read_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len)
{
switch (dfu->data.virt.dev_num) {
case 0x0:
return dfu_otp_read(offset, buf, len);
case 0x1:
return dfu_pmic_read(offset, buf, len);
}
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_read_medium_virt(dfu, offset, buf, len);
*len = 0;
return 0;
}
int dfu_write_medium_virt(struct dfu_entity *dfu, u64 offset,
void *buf, long *len)
{
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_write_medium_virt(dfu, offset, buf, len);
return -EOPNOTSUPP;
}
int dfu_get_medium_size_virt(struct dfu_entity *dfu, u64 *size)
{
if (IS_ENABLED(CONFIG_CMD_STM32PROG_USB) &&
dfu->data.virt.dev_num >= STM32PROG_VIRT_FIRST_DEV_NUM)
return stm32prog_get_medium_size_virt(dfu, size);
*size = SZ_1K;
return 0;
}

6
board/st/stm32f746-disco/stm32f746-disco.c
View File

@ -14,7 +14,6 @@
#include <serial.h>
#include <spl.h>
#include <splash.h>
#include <st_logo_data.h>
#include <video.h>
#include <asm/global_data.h>
#include <asm/io.h>
@ -134,10 +133,5 @@ int board_init(void)
}
#endif
#if defined(CONFIG_CMD_BMP)
bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle,
BMP_ALIGN_CENTER, BMP_ALIGN_CENTER);
#endif /* CONFIG_CMD_BMP */
return 0;
}

4
configs/stm32f746-disco_defconfig
View File

@ -56,13 +56,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_MAX_XRES=480
CONFIG_VIDEO_STM32_MAX_YRES=640
CONFIG_VIDEO_STM32_MAX_YRES=272
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

4
configs/stm32f746-disco_spl_defconfig
View File

@ -82,13 +82,13 @@ CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_SPL_TIMER=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_STM32=y
CONFIG_VIDEO_STM32_MAX_XRES=480
CONFIG_VIDEO_STM32_MAX_YRES=640
CONFIG_VIDEO_STM32_MAX_YRES=272
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

2
configs/stm32f769-disco_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
@ -64,7 +65,6 @@ CONFIG_VIDEO_STM32_MAX_XRES=480
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

2
configs/stm32f769-disco_spl_defconfig
View File

@ -82,6 +82,7 @@ CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_SPL_TIMER=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
CONFIG_BACKLIGHT_GPIO=y
CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
CONFIG_VIDEO_STM32=y
@ -90,7 +91,6 @@ CONFIG_VIDEO_STM32_MAX_XRES=480
CONFIG_VIDEO_STM32_MAX_YRES=800
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y

21
configs/stm32mp13_defconfig
View File

@ -10,6 +10,7 @@ CONFIG_DDR_CACHEABLE_SIZE=0x8000000
CONFIG_CMD_STM32KEY=y
CONFIG_TARGET_ST_STM32MP13x=y
CONFIG_ENV_OFFSET_REDUND=0x940000
CONFIG_CMD_STM32PROG=y
# CONFIG_ARMV7_NONSEC is not set
CONFIG_SYS_LOAD_ADDR=0xc2000000
CONFIG_SYS_MEMTEST_START=0xc0000000
@ -32,6 +33,8 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
@ -49,6 +52,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=-1
CONFIG_ENV_MMC_USE_DT=y
CONFIG_CLK_SCMI=y
CONFIG_SET_DFU_ALT_INFO=y
CONFIG_GPIO_HOG=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
@ -58,6 +62,8 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PINCONF=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
@ -65,6 +71,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_REGULATOR_SCMI=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y
@ -72,6 +79,20 @@ CONFIG_SYSRESET_PSCI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
# CONFIG_OPTEE_TA_AVB is not set
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_ONBOARD_HUB=y
CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=2000
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0483
CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_ERRNO_STR=y
# CONFIG_LMB_USE_MAX_REGIONS is not set
CONFIG_LMB_MEMORY_REGIONS=2

2
configs/stm32mp15_basic_defconfig
View File

@ -150,7 +150,7 @@ CONFIG_DM_REGULATOR_STM32_VREFBUF=y
CONFIG_DM_REGULATOR_STPMIC1=y
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_DM_RNG=y
CONFIG_RNG_STM32MP1=y
CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y

2
configs/stm32mp15_defconfig
View File

@ -123,7 +123,7 @@ CONFIG_DM_REGULATOR_SCMI=y
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
CONFIG_RNG_STM32MP1=y
CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y

2
configs/stm32mp15_trusted_defconfig
View File

@ -123,7 +123,7 @@ CONFIG_DM_REGULATOR_STPMIC1=y
CONFIG_REMOTEPROC_STM32_COPRO=y
CONFIG_RESET_SCMI=y
CONFIG_DM_RNG=y
CONFIG_RNG_STM32MP1=y
CONFIG_RNG_STM32=y
CONFIG_DM_RTC=y
CONFIG_RTC_STM32=y
CONFIG_SERIAL_RX_BUFFER=y

7
drivers/clk/stm32/clk-stm32mp1.c
View File

@ -72,6 +72,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define RCC_PLL2CSGR 0xA4
#define RCC_I2C46CKSELR 0xC0
#define RCC_SPI6CKSELR 0xC4
#define RCC_UART1CKSELR 0xC8
#define RCC_CPERCKSELR 0xD0
#define RCC_STGENCKSELR 0xD4
#define RCC_DDRITFCR 0xD8
@ -317,6 +318,7 @@ enum stm32mp1_parent_sel {
_SPI45_SEL,
_SPI6_SEL,
_RTC_SEL,
_UART1_SEL,
_PARENT_SEL_NB,
_UNKNOWN_SEL = 0xff,
};
@ -557,6 +559,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
@ -602,6 +605,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
static const u8 uart1_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER,
_PLL4_Q, _HSE_KER};
static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
_HSE_KER};
static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
@ -659,6 +664,7 @@ static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
(RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
rtc_parents),
STM32MP1_CLK_PARENT(_UART1_SEL, RCC_UART1CKSELR, 0, 0x7, uart1_parents),
};
#ifdef STM32MP1_CLOCK_TREE_INIT
@ -786,6 +792,7 @@ char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
[_SPI1_SEL] = "SPI1",
[_SPI45_SEL] = "SPI45",
[_RTC_SEL] = "RTC",
[_UART1_SEL] = "UART1",
};
static const struct stm32mp1_clk_data stm32mp1_data = {

3
drivers/ram/stm32mp1/stm32mp1_ram.c
View File

@ -127,7 +127,8 @@ static int stm32mp1_ddr_setup(struct udevice *dev)
dev_dbg(dev, "no st,mem-name\n");
return -EINVAL;
}
printf("RAM: %s\n", config.info.name);
if (CONFIG_IS_ENABLED(DISPLAY_PRINT))
printf("RAM: %s\n", config.info.name);
for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
ret = ofnode_read_u32_array(node, param[idx].name,

8
drivers/rng/Kconfig
View File

@ -48,11 +48,11 @@ config RNG_OPTEE
accessible to normal world but reserved and used by the OP-TEE
to avoid the weakness of a software PRNG.
config RNG_STM32MP1
bool "Enable random number generator for STM32MP1"
depends on ARCH_STM32MP
config RNG_STM32
bool "Enable random number generator for STM32"
depends on ARCH_STM32 || ARCH_STM32MP
help
Enable STM32MP1 rng driver.
Enable STM32 rng driver.
config RNG_ROCKCHIP
bool "Enable random number generator for rockchip crypto rng"

2
drivers/rng/Makefile
View File

@ -9,7 +9,7 @@ obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o
obj-$(CONFIG_RNG_MSM) += msm_rng.o
obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_STM32) += stm32_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o

408
drivers/rng/stm32_rng.c Normal file
View File

@ -0,0 +1,408 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2019, Linaro Limited
*/
#define LOG_CATEGORY UCLASS_RNG
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <reset.h>
#include <rng.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#define RNG_CR 0x00
#define RNG_CR_RNGEN BIT(2)
#define RNG_CR_CED BIT(5)
#define RNG_CR_CONFIG1 GENMASK(11, 8)
#define RNG_CR_NISTC BIT(12)
#define RNG_CR_CONFIG2 GENMASK(15, 13)
#define RNG_CR_CLKDIV_SHIFT 16
#define RNG_CR_CLKDIV GENMASK(19, 16)
#define RNG_CR_CONFIG3 GENMASK(25, 20)
#define RNG_CR_CONDRST BIT(30)
#define RNG_CR_ENTROPY_SRC_MASK (RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3)
#define RNG_CR_CONFIG_MASK (RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED | RNG_CR_CLKDIV)
#define RNG_SR 0x04
#define RNG_SR_SEIS BIT(6)
#define RNG_SR_CEIS BIT(5)
#define RNG_SR_SECS BIT(2)
#define RNG_SR_DRDY BIT(0)
#define RNG_DR 0x08
#define RNG_NSCR 0x0C
#define RNG_NSCR_MASK GENMASK(17, 0)
#define RNG_HTCR 0x10
#define RNG_NB_RECOVER_TRIES 3
/*
* struct stm32_rng_data - RNG compat data
*
* @max_clock_rate: Max RNG clock frequency, in Hertz
* @cr: Entropy source configuration
* @nscr: Noice sources control configuration
* @htcr: Health tests configuration
* @has_cond_reset: True if conditionnal reset is supported
*
*/
struct stm32_rng_data {
uint max_clock_rate;
u32 cr;
u32 nscr;
u32 htcr;
bool has_cond_reset;
};
struct stm32_rng_plat {
fdt_addr_t base;
struct clk clk;
struct reset_ctl rst;
const struct stm32_rng_data *data;
bool ced;
};
/*
* Extracts from the STM32 RNG specification when RNG supports CONDRST.
*
* When a noise source (or seed) error occurs, the RNG stops generating
* random numbers and sets to “1” both SEIS and SECS bits to indicate
* that a seed error occurred. (...)
*
* 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield
* description for details). This step is needed only if SECS is set.
* Indeed, when SEIS is set and SECS is cleared it means RNG performed
* the reset automatically (auto-reset).
* 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST
* to be cleared in the RNG_CR register, then confirm that SEIS is
* cleared in the RNG_SR register. Otherwise just clear SEIS bit in
* the RNG_SR register.
* 3. If SECS was set in step 1 (no auto-reset) wait for SECS to be
* cleared by RNG. The random number generation is now back to normal.
*/
static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_plat *pdata)
{
u32 sr = readl_relaxed(pdata->base + RNG_SR);
u32 cr = readl_relaxed(pdata->base + RNG_CR);
int err;
if (sr & RNG_SR_SECS) {
/* Conceal by resetting the subsystem (step 1.) */
writel_relaxed(cr | RNG_CR_CONDRST, pdata->base + RNG_CR);
writel_relaxed(cr & ~RNG_CR_CONDRST, pdata->base + RNG_CR);
} else {
/* RNG auto-reset (step 2.) */
writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
return 0;
}
err = readl_relaxed_poll_timeout(pdata->base + RNG_SR, sr, !(sr & RNG_CR_CONDRST), 100000);
if (err) {
log_err("%s: timeout %x\n", __func__, sr);
return err;
}
/* Check SEIS is cleared (step 2.) */
if (readl_relaxed(pdata->base + RNG_SR) & RNG_SR_SEIS)
return -EINVAL;
err = readl_relaxed_poll_timeout(pdata->base + RNG_SR, sr, !(sr & RNG_SR_SECS), 100000);
if (err) {
log_err("%s: timeout %x\n", __func__, sr);
return err;
}
return 0;
}
/*
* Extracts from the STM32 RNG specification, when CONDRST is not supported
*
* When a noise source (or seed) error occurs, the RNG stops generating
* random numbers and sets to “1” both SEIS and SECS bits to indicate
* that a seed error occurred. (...)
*
* The following sequence shall be used to fully recover from a seed
* error after the RNG initialization:
* 1. Clear the SEIS bit by writing it to “0”.
* 2. Read out 12 words from the RNG_DR register, and discard each of
* them in order to clean the pipeline.
* 3. Confirm that SEIS is still cleared. Random number generation is
* back to normal.
*/
static int stm32_rng_conceal_seed_error_sw_reset(struct stm32_rng_plat *pdata)
{
uint i = 0;
u32 sr = readl_relaxed(pdata->base + RNG_SR);
writel_relaxed(sr & ~RNG_SR_SEIS, pdata->base + RNG_SR);
for (i = 12; i != 0; i--)
(void)readl_relaxed(pdata->base + RNG_DR);
if (readl_relaxed(pdata->base + RNG_SR) & RNG_SR_SEIS)
return -EINVAL;
return 0;
}
static int stm32_rng_conceal_seed_error(struct stm32_rng_plat *pdata)
{
log_debug("Concealing RNG seed error\n");
if (pdata->data->has_cond_reset)
return stm32_rng_conceal_seed_error_cond_reset(pdata);
else
return stm32_rng_conceal_seed_error_sw_reset(pdata);
};
static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
{
int retval;
u32 sr, reg;
size_t increment;
struct stm32_rng_plat *pdata = dev_get_plat(dev);
uint tries = 0;
while (len > 0) {
retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
sr, 10000);
if (retval) {
log_err("%s: Timeout RNG no data", __func__);
return retval;
}
if (sr != RNG_SR_DRDY) {
if (sr & RNG_SR_SEIS) {
retval = stm32_rng_conceal_seed_error(pdata);
tries++;
if (retval || tries > RNG_NB_RECOVER_TRIES) {
log_err("%s: Couldn't recover from seed error", __func__);
return -ENOTRECOVERABLE;
}
/* Start again */
continue;
}
if (sr & RNG_SR_CEIS) {
log_info("RNG clock too slow");
writel_relaxed(0, pdata->base + RNG_SR);
}
}
/*
* Once the DRDY bit is set, the RNG_DR register can
* be read up to four consecutive times.
*/
reg = readl(pdata->base + RNG_DR);
/* Late seed error case: DR being 0 is an error status */
if (!reg) {
retval = stm32_rng_conceal_seed_error(pdata);
tries++;
if (retval || tries > RNG_NB_RECOVER_TRIES) {
log_err("%s: Couldn't recover from seed error", __func__);
return -ENOTRECOVERABLE;
}
/* Start again */
continue;
}
increment = min(len, sizeof(u32));
memcpy(data, &reg, increment);
data += increment;
len -= increment;
tries = 0;
}
return 0;
}
static uint stm32_rng_clock_freq_restrain(struct stm32_rng_plat *pdata)
{
ulong clock_rate = 0;
uint clock_div = 0;
clock_rate = clk_get_rate(&pdata->clk);
/*
* Get the exponent to apply on the CLKDIV field in RNG_CR register.
* No need to handle the case when clock-div > 0xF as it is physically
* impossible.
*/
while ((clock_rate >> clock_div) > pdata->data->max_clock_rate)
clock_div++;
log_debug("RNG clk rate : %lu\n", clk_get_rate(&pdata->clk) >> clock_div);
return clock_div;
}
static int stm32_rng_init(struct stm32_rng_plat *pdata)
{
int err;
u32 cr, sr;
err = clk_enable(&pdata->clk);
if (err)
return err;
cr = readl(pdata->base + RNG_CR);
/*
* Keep default RNG configuration if none was specified, that is when conf.cr is set to 0.
*/
if (pdata->data->has_cond_reset && pdata->data->cr) {
uint clock_div = stm32_rng_clock_freq_restrain(pdata);
cr &= ~RNG_CR_CONFIG_MASK;
cr |= RNG_CR_CONDRST | (pdata->data->cr & RNG_CR_ENTROPY_SRC_MASK) |
(clock_div << RNG_CR_CLKDIV_SHIFT);
if (pdata->ced)
cr &= ~RNG_CR_CED;
else
cr |= RNG_CR_CED;
writel(cr, pdata->base + RNG_CR);
/* Health tests and noise control registers */
writel_relaxed(pdata->data->htcr, pdata->base + RNG_HTCR);
writel_relaxed(pdata->data->nscr & RNG_NSCR_MASK, pdata->base + RNG_NSCR);
cr &= ~RNG_CR_CONDRST;
cr |= RNG_CR_RNGEN;
writel(cr, pdata->base + RNG_CR);
err = readl_poll_timeout(pdata->base + RNG_CR, cr,
(!(cr & RNG_CR_CONDRST)), 10000);
if (err) {
log_err("%s: Timeout!", __func__);
return err;
}
} else {
if (pdata->data->has_cond_reset)
cr |= RNG_CR_CONDRST;
if (pdata->ced)
cr &= ~RNG_CR_CED;
else
cr |= RNG_CR_CED;
writel(cr, pdata->base + RNG_CR);
if (pdata->data->has_cond_reset)
cr &= ~RNG_CR_CONDRST;
cr |= RNG_CR_RNGEN;
writel(cr, pdata->base + RNG_CR);
}
/* clear error indicators */
writel(0, pdata->base + RNG_SR);
err = readl_poll_timeout(pdata->base + RNG_SR, sr,
sr & RNG_SR_DRDY, 10000);
if (err)
log_err("%s: Timeout!", __func__);
return err;
}
static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
{
writel(0, pdata->base + RNG_CR);
return clk_disable(&pdata->clk);
}
static int stm32_rng_probe(struct udevice *dev)
{
struct stm32_rng_plat *pdata = dev_get_plat(dev);
pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
reset_assert(&pdata->rst);
udelay(20);
reset_deassert(&pdata->rst);
return stm32_rng_init(pdata);
}
static int stm32_rng_remove(struct udevice *dev)
{
struct stm32_rng_plat *pdata = dev_get_plat(dev);
return stm32_rng_cleanup(pdata);
}
static int stm32_rng_of_to_plat(struct udevice *dev)
{
struct stm32_rng_plat *pdata = dev_get_plat(dev);
int err;
pdata->base = dev_read_addr(dev);
if (!pdata->base)
return -ENOMEM;
err = clk_get_by_index(dev, 0, &pdata->clk);
if (err)
return err;
err = reset_get_by_index(dev, 0, &pdata->rst);
if (err)
return err;
pdata->ced = dev_read_bool(dev, "clock-error-detect");
return 0;
}
static const struct dm_rng_ops stm32_rng_ops = {
.read = stm32_rng_read,
};
static const struct stm32_rng_data stm32mp13_rng_data = {
.has_cond_reset = true,
.max_clock_rate = 48000000,
.htcr = 0x969D,
.nscr = 0x2B5BB,
.cr = 0xF00D00,
};
static const struct stm32_rng_data stm32_rng_data = {
.has_cond_reset = false,
.max_clock_rate = 3000000,
/* Not supported */
.htcr = 0,
.nscr = 0,
.cr = 0,
};
static const struct udevice_id stm32_rng_match[] = {
{.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
{.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
{},
};
U_BOOT_DRIVER(stm32_rng) = {
.name = "stm32-rng",
.id = UCLASS_RNG,
.of_match = stm32_rng_match,
.ops = &stm32_rng_ops,
.probe = stm32_rng_probe,
.remove = stm32_rng_remove,
.plat_auto = sizeof(struct stm32_rng_plat),
.of_to_plat = stm32_rng_of_to_plat,
};

198
drivers/rng/stm32mp1_rng.c
View File

@ -1,198 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2019, Linaro Limited
*/
#define LOG_CATEGORY UCLASS_RNG
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <reset.h>
#include <rng.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#define RNG_CR 0x00
#define RNG_CR_RNGEN BIT(2)
#define RNG_CR_CED BIT(5)
#define RNG_CR_CONDRST BIT(30)
#define RNG_SR 0x04
#define RNG_SR_SEIS BIT(6)
#define RNG_SR_CEIS BIT(5)
#define RNG_SR_SECS BIT(2)
#define RNG_SR_DRDY BIT(0)
#define RNG_DR 0x08
struct stm32_rng_data {
bool has_cond_reset;
};
struct stm32_rng_plat {
fdt_addr_t base;
struct clk clk;
struct reset_ctl rst;
const struct stm32_rng_data *data;
};
static int stm32_rng_read(struct udevice *dev, void *data, size_t len)
{
int retval, i;
u32 sr, count, reg;
size_t increment;
struct stm32_rng_plat *pdata = dev_get_plat(dev);
while (len > 0) {
retval = readl_poll_timeout(pdata->base + RNG_SR, sr,
sr & RNG_SR_DRDY, 10000);
if (retval)
return retval;
if (sr & (RNG_SR_SEIS | RNG_SR_SECS)) {
/* As per SoC TRM */
clrbits_le32(pdata->base + RNG_SR, RNG_SR_SEIS);
for (i = 0; i < 12; i++)
readl(pdata->base + RNG_DR);
if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) {
log_err("RNG Noise");
return -EIO;
}
/* start again */
continue;
}
/*
* Once the DRDY bit is set, the RNG_DR register can
* be read four consecutive times.
*/
count = 4;
while (len && count) {
reg = readl(pdata->base + RNG_DR);
memcpy(data, &reg, min(len, sizeof(u32)));
increment = min(len, sizeof(u32));
data += increment;
len -= increment;
count--;
}
}
return 0;
}
static int stm32_rng_init(struct stm32_rng_plat *pdata)
{
int err;
u32 cr, sr;
err = clk_enable(&pdata->clk);
if (err)
return err;
cr = readl(pdata->base + RNG_CR);
/* Disable CED */
cr |= RNG_CR_CED;
if (pdata->data->has_cond_reset) {
cr |= RNG_CR_CONDRST;
writel(cr, pdata->base + RNG_CR);
cr &= ~RNG_CR_CONDRST;
writel(cr, pdata->base + RNG_CR);
err = readl_poll_timeout(pdata->base + RNG_CR, cr,
(!(cr & RNG_CR_CONDRST)), 10000);
if (err)
return err;
}
/* clear error indicators */
writel(0, pdata->base + RNG_SR);
cr |= RNG_CR_RNGEN;
writel(cr, pdata->base + RNG_CR);
err = readl_poll_timeout(pdata->base + RNG_SR, sr,
sr & RNG_SR_DRDY, 10000);
return err;
}
static int stm32_rng_cleanup(struct stm32_rng_plat *pdata)
{
writel(0, pdata->base + RNG_CR);
return clk_disable(&pdata->clk);
}
static int stm32_rng_probe(struct udevice *dev)
{
struct stm32_rng_plat *pdata = dev_get_plat(dev);
pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev);
reset_assert(&pdata->rst);
udelay(20);
reset_deassert(&pdata->rst);
return stm32_rng_init(pdata);
}
static int stm32_rng_remove(struct udevice *dev)
{
struct stm32_rng_plat *pdata = dev_get_plat(dev);
return stm32_rng_cleanup(pdata);
}
static int stm32_rng_of_to_plat(struct udevice *dev)
{
struct stm32_rng_plat *pdata = dev_get_plat(dev);
int err;
pdata->base = dev_read_addr(dev);
if (!pdata->base)
return -ENOMEM;
err = clk_get_by_index(dev, 0, &pdata->clk);
if (err)
return err;
err = reset_get_by_index(dev, 0, &pdata->rst);
if (err)
return err;
return 0;
}
static const struct dm_rng_ops stm32_rng_ops = {
.read = stm32_rng_read,
};
static const struct stm32_rng_data stm32mp13_rng_data = {
.has_cond_reset = true,
};
static const struct stm32_rng_data stm32_rng_data = {
.has_cond_reset = false,
};
static const struct udevice_id stm32_rng_match[] = {
{.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data},
{.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data},
{},
};
U_BOOT_DRIVER(stm32_rng) = {
.name = "stm32-rng",
.id = UCLASS_RNG,
.of_match = stm32_rng_match,
.ops = &stm32_rng_ops,
.probe = stm32_rng_probe,
.remove = stm32_rng_remove,
.plat_auto = sizeof(struct stm32_rng_plat),
.of_to_plat = stm32_rng_of_to_plat,
};

7
include/configs/stm32f746-disco.h
View File

@ -23,6 +23,10 @@
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
#define STM32F746_BOARD_EXTRA_ENV \
"splashimage=0xC0448000\0" \
"splashpos=m,m\0"
#include <config_distro_bootcmd.h>
#define CFG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xC0008000\0" \
@ -31,7 +35,8 @@
"scriptaddr=0xC0418000\0" \
"pxefile_addr_r=0xC0428000\0" \
"ramdisk_addr_r=0xC0438000\0" \
BOOTENV
BOOTENV \
STM32F746_BOARD_EXTRA_ENV
#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \
CONFIG_SPL_PAD_TO)

13
include/configs/stm32mp13_common.h
View File

@ -35,16 +35,27 @@
#define BOOT_TARGET_MMC1(func)
#endif
#ifdef CONFIG_CMD_USB
#define BOOT_TARGET_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_USB(func)
#endif
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_MMC1(func) \
BOOT_TARGET_MMC0(func)
BOOT_TARGET_MMC0(func) \
BOOT_TARGET_USB(func)
/*
* default bootcmd for stm32mp13:
* for serial/usb: execute the stm32prog command
* for mmc boot (eMMC, SD card), distro boot on the same mmc device
*/
#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
"echo \"Boot over ${boot_device}${boot_instance}!\";" \
"if test ${boot_device} = serial || test ${boot_device} = usb;" \
"then stm32prog ${boot_device} ${boot_instance}; " \
"else " \
"run env_check;" \
"if test ${boot_device} = mmc;" \
"then env set boot_targets \"mmc${boot_instance}\"; fi;" \

25
include/configs/stm32mp15_dh_dhsom.h
View File

@ -20,7 +20,26 @@
#define STM32MP_BOARD_EXTRA_ENV \
"usb_pgood_delay=1000\0" \
"update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
"dh_update_sd_to_emmc=" /* Install U-Boot from SD to eMMC */ \
"setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
"load mmc 0:4 ${loadaddr1} boot/u-boot-spl.stm32 && " \
"setexpr sblkcnt ${filesize} + 0x1ff && " \
"setexpr sblkcnt ${sblkcnt} / 0x200 && " \
"load mmc 0:4 ${loadaddr} boot/u-boot.itb && " \
"setexpr ublkcnt ${filesize} + 0x1ff && " \
"setexpr ublkcnt ${ublkcnt} / 0x200 && " \
"mmc partconf 1 1 1 1 && mmc dev 1 1 && " \
"mmc write ${loadaddr1} 0 ${sblkcnt} && " \
"mmc dev 1 2 && " \
"mmc write ${loadaddr1} 0 ${sblkcnt} && " \
"mmc dev 1 && " \
"gpt write mmc 1 'name=ssbl,size=2MiB' && " \
"mmc write ${loadaddr} 0x22 ${ublkcnt} && " \
"mmc partconf 1 1 1 0 && " \
"setenv loadaddr1 && " \
"setenv sblkcnt && " \
"setenv ublkcnt\0" \
"dh_update_sd_to_sf=" /* Erase SPI NOR and install U-Boot from SD */ \
"setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \
"load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \
"env set filesize1 ${filesize} && " \
@ -29,7 +48,9 @@
"sf update ${loadaddr1} 0 ${filesize1} && " \
"sf update ${loadaddr1} 0x40000 ${filesize1} && " \
"sf update ${loadaddr} 0x80000 ${filesize} && " \
"env set filesize1 && env set loadaddr1\0"
"env set filesize1 && env set loadaddr1\0" \
"update_sf=run dh_update_sd_to_sf\0"
#include <configs/stm32mp15_common.h>

2
include/dt-bindings/clock/stm32mp1-clks.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

2
include/dt-bindings/clock/stm32mp13-clks.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.

1
include/dt-bindings/mfd/stm32f7-rcc.h
View File

@ -64,6 +64,7 @@
#define STM32F7_RCC_APB1_TIM14 8
#define STM32F7_RCC_APB1_LPTIM1 9
#define STM32F7_RCC_APB1_WWDG 11
#define STM32F7_RCC_APB1_CAN3 13
#define STM32F7_RCC_APB1_SPI2 14
#define STM32F7_RCC_APB1_SPI3 15
#define STM32F7_RCC_APB1_SPDIFRX 16

42
include/dt-bindings/regulator/st,stm32mp13-regulator.h Normal file
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@ -0,0 +1,42 @@
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*/
#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H
#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H
/* SCMI voltage domains identifiers */
/* SOC Internal regulators */
#define VOLTD_SCMI_REG11 0
#define VOLTD_SCMI_REG18 1
#define VOLTD_SCMI_USB33 2
#define VOLTD_SCMI_SDMMC1_IO 3
#define VOLTD_SCMI_SDMMC2_IO 4
#define VOLTD_SCMI_VREFBUF 5
/* STPMIC1 regulators */
#define VOLTD_SCMI_STPMIC1_BUCK1 6
#define VOLTD_SCMI_STPMIC1_BUCK2 7
#define VOLTD_SCMI_STPMIC1_BUCK3 8
#define VOLTD_SCMI_STPMIC1_BUCK4 9
#define VOLTD_SCMI_STPMIC1_LDO1 10
#define VOLTD_SCMI_STPMIC1_LDO2 11
#define VOLTD_SCMI_STPMIC1_LDO3 12
#define VOLTD_SCMI_STPMIC1_LDO4 13
#define VOLTD_SCMI_STPMIC1_LDO5 14
#define VOLTD_SCMI_STPMIC1_LDO6 15
#define VOLTD_SCMI_STPMIC1_VREFDDR 16
#define VOLTD_SCMI_STPMIC1_BOOST 17
#define VOLTD_SCMI_STPMIC1_PWR_SW1 18
#define VOLTD_SCMI_STPMIC1_PWR_SW2 19
/* External regulators */
#define VOLTD_SCMI_REGU0 20
#define VOLTD_SCMI_REGU1 21
#define VOLTD_SCMI_REGU2 22
#define VOLTD_SCMI_REGU3 23
#define VOLTD_SCMI_REGU4 24
#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */

2
include/dt-bindings/reset/stm32mp1-resets.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.

2
include/dt-bindings/reset/stm32mp13-resets.h
View File

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.

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