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clk: sunxi: Add support for the D1 CCU

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Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Samuel Holland 2022-04-30 22:38:37 -05:00 committed by Andre Przywara
parent ad9dcb5001
commit b9a91b98e8
4 changed files with 96 additions and 0 deletions
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6
drivers/clk/sunxi/Kconfig
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@ -87,6 +87,12 @@ config CLK_SUN8I_H3
This enables common clock driver support for platforms based
on Allwinner H3/H5 SoC.
config CLK_SUN20I_D1
bool "Clock driver for Allwinner D1"
help
This enables common clock driver support for platforms based
on Allwinner D1 SoC.
config CLK_SUN50I_H6
bool "Clock driver for Allwinner H6"
default MACH_SUN50I_H6

1
drivers/clk/sunxi/Makefile
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@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o

84
drivers/clk/sunxi/clk_d1.c Normal file
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@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <clk/sunxi.h>
#include <dt-bindings/clock/sun20i-d1-ccu.h>
#include <dt-bindings/reset/sun20i-d1-ccu.h>
#include <linux/bitops.h>
static struct ccu_clk_gate d1_gates[] = {
[CLK_APB0] = GATE_DUMMY,
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
[CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
[CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
[CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
[CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
[CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
[CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
[CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
[CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
[CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
[CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
[CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
[CLK_RISCV] = GATE(0xd04, BIT(31)),
};
static struct ccu_reset d1_resets[] = {
[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
[RST_BUS_UART0] = RESET(0x90c, BIT(16)),
[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
[RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
[RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
[RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
[RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
[RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
[RST_USB_PHY0] = RESET(0xa70, BIT(30)),
[RST_USB_PHY1] = RESET(0xa74, BIT(30)),
[RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
[RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
[RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
[RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
[RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
};
const struct ccu_desc d1_ccu_desc = {
.gates = d1_gates,
.resets = d1_resets,
.num_gates = ARRAY_SIZE(d1_gates),
.num_resets = ARRAY_SIZE(d1_resets),
};

5
drivers/clk/sunxi/clk_sunxi.c
View File

@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_desc;
extern const struct ccu_desc a80_ccu_desc;
extern const struct ccu_desc a80_mmc_clk_desc;
extern const struct ccu_desc a83t_ccu_desc;
extern const struct ccu_desc d1_ccu_desc;
extern const struct ccu_desc f1c100s_ccu_desc;
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
@ -195,6 +196,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
{ .compatible = "allwinner,sun50i-h5-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN20I_D1
{ .compatible = "allwinner,sun20i-d1-ccu",
.data = (ulong)&d1_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6
{ .compatible = "allwinner,sun50i-h6-ccu",
.data = (ulong)&h6_ccu_desc },