net: am65-cpsw: cpsw_mdio: Switch to proper DM_MDIO framework
Add a new Kconfig symbol MDIO_TI_CPSW for the CPSW MDIO driver and build it with proper DM support if enabled. If MDIO_TI_CPSW is not enabled then we continue to behave like before. Clean up MDIO custom handling in am65-cpsw and use dm_eth_phy_connect() to get the PHY. Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
This commit is contained in:
Roger Quadros
Tom Rini
parent
a0e02c6619
commit
be2eb3ad8f
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@ -45,7 +45,15 @@ config TI_AM65_CPSW_NUSS
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imply MISC_INIT_R
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imply MISC
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imply SYSCON
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imply MDIO_TI_CPSW
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select PHYLIB
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help
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This driver supports TI K3 MCU CPSW Nuss Ethernet controller
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in Texas Instruments K3 AM65x SoCs.
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config MDIO_TI_CPSW
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bool "TI CPSW MDIO interface support"
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depends on DM_MDIO
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help
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This driver supports the TI CPSW MDIO interface found in various
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TI SoCs.
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@ -5,4 +5,5 @@
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obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o cpsw_mdio.o
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obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
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obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o cpsw_mdio.o
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obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o cpsw_mdio.o
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obj-$(CONFIG_TI_AM65_CPSW_NUSS) += am65-cpsw-nuss.o
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obj-$(CONFIG_MDIO_TI_CPSW) += cpsw_mdio.o
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@ -31,8 +31,6 @@
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#include <linux/printk.h>
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#include <linux/soc/ti/ti-udma.h>
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#include "cpsw_mdio.h"
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#define AM65_CPSW_CPSWNU_MAX_PORTS 9
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#define AM65_CPSW_SS_BASE 0x0
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@ -113,7 +111,6 @@ struct am65_cpsw_common {
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struct udevice *dev;
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fdt_addr_t ss_base;
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fdt_addr_t cpsw_base;
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fdt_addr_t mdio_base;
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fdt_addr_t ale_base;
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struct clk fclk;
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@ -122,13 +119,8 @@ struct am65_cpsw_common {
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u32 port_num;
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struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS];
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struct mii_dev *bus;
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u32 bus_freq;
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struct gpio_desc mdio_gpio_reset;
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u32 reset_delay_us;
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u32 reset_post_delay_us;
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struct dma dma_tx;
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struct dma dma_rx;
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u32 rx_next;
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@ -140,13 +132,7 @@ struct am65_cpsw_priv {
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struct udevice *dev;
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struct am65_cpsw_common *cpsw_common;
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u32 port_id;
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struct phy_device *phydev;
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bool has_phy;
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ofnode phy_node;
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u32 phy_addr;
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bool mdio_manual_mode;
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};
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#ifdef PKTSIZE_ALIGN
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@ -622,111 +608,15 @@ static const struct eth_ops am65_cpsw_ops = {
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.read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
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};
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static const struct soc_attr k3_mdio_soc_data[] = {
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{ .family = "AM62X", .revision = "SR1.0" },
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{ .family = "AM64X", .revision = "SR1.0" },
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{ .family = "AM64X", .revision = "SR2.0" },
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{ .family = "AM65X", .revision = "SR1.0" },
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{ .family = "AM65X", .revision = "SR2.0" },
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{ .family = "J7200", .revision = "SR1.0" },
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{ .family = "J7200", .revision = "SR2.0" },
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{ .family = "J721E", .revision = "SR1.0" },
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{ .family = "J721E", .revision = "SR1.1" },
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{ .family = "J721S2", .revision = "SR1.0" },
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{ /* sentinel */ },
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};
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static ofnode am65_cpsw_find_mdio(ofnode parent)
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{
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ofnode node;
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ofnode_for_each_subnode(node, parent)
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if (ofnode_device_is_compatible(node, "ti,cpsw-mdio"))
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return node;
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return ofnode_null();
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}
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static int am65_cpsw_mdio_setup(struct udevice *dev)
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{
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struct am65_cpsw_priv *priv = dev_get_priv(dev);
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struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
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struct udevice *mdio_dev;
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ofnode mdio;
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int ret;
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mdio = am65_cpsw_find_mdio(dev_ofnode(cpsw_common->dev));
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if (!ofnode_valid(mdio))
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return 0;
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/*
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* The MDIO controller is represented in the DT binding by a
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* subnode of the MAC controller.
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*
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* We don't have a DM driver for the MDIO device yet, and thus any
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* pinctrl setting on its node will be ignored.
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*
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* However, we do need to make sure the pins states tied to the
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* MDIO node are configured properly. Fortunately, the core DM
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* does that for use when we get a device, so we can work around
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* that whole issue by just requesting a dummy MDIO driver to
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* probe, and our pins will get muxed.
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*/
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ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdio_dev);
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if (ret)
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return ret;
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return 0;
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}
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static int am65_cpsw_mdio_init(struct udevice *dev)
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{
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struct am65_cpsw_priv *priv = dev_get_priv(dev);
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struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
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int ret;
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if (!priv->has_phy || cpsw_common->bus)
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return 0;
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if (IS_ENABLED(CONFIG_DM_GPIO)) {
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if (dm_gpio_is_valid(&cpsw_common->mdio_gpio_reset)) {
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dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 1);
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udelay(cpsw_common->reset_delay_us);
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dm_gpio_set_value(&cpsw_common->mdio_gpio_reset, 0);
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if (cpsw_common->reset_post_delay_us > 0)
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udelay(cpsw_common->reset_post_delay_us);
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}
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}
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ret = am65_cpsw_mdio_setup(dev);
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if (ret)
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return ret;
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cpsw_common->bus = cpsw_mdio_init(dev->name,
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cpsw_common->mdio_base,
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cpsw_common->bus_freq,
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clk_get_rate(&cpsw_common->fclk),
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priv->mdio_manual_mode);
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if (!cpsw_common->bus)
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return -EFAULT;
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return 0;
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}
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static int am65_cpsw_phy_init(struct udevice *dev)
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{
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struct am65_cpsw_priv *priv = dev_get_priv(dev);
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struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct phy_device *phydev;
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u32 supported = PHY_GBIT_FEATURES;
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int ret;
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phydev = phy_connect(cpsw_common->bus,
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priv->phy_addr,
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priv->dev,
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pdata->phy_interface);
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phydev = dm_eth_phy_connect(dev);
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if (!phydev) {
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dev_err(dev, "phy_connect() failed\n");
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return -ENODEV;
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@ -740,13 +630,10 @@ static int am65_cpsw_phy_init(struct udevice *dev)
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}
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phydev->advertising = phydev->supported;
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if (ofnode_valid(priv->phy_node))
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phydev->node = priv->phy_node;
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priv->phydev = phydev;
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ret = phy_config(phydev);
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if (ret < 0)
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pr_err("phy_config() failed: %d", ret);
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dev_err(dev, "phy_config() failed: %d", ret);
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return ret;
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}
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@ -755,8 +642,6 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct am65_cpsw_priv *priv = dev_get_priv(dev);
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struct ofnode_phandle_args out_args;
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int ret = 0;
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dev_read_u32(dev, "reg", &priv->port_id);
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@ -771,28 +656,7 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
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dev_err(dev, "Port %u speed froced to %uMbit\n",
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priv->port_id, pdata->max_speed);
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priv->has_phy = true;
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ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
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NULL, 0, 0, &out_args);
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if (ret) {
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dev_err(dev, "can't parse phy-handle port %u (%d)\n",
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priv->port_id, ret);
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priv->has_phy = false;
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ret = 0;
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}
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priv->phy_node = out_args.node;
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if (priv->has_phy) {
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ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
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if (ret) {
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dev_err(dev, "failed to get phy_addr port %u (%d)\n",
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priv->port_id, ret);
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goto out;
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}
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}
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out:
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return ret;
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return 0;
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}
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static int am65_cpsw_port_probe(struct udevice *dev)
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@ -811,10 +675,6 @@ static int am65_cpsw_port_probe(struct udevice *dev)
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sprintf(portname, "%s%s", dev->parent->name, dev->name);
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device_set_name(dev, portname);
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priv->mdio_manual_mode = false;
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if (soc_device_match(k3_mdio_soc_data))
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priv->mdio_manual_mode = true;
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ret = am65_cpsw_ofdata_parse_phy(dev);
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if (ret)
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goto out;
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@ -823,13 +683,8 @@ static int am65_cpsw_port_probe(struct udevice *dev)
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if (ret)
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goto out;
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ret = am65_cpsw_mdio_init(dev);
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if (ret)
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goto out;
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ret = am65_cpsw_phy_init(dev);
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if (ret)
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goto out;
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out:
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return ret;
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}
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@ -837,7 +692,7 @@ out:
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static int am65_cpsw_probe_nuss(struct udevice *dev)
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{
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struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
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ofnode ports_np, node, mdio_np;
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ofnode ports_np, node;
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int ret, i;
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struct udevice *port_dev;
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@ -862,25 +717,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
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cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
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cpsw_common->ale_base = cpsw_common->cpsw_base +
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AM65_CPSW_CPSW_NU_ALE_BASE;
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cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
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if (IS_ENABLED(CONFIG_DM_GPIO)) {
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/* get bus level PHY reset GPIO details */
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mdio_np = dev_read_subnode(dev, "mdio");
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if (!ofnode_valid(mdio_np)) {
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ret = -ENOENT;
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goto out;
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}
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cpsw_common->reset_delay_us = ofnode_read_u32_default(mdio_np, "reset-delay-us",
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DEFAULT_GPIO_RESET_DELAY);
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cpsw_common->reset_post_delay_us = ofnode_read_u32_default(mdio_np,
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"reset-post-delay-us",
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0);
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ret = gpio_request_by_name_nodev(mdio_np, "reset-gpios", 0,
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&cpsw_common->mdio_gpio_reset,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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}
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ports_np = dev_read_subnode(dev, "ethernet-ports");
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if (!ofnode_valid(ports_np)) {
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@ -940,12 +776,11 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
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dev_read_u32_default(dev, "bus_freq",
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AM65_CPSW_MDIO_BUS_FREQ_DEF);
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dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u mdio_freq:%u\n",
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dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
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readl(cpsw_common->ss_base),
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readl(cpsw_common->cpsw_base),
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readl(cpsw_common->ale_base),
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cpsw_common->port_num,
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cpsw_common->bus_freq);
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cpsw_common->port_num);
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out:
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power_domain_free(&cpsw_common->pwrdmn);
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@ -976,14 +811,3 @@ U_BOOT_DRIVER(am65_cpsw_nuss_port) = {
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.plat_auto = sizeof(struct eth_pdata),
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.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
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};
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static const struct udevice_id am65_cpsw_mdio_ids[] = {
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{ .compatible = "ti,cpsw-mdio" },
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{ }
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};
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U_BOOT_DRIVER(am65_cpsw_mdio) = {
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.name = "am65_cpsw_mdio",
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.id = UCLASS_MDIO,
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.of_match = am65_cpsw_mdio_ids,
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};
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@ -5,11 +5,15 @@
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm/device_compat.h>
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#include <log.h>
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#include <malloc.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <soc.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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@ -22,6 +26,7 @@ struct cpsw_mdio_regs {
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#define CONTROL_FAULT BIT(19)
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#define CONTROL_FAULT_ENABLE BIT(18)
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#define CONTROL_DIV_MASK GENMASK(15, 0)
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#define CONTROL_MAX_DIV CONTROL_DIV_MASK
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#define MDIO_MAN_MDCLK_O BIT(2)
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#define MDIO_MAN_OE BIT(1)
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@ -72,6 +77,8 @@ struct cpsw_mdio_regs {
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*/
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#define CPSW_MDIO_TIMEOUT 100 /* msecs */
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#define CPSW_MDIO_DEF_BUS_FREQ 2200000 /* 2.2 MHz */
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enum cpsw_mdio_manual {
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MDIO_PIN = 0,
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MDIO_OE,
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@ -82,8 +89,35 @@ struct cpsw_mdio {
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struct cpsw_mdio_regs *regs;
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struct mii_dev *bus;
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int div;
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bool manual_mode;
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struct clk clk;
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unsigned long bus_freq;
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};
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static int cpsw_mdio_enable(struct cpsw_mdio *data)
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{
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int ret;
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/* set enable and clock divider */
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writel(data->div | CONTROL_ENABLE, &data->regs->control);
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ret = wait_for_bit_le32(&data->regs->control,
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CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true);
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if (ret)
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return ret;
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/*
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* wait for scan logic to settle:
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* the scan time consists of (a) a large fixed component, and (b) a
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* small component that varies with the mii bus frequency. These
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* were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
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* silicon. Since the effect of (b) was found to be largely
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* negligible, we keep things simple here.
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*/
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mdelay(1);
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return 0;
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}
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static void cpsw_mdio_disable(struct cpsw_mdio *mdio)
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{
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u32 reg;
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@ -206,10 +240,16 @@ static void cpsw_mdio_sw_preamble(struct cpsw_mdio *mdio)
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}
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}
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#if defined(CONFIG_DM_MDIO)
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#define MII_TO_CPSW_MDIO(bus) (dev_get_priv((struct udevice *)(bus)->priv))
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#else
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#define MII_TO_CPSW_MDIO(bus) ((bus)->priv)
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#endif
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static int cpsw_mdio_sw_read(struct mii_dev *bus, int phy_id,
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int dev_addr, int phy_reg)
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{
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struct cpsw_mdio *mdio = bus->priv;
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struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
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u32 reg, i;
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u8 ack;
|
||||
|
||||
|
|
@ -266,7 +306,7 @@ static int cpsw_mdio_sw_read(struct mii_dev *bus, int phy_id,
|
|||
static int cpsw_mdio_sw_write(struct mii_dev *bus, int phy_id,
|
||||
int dev_addr, int phy_reg, u16 phy_data)
|
||||
{
|
||||
struct cpsw_mdio *mdio = bus->priv;
|
||||
struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
|
||||
|
||||
if ((phy_reg & ~PHY_REG_MASK) || (phy_id & ~PHY_ID_MASK))
|
||||
return -EINVAL;
|
||||
|
|
@ -316,7 +356,7 @@ static int cpsw_mdio_wait_for_user_access(struct cpsw_mdio *mdio)
|
|||
static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
|
||||
int dev_addr, int phy_reg)
|
||||
{
|
||||
struct cpsw_mdio *mdio = bus->priv;
|
||||
struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
|
||||
int data, ret;
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -342,7 +382,7 @@ static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
|
|||
static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
|
||||
int phy_reg, u16 data)
|
||||
{
|
||||
struct cpsw_mdio *mdio = bus->priv;
|
||||
struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
||||
|
|
@ -361,9 +401,10 @@ static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
|
|||
return cpsw_mdio_wait_for_user_access(mdio);
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_MDIO_TI_CPSW)
|
||||
u32 cpsw_mdio_get_alive(struct mii_dev *bus)
|
||||
{
|
||||
struct cpsw_mdio *mdio = bus->priv;
|
||||
struct cpsw_mdio *mdio = MII_TO_CPSW_MDIO(bus);
|
||||
u32 val;
|
||||
|
||||
val = readl(&mdio->regs->alive);
|
||||
|
|
@ -396,22 +437,11 @@ struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
|
|||
else
|
||||
cpsw_mdio->div = (fck_freq / bus_freq) - 1;
|
||||
cpsw_mdio->div &= CONTROL_DIV_MASK;
|
||||
|
||||
/* set enable and clock divider */
|
||||
writel(cpsw_mdio->div | CONTROL_ENABLE | CONTROL_FAULT |
|
||||
CONTROL_FAULT_ENABLE, &cpsw_mdio->regs->control);
|
||||
wait_for_bit_le32(&cpsw_mdio->regs->control,
|
||||
CONTROL_IDLE, false, CPSW_MDIO_TIMEOUT, true);
|
||||
|
||||
/*
|
||||
* wait for scan logic to settle:
|
||||
* the scan time consists of (a) a large fixed component, and (b) a
|
||||
* small component that varies with the mii bus frequency. These
|
||||
* were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
|
||||
* silicon. Since the effect of (b) was found to be largely
|
||||
* negligible, we keep things simple here.
|
||||
*/
|
||||
mdelay(1);
|
||||
ret = cpsw_mdio_enable(cpsw_mdio);
|
||||
if (ret) {
|
||||
debug("mdio_enable failed: %d\n", ret);
|
||||
goto free_bus;
|
||||
}
|
||||
|
||||
if (manual_mode) {
|
||||
cpsw_mdio->bus->read = cpsw_mdio_sw_read;
|
||||
|
|
@ -452,3 +482,129 @@ void cpsw_mdio_free(struct mii_dev *bus)
|
|||
mdio_free(bus);
|
||||
free(mdio);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static int cpsw_mdio_init_clk(struct cpsw_mdio *data)
|
||||
{
|
||||
u32 mdio_in, div;
|
||||
|
||||
mdio_in = clk_get_rate(&data->clk);
|
||||
div = (mdio_in / data->bus_freq) - 1;
|
||||
if (div > CONTROL_MAX_DIV)
|
||||
div = CONTROL_MAX_DIV;
|
||||
|
||||
data->div = div;
|
||||
return cpsw_mdio_enable(data);
|
||||
}
|
||||
|
||||
static int cpsw_mdio_bus_read(struct udevice *dev, int addr,
|
||||
int devad, int reg)
|
||||
{
|
||||
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
||||
NULL;
|
||||
struct cpsw_mdio *priv = dev_get_priv(dev);
|
||||
|
||||
if (pdata && pdata->mii_bus) {
|
||||
if (priv->manual_mode)
|
||||
return cpsw_mdio_sw_read(pdata->mii_bus, addr, devad, reg);
|
||||
else
|
||||
return cpsw_mdio_read(pdata->mii_bus, addr, devad, reg);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int cpsw_mdio_bus_write(struct udevice *dev, int addr,
|
||||
int devad, int reg, u16 val)
|
||||
{
|
||||
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
|
||||
NULL;
|
||||
struct cpsw_mdio *priv = dev_get_priv(dev);
|
||||
|
||||
if (pdata && pdata->mii_bus) {
|
||||
if (priv->manual_mode)
|
||||
return cpsw_mdio_sw_write(pdata->mii_bus, addr, devad, reg, val);
|
||||
else
|
||||
return cpsw_mdio_write(pdata->mii_bus, addr, devad, reg, val);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static const struct mdio_ops cpsw_mdio_ops = {
|
||||
.read = cpsw_mdio_bus_read,
|
||||
.write = cpsw_mdio_bus_write,
|
||||
};
|
||||
|
||||
static const struct soc_attr k3_mdio_soc_data[] = {
|
||||
{ .family = "AM62X", .revision = "SR1.0" },
|
||||
{ .family = "AM64X", .revision = "SR1.0" },
|
||||
{ .family = "AM64X", .revision = "SR2.0" },
|
||||
{ .family = "AM65X", .revision = "SR1.0" },
|
||||
{ .family = "AM65X", .revision = "SR2.0" },
|
||||
{ .family = "J7200", .revision = "SR1.0" },
|
||||
{ .family = "J7200", .revision = "SR2.0" },
|
||||
{ .family = "J721E", .revision = "SR1.0" },
|
||||
{ .family = "J721E", .revision = "SR1.1" },
|
||||
{ .family = "J721S2", .revision = "SR1.0" },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static const struct udevice_id cpsw_mdio_ids[] = {
|
||||
{ .compatible = "ti,davinci_mdio", },
|
||||
{ .compatible = "ti,cpsw-mdio", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int cpsw_mdio_probe(struct udevice *dev)
|
||||
{
|
||||
struct cpsw_mdio *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
if (!priv) {
|
||||
dev_err(dev, "dev_get_priv(dev %p) = NULL\n", dev);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv->regs = dev_remap_addr(dev);
|
||||
|
||||
if (soc_device_match(k3_mdio_soc_data))
|
||||
priv->manual_mode = true;
|
||||
|
||||
ret = clk_get_by_name(dev, "fck", &priv->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get clock %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv->bus_freq = dev_read_u32_default(dev, "bus_freq",
|
||||
CPSW_MDIO_DEF_BUS_FREQ);
|
||||
ret = cpsw_mdio_init_clk(priv);
|
||||
if (ret) {
|
||||
dev_err(dev, "init clock failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpsw_mdio_remove(struct udevice *dev)
|
||||
{
|
||||
struct cpsw_mdio *priv = dev_get_priv(dev);
|
||||
|
||||
cpsw_mdio_disable(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(cpsw_mdio) = {
|
||||
.name = "cpsw_mdio",
|
||||
.id = UCLASS_MDIO,
|
||||
.of_match = cpsw_mdio_ids,
|
||||
.probe = cpsw_mdio_probe,
|
||||
.remove = cpsw_mdio_remove,
|
||||
.ops = &cpsw_mdio_ops,
|
||||
.priv_auto = sizeof(struct cpsw_mdio),
|
||||
};
|
||||
#endif /* CONFIG_MDIO_TI_CPSW */
|
||||
|
|
|
|||
|
|
@ -10,9 +10,11 @@
|
|||
|
||||
struct cpsw_mdio;
|
||||
|
||||
#if !defined(CONFIG_MDIO_TI_CPSW)
|
||||
struct mii_dev *cpsw_mdio_init(const char *name, phys_addr_t mdio_base,
|
||||
u32 bus_freq, int fck_freq, bool manual_mode);
|
||||
void cpsw_mdio_free(struct mii_dev *bus);
|
||||
u32 cpsw_mdio_get_alive(struct mii_dev *bus);
|
||||
#endif /* CONFIG_MDIO_TI_CPSW */
|
||||
|
||||
#endif /* CPSW_MDIO_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user