rockchip: rk3588-rock-5b: Sync USB3 nodes from mainline linux patches
The device tree for rk3588 and rock-5b contain usb3 nodes that have deviated too much from current state of submitted mainline linux usb3 patches, see [1]. Sync usb3 related nodes from latest patches and collaboras rk3588 tree so that dwc3-generic driver can be updated to include support for the rockchip,rk3588-dwc3 compatible in the future, use rockchip,rk3568-dwc3 compatible until final node is merged in linux maintainer tree. [1] https://lore.kernel.org/lkml/20231009172129.43568-1-sebastian.reichel@collabora.com/ Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
Kever Yang
parent
191ece249a
commit
c1710bfc4f
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@ -19,38 +19,10 @@
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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};
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vcc5v0_usbdcin: vcc5v0-usbdcin {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usbdcin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc12v_dcin>;
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};
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vcc5v0_usb: vcc5v0-usb {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usbdcin>;
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};
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vbus5v0_typec: vbus5v0-typec {
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compatible = "regulator-fixed";
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regulator-name = "vbus5v0_typec";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc5v0_usb>;
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pinctrl-names = "default";
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pinctrl-0 = <&typec5v_pwren>;
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};
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&combphy2_psu {
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status = "okay";
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};
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&fspim2_pins {
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@ -58,13 +30,9 @@
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};
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&pinctrl {
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usb-typec {
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usb {
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usbc0_int: usbc0-int {
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rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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typec5v_pwren: typec5v-pwren {
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rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
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rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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@ -97,7 +65,6 @@
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};
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&u2phy0_otg {
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rockchip,typec-vbus-det;
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status = "okay";
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};
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@ -109,25 +76,17 @@
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status = "okay";
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};
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&usb2phy2_grf {
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&usbdp_phy1 {
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status = "okay";
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};
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&usb2phy3_grf {
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&usbdp_phy1_u3 {
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status = "okay";
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};
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&usb_host0_ehci {
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companion = <&usb_host0_ohci>;
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};
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&usb_host1_ehci {
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companion = <&usb_host1_ohci>;
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};
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&usbdp_phy0 {
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orientation-switch;
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svid = <0xff01>;
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mode-switch;
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sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
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status = "okay";
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@ -135,14 +94,15 @@
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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usbdp_phy0_orientation_switch: endpoint@0 {
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usbdp_phy0_typec_ss: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&usbc0_orien_sw>;
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remote-endpoint = <&usbc0_ss>;
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};
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usbdp_phy0_dp_altmode_mux: endpoint@1 {
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usbdp_phy0_typec_sbu: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&dp_altmode_mux>;
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remote-endpoint = <&usbc0_sbu>;
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};
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};
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};
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@ -151,84 +111,53 @@
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status = "okay";
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};
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&usbdp_phy1 {
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rockchip,dp-lane-mux = <2 3>;
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status = "okay";
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};
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&usbdp_phy1_u3 {
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status = "okay";
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};
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&usbdrd3_0 {
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status = "okay";
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};
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&usbdrd3_1 {
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status = "okay";
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};
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&usbdrd_dwc3_0 {
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&usb_host0_xhci {
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usb-role-switch;
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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dwc3_0_role_switch: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&usbc0_role_sw>;
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usb_host0_xhci_drd_sw: endpoint {
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remote-endpoint = <&usbc0_hs>;
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};
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};
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};
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&usb_host1_xhci {
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status = "okay";
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};
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&usb_host2_xhci {
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4m1_xfer>;
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status = "okay";
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usbc0: fusb302@22 {
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usbc0: usb-typec@22 {
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compatible = "fcs,fusb302";
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reg = <0x22>;
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interrupt-parent = <&gpio3>;
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interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&usbc0_int>;
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vbus-supply = <&vbus5v0_typec>;
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vbus-supply = <&vcc12v_dcin>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usbc0_role_sw: endpoint@0 {
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remote-endpoint = <&dwc3_0_role_switch>;
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};
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};
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};
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usb_con: connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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power-role = "dual";
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power-role = "sink";
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try-power-role = "sink";
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op-sink-microwatt = <1000000>;
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sink-pdos =
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<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
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source-pdos =
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<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
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altmodes {
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#address-cells = <1>;
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#size-cells = <0>;
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altmode@0 {
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reg = <0>;
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svid = <0xff01>;
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vdo = <0xffffffff>;
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};
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};
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<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>,
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<PDO_VAR(5000, 20000, 5000)>;
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ports {
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#address-cells = <1>;
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@ -236,15 +165,22 @@
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port@0 {
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reg = <0>;
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usbc0_orien_sw: endpoint {
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remote-endpoint = <&usbdp_phy0_orientation_switch>;
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usbc0_hs: endpoint {
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remote-endpoint = <&usb_host0_xhci_drd_sw>;
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};
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};
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port@1 {
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reg = <1>;
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dp_altmode_mux: endpoint {
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remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
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usbc0_ss: endpoint {
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remote-endpoint = <&usbdp_phy0_typec_ss>;
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};
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};
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port@2 {
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reg = <2>;
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usbc0_sbu: endpoint {
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remote-endpoint = <&usbdp_phy0_typec_sbu>;
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};
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};
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};
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@ -6,32 +6,24 @@
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#include "rk3588s-u-boot.dtsi"
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/ {
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usbdrd3_1: usbdrd3_1 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
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usb_host1_xhci: usb@fc400000 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
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reg = <0x0 0xfc400000 0x0 0x400000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
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<&cru ACLK_USB3OTG1>;
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clock-names = "ref", "suspend", "bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "ref_clk", "suspend_clk", "bus_clk";
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dr_mode = "host";
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phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG1>;
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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status = "disabled";
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usbdrd_dwc3_1: usb@fc400000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfc400000 0x0 0x400000>;
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG1>;
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reset-names = "usb3-otg";
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dr_mode = "host";
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phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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};
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};
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usbdpphy1_grf: syscon@fd5cc000 {
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@ -56,7 +48,6 @@
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy1";
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#clock-cells = <0>;
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rockchip,usbctrl-grf = <&usb_grf>;
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status = "disabled";
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u2phy1_otg: otg-port {
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@ -21,35 +21,47 @@
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status = "okay";
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};
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usbdrd3_0: usbdrd3_0 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
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usb_host0_xhci: usb@fc000000 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
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reg = <0x0 0xfc000000 0x0 0x400000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
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<&cru ACLK_USB3OTG0>;
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clock-names = "ref", "suspend", "bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clock-names = "ref_clk", "suspend_clk", "bus_clk";
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dr_mode = "otg";
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phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG0>;
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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status = "disabled";
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};
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usbdrd_dwc3_0: usb@fc000000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfc000000 0x0 0x400000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG0>;
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reset-names = "usb3-otg";
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dr_mode = "otg";
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phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
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phy-names = "usb2-phy", "usb3-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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quirk-skip-phy-init;
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};
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usb_host2_xhci: usb@fcd00000 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3568-dwc3", "snps,dwc3";
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reg = <0x0 0xfcd00000 0x0 0x400000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
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<&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
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<&cru CLK_PIPEPHY2_PIPE_U3_G>;
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clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
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dr_mode = "host";
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phys = <&combphy2_psu PHY_TYPE_USB3>;
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phy-names = "usb3-phy";
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phy_type = "utmi_wide";
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resets = <&cru SRST_A_USB3OTG2>;
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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snps,dis_rxdet_inp3_quirk;
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status = "disabled";
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};
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pmu1_grf: syscon@fd58a000 {
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@ -58,6 +70,11 @@
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reg = <0x0 0xfd58a000 0x0 0x2000>;
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};
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usbdpphy0_grf: syscon@fd5c8000 {
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compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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reg = <0x0 0xfd5c8000 0x0 0x4000>;
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};
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usb2phy0_grf: syscon@fd5d0000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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@ -75,7 +92,6 @@
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clock-names = "phyclk";
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clock-output-names = "usb480m_phy0";
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#clock-cells = <0>;
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rockchip,usbctrl-grf = <&usb_grf>;
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status = "disabled";
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u2phy0_otg: otg-port {
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@ -101,7 +101,6 @@ CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_DM_USB_GADGET=y
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CONFIG_USB_XHCI_HCD=y
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# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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