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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Browse Source 
- i2c dm model support of lx2160a, ls1088a, lx2088a, ls1028a
- icid setup for ls1028a, ls1088a
- other small fixes
This commit is contained in:
Tom Rini 2019-08-22 07:29:54 -04:00
commit c399dca834
70 changed files with 1526 additions and 189 deletions
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3
arch/arm/Kconfig
View File

@ -1093,6 +1093,7 @@ config TARGET_LS2080A_SIMU
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
help
Support for Freescale LS2080A_SIMU platform
The LS2080A Development System (QDS) is a pre silicon
@ -1306,6 +1307,8 @@ config TARGET_LS1028AQDS
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select ARCH_MISC_INIT
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance

36
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -40,14 +40,6 @@ config ARCH_LS1028A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC_I2C5
select SYS_I2C_MXC_I2C6
select SYS_I2C_MXC_I2C7
select SYS_I2C_MXC_I2C8
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@ -155,10 +147,10 @@ config ARCH_LS1088A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC_I2C1 if !TFABOOT
select SYS_I2C_MXC_I2C2 if !TFABOOT
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
imply SCSI
imply PANIC_HANG
@ -205,10 +197,10 @@ config ARCH_LS2080A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC_I2C1 if !TFABOOT
select SYS_I2C_MXC_I2C2 if !TFABOOT
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
imply DISTRO_DEFAULTS
imply PANIC_HANG
@ -235,14 +227,6 @@ config ARCH_LX2160A
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC_I2C5
select SYS_I2C_MXC_I2C6
select SYS_I2C_MXC_I2C7
select SYS_I2C_MXC_I2C8
imply DISTRO_DEFAULTS
imply PANIC_HANG
imply SCSI
@ -513,6 +497,10 @@ config SYS_FSL_DUART_CLK_DIV
config SYS_FSL_I2C_CLK_DIV
int "I2C clock divider"
default 1 if ARCH_LS1043A
default 4 if ARCH_LS1012A
default 4 if ARCH_LS1028A
default 8 if ARCH_LX2160A
default 8 if ARCH_LS1088A
default 2
help
This is the divider that is used to derive I2C clock from Platform

2
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View File

@ -47,8 +47,10 @@ endif
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
obj-y += icid.o ls1088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1028A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
obj-y += icid.o ls1028_ids.o
endif

5
arch/arm/cpu/armv8/fsl-layerscape/icid.c
View File

@ -17,7 +17,10 @@ static void set_icid(struct icid_id_table *tbl, int size)
int i;
for (i = 0; i < size; i++)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
if (tbl[i].le)
out_le32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
else
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
#ifdef CONFIG_SYS_DPAA_FMAN

33
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

30
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c Normal file
View File

@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = {
SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

4
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -340,6 +340,10 @@ void fsl_lsch3_early_init_f(void)
if (fsl_check_boot_mode_secure() == 1)
bypass_smmu();
#endif
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
set_icids();
#endif
}
/* Get VDD in the unit mV from voltage ID */

13
arch/arm/dts/fsl-ls1028a-qds.dts
View File

@ -37,10 +37,23 @@
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
};
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
&i2c2 {

20
arch/arm/dts/fsl-ls1028a-rdb.dts
View File

@ -37,6 +37,26 @@
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&i2c1 {

23
arch/arm/dts/fsl-ls1088a-qds.dts
View File

@ -18,6 +18,29 @@
};
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;

23
arch/arm/dts/fsl-ls1088a-rdb.dts
View File

@ -17,6 +17,29 @@
};
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&qspi {
bus-num = <0>;
status = "okay";

32
arch/arm/dts/fsl-ls1088a.dtsi
View File

@ -34,6 +34,38 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 4>;
};
i2c1: i2c@2010000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 4>;
};
i2c2: i2c@2020000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 4>;
};
i2c3: i2c@2030000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 4>;
};
serial0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";

19
arch/arm/dts/fsl-ls2080a-qds.dts
View File

@ -19,6 +19,25 @@
};
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
};
};
&dspi {
bus-num = <0>;
status = "okay";

36
arch/arm/dts/fsl-ls2080a.dtsi
View File

@ -56,6 +56,42 @@
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
};
i2c0: i2c@2000000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
};
i2c1: i2c@2010000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 0x4>; /* Level high type */
};
i2c2: i2c@2020000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
};
i2c3: i2c@2030000 {
status = "disabled";
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 0x4>; /* Level high type */
};
dspi: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;

22
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
View File

@ -57,6 +57,28 @@
};
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
pca9547@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
};
};
&sata {
status = "okay";
};

23
arch/arm/dts/fsl-lx2160a-qds.dts
View File

@ -23,6 +23,29 @@
status = "okay";
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
};
};
&sata0 {
status = "okay";
};

14
arch/arm/dts/fsl-lx2160a-rdb.dts
View File

@ -27,6 +27,20 @@
status = "okay";
};
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
};
&i2c4 {
status = "okay";
rtc@51 {
compatible = "pcf2127-rtc";
reg = <0x51>;
};
};
&sata0 {
status = "okay";
};

85
arch/arm/dts/fsl-lx2160a.dtsi
View File

@ -49,6 +49,80 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <0 34 4>;
scl-gpio = <&gpio2 15 0>;
status = "disabled";
};
i2c1: i2c@2010000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <0 34 4>;
status = "disabled";
};
i2c2: i2c@2020000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <0 35 4>;
status = "disabled";
};
i2c3: i2c@2030000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <0 35 4>;
status = "disabled";
};
i2c4: i2c@2040000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <0 74 4>;
scl-gpio = <&gpio2 16 0>;
status = "disabled";
};
i2c5: i2c@2050000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <0 74 4>;
status = "disabled";
};
i2c6: i2c@2060000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <0 75 4>;
status = "disabled";
};
i2c7: i2c@2070000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <0 75 4>;
status = "disabled";
};
uart0: serial@21c0000 {
compatible = "arm,pl011";
reg = <0x0 0x21c0000 0x0 0x1000>;
@ -102,6 +176,17 @@
num-cs = <6>;
};
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
interrupts = <0 37 4>;
gpio-controller;
little-endian;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;

2
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -178,8 +178,10 @@
#elif defined(CONFIG_ARCH_LX2160A)
#define TZPC_BASE 0x02200000
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
#if !defined(CONFIG_DM_I2C)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#define SRDS_MAX_LANES 8
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6

106
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View File

@ -17,6 +17,7 @@ struct icid_id_table {
u32 reg;
phys_addr_t compat_addr;
phys_addr_t reg_addr;
bool le;
};
struct fman_icid_id_table {
@ -30,18 +31,35 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
void set_icids(void);
void fdt_fixup_icid(void *blob);
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .compat = name, \
.id = idA, \
.reg = regA, \
.compat_addr = compataddr, \
.reg_addr = addr, \
.le = _le \
}
#ifdef CONFIG_SYS_FSL_SEC_LE
#define SEC_IS_LE true
#elif defined(CONFIG_SYS_FSL_SEC_BE)
#define SEC_IS_LE false
#endif
#ifdef CONFIG_FSL_LSCH2
#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
#define SCFG_IS_LE true
#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
#define SCFG_IS_LE false
#endif
#define QDMA_IS_LE false
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
compataddr)
compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
@ -55,14 +73,6 @@ void fdt_fixup_icid(void *blob);
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
CONFIG_SYS_FSL_ESDHC_ADDR)
#define SET_QDMA_ICID(compat, streamid) \
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
QDMA_BASE_ADDR), \
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
QDMA_BASE_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
EDMA_BASE_ADDR)
@ -81,22 +91,78 @@ void fdt_fixup_icid(void *blob);
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_ADDR, \
CONFIG_SYS_FSL_QMAN_ADDR)
CONFIG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_ADDR, \
CONFIG_SYS_FSL_BMAN_ADDR)
CONFIG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR)
CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
extern struct fman_icid_id_table fman_icid_tbl[];
extern int fman_icid_tbl_sz;
#else /* CONFIG_FSL_LSCH2 */
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
#define GUR_IS_LE true
#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
#define GUR_IS_LE false
#endif
#define QDMA_IS_LE true
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, streamid, \
offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
compataddr, GUR_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
#define SET_SATA_ICID(sata_num, compat, streamid) \
SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
AHCI_BASE_ADDR##sata_num)
#define SET_SDHC_ICID(sdhc_num, streamid) \
SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
FSL_ESDHC##sdhc_num##_BASE_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
EDMA_BASE_ADDR)
#define SET_GPU_ICID(compat, streamid) \
SET_GUR_ICID(compat, streamid, misc1_amqr,\
GPU_BASE_ADDR)
#define SET_DISPLAY_ICID(streamid) \
SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
DISPLAY_BASE_ADDR)
#define SEC_ICID_REG_VAL(streamid) (streamid)
#endif /* CONFIG_FSL_LSCH2 */
#define SET_QDMA_ICID(compat, streamid) \
SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
QDMA_BASE_ADDR, QDMA_IS_LE), \
SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
QDMA_BASE_ADDR, QDMA_IS_LE)
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY( \
@ -106,24 +172,22 @@ void fdt_fixup_icid(void *blob);
? NULL \
: "fsl,sec-v4.0-job-ring"), \
streamid, \
(((streamid) << 16) | (streamid)), \
SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
FSL_SEC_JR##jr_num##_BASE_ADDR)
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, 0)
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, 0)
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[];
extern struct fman_icid_id_table fman_icid_tbl[];
extern int icid_tbl_sz;
extern int fman_icid_tbl_sz;
#endif

29
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -25,6 +25,8 @@
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
#endif
@ -79,20 +81,41 @@
#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
/* EDMA */
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x012c0000)
/* SATA */
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
/* QDMA */
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
#define QMAN_CQSIDR_REG 0x20a80
/* DISPLAY */
#define DISPLAY_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e080000)
/* GPU */
#define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000)
/* SFP */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x07020000ull
#define FSL_SEC_JR2_OFFSET 0x07030000ull
#define FSL_SEC_JR3_OFFSET 0x07040000ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
#ifdef CONFIG_TFABOOT
#ifdef CONFIG_NXP_LSCH3_2
@ -417,7 +440,8 @@ struct ccsr_gur {
u32 usb2_amqr;
u8 res_528[0x530-0x528]; /* add more registers when needed */
u32 sdmm1_amqr;
u8 res_534[0x550-0x534]; /* add more registers when needed */
u32 sdmm2_amqr;
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
u8 res_558[0x570-0x558]; /* add more registers when needed */
@ -425,7 +449,8 @@ struct ccsr_gur {
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;
u32 spare2_amqr;
u8 res_598[0x620-0x598]; /* add more registers when needed */
u32 spare3_amqr;
u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */
u32 gencr[7]; /* General Control Registers */
u8 res_63c[0x640-0x63c]; /* add more registers when needed */
u32 cgensr1; /* Core General Status Register */

13
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View File

@ -76,7 +76,7 @@
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
#define FSL_DMA_STREAM_ID 6
#elif defined(CONFIG_ARCH_LS1088A)
#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
#define FSL_DMA_STREAM_ID 5
#endif
@ -98,4 +98,15 @@
#define FSL_DPAA2_STREAM_ID_START 23
#define FSL_DPAA2_STREAM_ID_END 63
#define FSL_SEC_STREAM_ID 64
#define FSL_SEC_JR1_STREAM_ID 65
#define FSL_SEC_JR2_STREAM_ID 66
#define FSL_SEC_JR3_STREAM_ID 67
#define FSL_SEC_JR4_STREAM_ID 68
#define FSL_SDMMC2_STREAM_ID 69
#define FSL_EDMA_STREAM_ID 70
#define FSL_GPU_STREAM_ID 71
#define FSL_DISPLAY_STREAM_ID 72
#endif

4
arch/arm/include/asm/gpio.h
View File

@ -1,6 +1,8 @@
#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
!defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \
!defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>

21
board/freescale/common/emc2305.c
View File

@ -24,10 +24,22 @@ void set_fan_speed(u8 data)
I2C_EMC2305_FAN5};
for (index = 0; index < NUM_OF_FANS; index++) {
#ifndef CONFIG_DM_I2C
if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
#else
struct udevice *dev;
if (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
continue;
if (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {
printf("Error: failed to change fan speed @%x\n",
Fan[index]);
}
#endif
}
}
@ -36,6 +48,15 @@ void emc2305_init(void)
u8 data;
data = I2C_EMC2305_CMD;
#ifndef CONFIG_DM_I2C
if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
printf("Error: failed to configure EMC2305\n");
#else
struct udevice *dev;
if (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))
if (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))
printf("Error: failed to configure EMC2305\n");
#endif
}

62
board/freescale/common/qixis.c
View File

@ -21,16 +21,40 @@
#define QIXIS_LBMAP_BRDCFG_REG 0x00
#endif
#ifndef QIXIS_RCFG_CTL_RECONFIG_IDLE
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#endif
#ifndef QIXIS_RCFG_CTL_RECONFIG_START
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#endif
#ifdef CONFIG_SYS_I2C_FPGA_ADDR
u8 qixis_read_i2c(unsigned int reg)
{
#ifndef CONFIG_DM_I2C
return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
#else
struct udevice *dev;
if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
return 0xff;
return dm_i2c_reg_read(dev, reg);
#endif
}
void qixis_write_i2c(unsigned int reg, u8 value)
{
u8 val = value;
#ifndef CONFIG_DM_I2C
i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
#else
struct udevice *dev;
if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))
dm_i2c_reg_write(dev, reg, val);
#endif
}
#endif
@ -142,11 +166,13 @@ static void qixis_reset(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
}
#ifdef QIXIS_LBMAP_ALTBANK
static void qixis_bank_reset(void)
{
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
}
#endif
static void __maybe_unused set_lbmap(int lbmap)
{
@ -159,12 +185,16 @@ static void __maybe_unused set_lbmap(int lbmap)
static void __maybe_unused set_rcw_src(int rcw_src)
{
#ifdef CONFIG_NXP_LSCH3_2
QIXIS_WRITE(dutcfg[0], (rcw_src & 0xff));
#else
u8 reg;
reg = QIXIS_READ(dutcfg[1]);
reg = (reg & ~1) | (rcw_src & 1);
QIXIS_WRITE(dutcfg[1], reg);
QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
#endif
}
static void qixis_dump_regs(void)
@ -210,16 +240,20 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
set_lbmap(QIXIS_LBMAP_DFLTBANK);
qixis_reset();
} else if (strcmp(argv[1], "altbank") == 0) {
#ifdef QIXIS_LBMAP_ALTBANK
set_lbmap(QIXIS_LBMAP_ALTBANK);
qixis_bank_reset();
#else
printf("No Altbank!\n");
#endif
} else if (strcmp(argv[1], "nand") == 0) {
#ifdef QIXIS_LBMAP_NAND
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_NAND);
set_rcw_src(QIXIS_RCW_SRC_NAND);
QIXIS_WRITE(rcfg_ctl, 0x20);
QIXIS_WRITE(rcfg_ctl, 0x21);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@ -233,8 +267,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
#endif
QIXIS_WRITE(rcfg_ctl, 0x20);
QIXIS_WRITE(rcfg_ctl, 0x21);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@ -244,8 +278,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_IFC);
set_rcw_src(QIXIS_RCW_SRC_IFC);
QIXIS_WRITE(rcfg_ctl, 0x20);
QIXIS_WRITE(rcfg_ctl, 0x21);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@ -255,8 +289,8 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
QIXIS_WRITE(rcfg_ctl, 0x20);
QIXIS_WRITE(rcfg_ctl, 0x21);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@ -266,8 +300,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_SD_QSPI);
set_rcw_src(QIXIS_RCW_SRC_SD);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
QIXIS_RCFG_CTL_RECONFIG_IDLE);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
@ -277,8 +313,10 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_QSPI);
set_rcw_src(QIXIS_RCW_SRC_QSPI);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
QIXIS_RCFG_CTL_RECONFIG_IDLE);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif

84
board/freescale/common/sys_eeprom.c
View File

@ -149,23 +149,42 @@ static int read_eeprom(void)
{
int ret;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
#ifndef CONFIG_DM_I2C
unsigned int bus;
#endif
#endif
if (has_been_read)
return 0;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
#ifndef CONFIG_DM_I2C
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
#endif
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e, sizeof(e));
#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e, sizeof(e));
#else
struct udevice *dev;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
#else
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
#endif
if (!ret)
ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
#endif
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
#ifndef CONFIG_DM_I2C
i2c_set_bus_num(bus);
#endif
#endif
#ifdef DEBUG
show_eeprom();
@ -199,7 +218,9 @@ static int prog_eeprom(void)
int i;
void *p;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
#ifndef CONFIG_DM_I2C
unsigned int bus;
#endif
#endif
/* Set the reserved values to 0xFF */
@ -211,9 +232,11 @@ static int prog_eeprom(void)
#endif
update_crc();
#ifndef CONFIG_DM_I2C
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
bus = i2c_get_bus_num();
i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
#endif
#endif
/*
@ -222,8 +245,26 @@ static int prog_eeprom(void)
* complete a given write.
*/
for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
#ifndef CONFIG_DM_I2C
ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
p, min((int)(sizeof(e) - i), 8));
#else
struct udevice *dev;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
#else
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
#endif
if (!ret)
ret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i),
8));
#endif
if (ret)
break;
udelay(5000); /* 5ms write cycle timing */
@ -233,14 +274,33 @@ static int prog_eeprom(void)
/* Verify the write by reading back the EEPROM and comparing */
struct eeprom e2;
#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&e2, sizeof(e2));
#else
struct udevice *dev;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
#else
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
#endif
if (!ret)
ret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));
#endif
if (!ret && memcmp(&e, &e2, sizeof(e)))
ret = -1;
}
#ifndef CONFIG_DM_I2C
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
i2c_set_bus_num(bus);
#endif
#endif
if (ret) {
@ -529,8 +589,24 @@ unsigned int get_cpu_board_revision(void)
u8 minor; /* 0x05 Board revision, minor */
} be;
#ifndef CONFIG_DM_I2C
i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(void *)&be, sizeof(be));
#else
struct udevice *dev;
#ifdef CONFIG_SYS_EEPROM_BUS_NUM
ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev);
#else
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
&dev)
#endif
if (!ret)
dm_i2c_read(dev, 0, (void *)&be, sizeof(be));
#endif
if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
return MPC85XX_CPU_BOARD_REV(0, 0);

84
board/freescale/common/vid.c
View File

@ -61,13 +61,23 @@ static int find_ir_chip_on_i2c(void)
u8 byte;
int i;
const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
#ifdef CONFIG_DM_I2C
struct udevice *dev;
#endif
/* Check all the address */
for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
i2caddress = ir_i2c_addr[i];
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
sizeof(byte));
#else
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,
(void *)&byte, sizeof(byte));
#endif
if ((ret >= 0) && (byte == IR36021_MFR_ID))
return i2caddress;
}
@ -103,11 +113,21 @@ static int read_voltage_from_INA220(int i2caddress)
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf[2];
#ifdef CONFIG_DM_I2C
struct udevice *dev;
#endif
for (i = 0; i < NUM_READINGS; i++) {
#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
(void *)&buf, 2);
#else
ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,
(void *)&buf, 2);
#endif
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
@ -136,11 +156,21 @@ static int read_voltage_from_IR(int i2caddress)
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
#endif
for (i = 0; i < NUM_READINGS; i++) {
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_LOOP1_VOUT_OFFSET,
1, (void *)&buf, 1);
#else
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,
(void *)&buf, 1);
#endif
if (ret) {
printf("VID: failed to read vcpu\n");
return ret;
@ -179,17 +209,33 @@ static int read_voltage_from_LTC(int i2caddress)
int ret, vcode = 0;
u8 chan = PWM_CHANNEL0;
#ifndef CONFIG_DM_I2C
/* select the PAGE 0 using PMBus commands PAGE for VDD*/
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);
#endif
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
#ifndef CONFIG_DM_I2C
/*read the output voltage using PMBus command READ_VOUT*/
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
#else
ret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
}
#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@ -294,8 +340,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
vid = DIV_ROUND_UP(vdd - 245, 5);
#endif
#ifndef CONFIG_DM_I2C
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,
(void *)&vid, sizeof(vid));
#endif
if (ret) {
printf("VID: failed to write VID\n");
return -1;
@ -331,8 +387,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)
vdd & 0xFF, (vdd & 0xFF00) >> 8};
/* Write the desired voltage code to the regulator */
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_VOL_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
(void *)&buff, 5);
#endif
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@ -516,14 +581,24 @@ int adjust_vdd(ulong vdd_override)
}
/* check IR chip work on Intel mode*/
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
(void *)&buf, 1);
#endif
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;
goto exit;
}
if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
printf("VID: IR Chip is not used in Intel mode.\n");
ret = -1;
@ -688,9 +763,18 @@ int adjust_vdd(ulong vdd_override)
}
/* check IR chip work on Intel mode*/
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2caddress,
IR36021_INTEL_MODE_OOFSET,
1, (void *)&buf, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,
(void *)&buf, 1);
#endif
if (ret) {
printf("VID: failed to read IR chip mode.\n");
ret = -1;

11
board/freescale/ls1028a/ls1028a.c
View File

@ -13,6 +13,7 @@
#include <linux/libfdt.h>
#include <env_internal.h>
#include <asm/arch-fsl-layerscape/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <i2c.h>
#include <asm/arch/soc.h>
#ifdef CONFIG_FSL_LS_PPA
@ -73,7 +74,15 @@ int board_init(void)
#if defined(CONFIG_TARGET_LS1028ARDB)
u8 val = I2C_MUX_CH_DEFAULT;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
#else
struct udevice *dev;
if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
dm_i2c_write(dev, 0x0b, &val, 1);
#endif
#endif
return 0;
}
@ -135,6 +144,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory_banks(blob, base, size, 2);
fdt_fixup_icid(blob);
return 0;
}
#endif

143
board/freescale/ls1088a/eth_ls1088aqds.c
View File

@ -81,11 +81,16 @@ struct ls1088a_qds_mdio {
struct mii_dev *realbus;
};
struct reg_pair {
uint addr;
u8 *val;
};
static void sgmii_configure_repeater(int dpmac)
{
struct mii_dev *bus;
uint8_t a = 0xf;
int i, j, ret;
int i, j, k, ret;
unsigned short value;
const char *dev = "LS1088A_QDS_MDIO2";
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@ -97,8 +102,28 @@ static void sgmii_configure_repeater(int dpmac)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
struct reg_pair reg_pair[10] = {
{6, &reg_val[0]}, {4, &reg_val[1]},
{8, &reg_val[2]}, {0xf, NULL},
{0x11, NULL}, {0x16, NULL},
{0x18, NULL}, {0x23, &reg_val[3]},
{0x2d, &reg_val[4]}, {4, &reg_val[5]},
};
#ifdef CONFIG_DM_I2C
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
#ifndef CONFIG_DM_I2C
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
if (!ret)
ret = dm_i2c_write(udev, 0, &a, 1);
#endif
if (ret)
goto error;
switch (dpmac) {
case 1:
@ -144,31 +169,34 @@ static void sgmii_configure_repeater(int dpmac)
return;
}
#ifdef CONFIG_DM_I2C
i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
#endif
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_phy_addr, 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_phy_addr, 8, 1, &a, 1);
reg_pair[3].val = &ch_a_eq[i];
reg_pair[4].val = &ch_a_ctl2[j];
reg_pair[5].val = &ch_b_eq[i];
reg_pair[6].val = &ch_b_ctl2[j];
for (k = 0; k < 10; k++) {
#ifndef CONFIG_DM_I2C
ret = i2c_write(i2c_phy_addr,
reg_pair[k].addr,
1, reg_pair[k].val, 1);
#else
ret = i2c_get_chip_for_busnum(0,
i2c_phy_addr,
1, &udev);
if (!ret)
ret = dm_i2c_write(udev,
reg_pair[k].addr,
reg_pair[k].val, 1);
#endif
if (ret)
goto error;
}
i2c_write(i2c_phy_addr, 0xf, 1,
&ch_a_eq[i], 1);
i2c_write(i2c_phy_addr, 0x11, 1,
&ch_a_ctl2[j], 1);
i2c_write(i2c_phy_addr, 0x16, 1,
&ch_b_eq[i], 1);
i2c_write(i2c_phy_addr, 0x18, 1,
&ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
@ -203,7 +231,7 @@ error:
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
int i, j;
int i, j, k;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@ -213,12 +241,32 @@ static void qsgmii_configure_repeater(int dpmac)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
struct reg_pair reg_pair[10] = {
{6, &reg_val[0]}, {4, &reg_val[1]},
{8, &reg_val[2]}, {0xf, NULL},
{0x11, NULL}, {0x16, NULL},
{0x18, NULL}, {0x23, &reg_val[3]},
{0x2d, &reg_val[4]}, {4, &reg_val[5]},
};
const char *dev = mdio_names[EMI1_SLOT1];
int ret = 0;
unsigned short value;
#ifdef CONFIG_DM_I2C
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
#ifndef CONFIG_DM_I2C
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
if (!ret)
ret = dm_i2c_write(udev, 0, &a, 1);
#endif
if (ret)
goto error;
switch (dpmac) {
case 7:
@ -252,28 +300,35 @@ static void qsgmii_configure_repeater(int dpmac)
return;
}
#ifdef CONFIG_DM_I2C
i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
#endif
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_phy_addr, 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_phy_addr, 8, 1, &a, 1);
reg_pair[3].val = &ch_a_eq[i];
reg_pair[4].val = &ch_a_ctl2[j];
reg_pair[5].val = &ch_b_eq[i];
reg_pair[6].val = &ch_b_ctl2[j];
i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
for (k = 0; k < 10; k++) {
#ifndef CONFIG_DM_I2C
ret = i2c_write(i2c_phy_addr,
reg_pair[k].addr,
1, reg_pair[k].val, 1);
#else
ret = i2c_get_chip_for_busnum(0,
i2c_addr[dpmac],
1, &udev);
if (!ret)
ret = dm_i2c_write(udev,
reg_pair[k].addr,
reg_pair[k].val, 1);
#endif
if (ret)
goto error;
}
i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)
goto error;

209
board/freescale/ls1088a/ls1088a.c
View File

@ -21,6 +21,7 @@
#include <hwconfig.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/qixis.h"
#include "ls1088a_qixis.h"
@ -374,7 +375,15 @@ int select_i2c_ch_pca9547(u8 ch)
{
int ret;
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, 0, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -393,38 +402,89 @@ void board_retimer_init(void)
/* Access to Control/Shared register */
reg = 0x0;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
#else
struct udevice *dev;
i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Read device revision and ID */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
#else
dm_i2c_read(dev, 1, &reg, 1);
#endif
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
#else
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Reset Channel Registers */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
#else
dm_i2c_read(dev, 0, &reg, 1);
#endif
reg |= 0x4;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
#else
dm_i2c_write(dev, 0, &reg, 1);
#endif
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x60, &reg, 1);
#endif
reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x61, &reg, 1);
#endif
reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x62, &reg, 1);
#endif
reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x63, &reg, 1);
#endif
reg = 0xcd;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x64, &reg, 1);
#endif
/* Select VCO Divider to full rate (000) */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
#else
dm_i2c_read(dev, 0x2F, &reg, 1);
#endif
reg &= 0x0f;
reg |= 0x70;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x2F, &reg, 1);
#endif
#ifdef CONFIG_TARGET_LS1088AQDS
/* Retimer is connected to I2C1_CH5 */
@ -432,38 +492,88 @@ void board_retimer_init(void)
/* Access to Control/Shared register */
reg = 0x0;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
#else
i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Read device revision and ID */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
#else
dm_i2c_read(dev, 1, &reg, 1);
#endif
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
#else
dm_i2c_write(dev, 0xff, &reg, 1);
#endif
/* Reset Channel Registers */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
#else
dm_i2c_read(dev, 0, &reg, 1);
#endif
reg |= 0x4;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
#else
dm_i2c_write(dev, 0, &reg, 1);
#endif
/* Set data rate as 10.3125 Gbps */
reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x60, &reg, 1);
#endif
reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x61, &reg, 1);
#endif
reg = 0x90;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x62, &reg, 1);
#endif
reg = 0xb3;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x63, &reg, 1);
#endif
reg = 0xcd;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x64, &reg, 1);
#endif
/* Select VCO Divider to full rate (000) */
#ifndef CONFIG_DM_I2C
i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
#else
dm_i2c_read(dev, 0x2F, &reg, 1);
#endif
reg &= 0x0f;
reg |= 0x70;
#ifndef CONFIG_DM_I2C
i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
#else
dm_i2c_write(dev, 0x2F, &reg, 1);
#endif
#endif
/*return the default channel*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@ -482,6 +592,32 @@ int misc_init_r(void)
QIXIS_WRITE(brdcfg[5], brdcfg5);
}
#endif
#ifdef CONFIG_TARGET_LS1088AQDS
u8 brdcfg4, brdcfg5;
if (hwconfig("dspi-on-board")) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
brdcfg4 |= BRDCFG4_SPI;
QIXIS_WRITE(brdcfg[4], brdcfg4);
brdcfg5 = QIXIS_READ(brdcfg[5]);
brdcfg5 &= ~BRDCFG5_SPR_MASK;
brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
QIXIS_WRITE(brdcfg[5], brdcfg5);
} else if (hwconfig("dspi-off-board")) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
brdcfg4 |= BRDCFG4_SPI;
QIXIS_WRITE(brdcfg[4], brdcfg4);
brdcfg5 = QIXIS_READ(brdcfg[5]);
brdcfg5 &= ~BRDCFG5_SPR_MASK;
brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
QIXIS_WRITE(brdcfg[5], brdcfg5);
}
#endif
return 0;
}
#endif
@ -500,16 +636,30 @@ int get_serdes_volt(void)
u8 chan = PWM_CHANNEL0;
/* Select the PAGE 0 using PMBus commands PAGE for VDD */
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE, 1, &chan, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
&chan, 1);
#endif
if (ret) {
printf("VID: failed to select VDD Page 0\n");
return ret;
}
/* Read the output voltage using PMBus command READ_VOUT */
#ifndef CONFIG_DM_I2C
ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
#else
dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
#endif
if (ret) {
printf("VID: failed to read the volatge\n");
return ret;
@ -525,8 +675,17 @@ int set_serdes_volt(int svdd)
svdd & 0xFF, (svdd & 0xFF00) >> 8};
/* Write the desired voltage code to the SVDD regulator */
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
(void *)&buff, 5);
#endif
if (ret) {
printf("VID: I2C failed to write to the volatge regulator\n");
return -1;
@ -557,8 +716,18 @@ int set_serdes_volt(int svdd)
printf("SVDD changing of RDB\n");
/* Read the BRDCFG54 via CLPD */
#ifndef CONFIG_DM_I2C
ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
(void *)&brdcfg4, 1);
#endif
if (ret) {
printf("VID: I2C failed to read the CPLD BRDCFG4\n");
return -1;
@ -567,8 +736,14 @@ int set_serdes_volt(int svdd)
brdcfg4 = brdcfg4 | 0x08;
/* Write to the BRDCFG4 */
#ifndef CONFIG_DM_I2C
ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
#else
ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
(void *)&brdcfg4, 1);
#endif
if (ret) {
debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
return -1;
@ -739,11 +914,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
u16 mc_memory_bank = 0;
u64 *base;
u64 *size;
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
if (mc_memory_base != 0)
mc_memory_bank++;
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
base = calloc(total_memory_banks, sizeof(u64));
size = calloc(total_memory_banks, sizeof(u64));
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@ -760,7 +950,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
if (mc_memory_base != 0) {
for (i = 0; i <= total_memory_banks; i++) {
if (base[i] == 0 && size[i] == 0) {
base[i] = mc_memory_base;
size[i] = mc_memory_size;
break;
}
}
}
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
@ -769,6 +969,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_icid(blob);
if (is_pb_board())
fixup_ls1088ardb_pb_banner(blob);

11
board/freescale/ls1088a/ls1088a_qixis.h
View File

@ -41,4 +41,15 @@
#define BRDCFG5_SPISDHC_MASK 0x0C
#define BRDCFG5_FORCE_SD 0x08
/* Definitions of QIXIS Registers for LS1088AQDS */
/* BRDCFG4 */
#define BRDCFG4_USBOSC_MASK 0x01
#define BRDCFG4_SPI 0x01
/* BRDCFG5 */
#define BRDCFG5_SPR_MASK 0x0f
#define BRDCFG5_SPI_ON_BOARD 0x0a
#define BRDCFG5_SPI_OFF_BOARD 0x0f
#endif

143
board/freescale/ls2080aqds/eth.c
View File

@ -90,11 +90,16 @@ struct ls2080a_qds_mdio {
struct mii_dev *realbus;
};
struct reg_pair {
uint addr;
u8 *val;
};
static void sgmii_configure_repeater(int serdes_port)
{
struct mii_dev *bus;
uint8_t a = 0xf;
int i, j, ret;
int i, j, k, ret;
int dpmac_id = 0, dpmac, mii_bus = 0;
unsigned short value;
char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
@ -105,10 +110,30 @@ static void sgmii_configure_repeater(int serdes_port)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
struct reg_pair reg_pair[10] = {
{6, &reg_val[0]}, {4, &reg_val[1]},
{8, &reg_val[2]}, {0xf, NULL},
{0x11, NULL}, {0x16, NULL},
{0x18, NULL}, {0x23, &reg_val[3]},
{0x2d, &reg_val[4]}, {4, &reg_val[5]},
};
int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
#ifdef CONFIG_DM_I2C
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
#ifndef CONFIG_DM_I2C
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
if (!ret)
ret = dm_i2c_write(udev, 0, &a, 1);
#endif
if (ret)
goto error;
for (dpmac = 0; dpmac < 8; dpmac++) {
/* Check the PHY status */
@ -121,7 +146,15 @@ static void sgmii_configure_repeater(int serdes_port)
mii_bus = 1;
dpmac_id = dpmac + 9;
a = 0xb;
i2c_write(0x76, 0, 0, &a, 1);
#ifndef CONFIG_DM_I2C
ret = i2c_write(0x76, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
if (!ret)
ret = dm_i2c_write(udev, 0, &a, 1);
#endif
if (ret)
goto error;
break;
}
@ -154,29 +187,29 @@ static void sgmii_configure_repeater(int serdes_port)
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
reg_pair[3].val = &ch_a_eq[i];
reg_pair[4].val = &ch_a_ctl2[j];
reg_pair[5].val = &ch_b_eq[i];
reg_pair[6].val = &ch_b_ctl2[j];
i2c_write(i2c_addr[dpmac], 0xf, 1,
&ch_a_eq[i], 1);
i2c_write(i2c_addr[dpmac], 0x11, 1,
&ch_a_ctl2[j], 1);
for (k = 0; k < 10; k++) {
#ifndef CONFIG_DM_I2C
ret = i2c_write(i2c_addr[dpmac],
reg_pair[k].addr,
1, reg_pair[k].val, 1);
#else
ret = i2c_get_chip_for_busnum(0,
i2c_addr[dpmac],
1, &udev);
if (!ret)
ret = dm_i2c_write(udev,
reg_pair[k].addr,
reg_pair[k].val, 1);
#endif
if (ret)
goto error;
}
i2c_write(i2c_addr[dpmac], 0x16, 1,
&ch_b_eq[i], 1);
i2c_write(i2c_addr[dpmac], 0x18, 1,
&ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev[mii_bus],
riser_phy_addr[dpmac],
@ -217,7 +250,7 @@ error:
static void qsgmii_configure_repeater(int dpmac)
{
uint8_t a = 0xf;
int i, j;
int i, j, k;
int i2c_phy_addr = 0;
int phy_addr = 0;
int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
@ -227,12 +260,32 @@ static void qsgmii_configure_repeater(int dpmac)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
struct reg_pair reg_pair[10] = {
{6, &reg_val[0]}, {4, &reg_val[1]},
{8, &reg_val[2]}, {0xf, NULL},
{0x11, NULL}, {0x16, NULL},
{0x18, NULL}, {0x23, &reg_val[3]},
{0x2d, &reg_val[4]}, {4, &reg_val[5]},
};
const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
#ifdef CONFIG_DM_I2C
struct udevice *udev;
#endif
/* Set I2c to Slot 1 */
i2c_write(0x77, 0, 0, &a, 1);
#ifndef CONFIG_DM_I2C
ret = i2c_write(0x77, 0, 0, &a, 1);
#else
ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
if (!ret)
ret = dm_i2c_write(udev, 0, &a, 1);
#endif
if (ret)
goto error;
switch (dpmac) {
case 1:
@ -283,25 +336,29 @@ static void qsgmii_configure_repeater(int dpmac)
for (i = 0; i < 4; i++) {
for (j = 0; j < 4; j++) {
a = 0x18;
i2c_write(i2c_phy_addr, 6, 1, &a, 1);
a = 0x38;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
a = 0x4;
i2c_write(i2c_phy_addr, 8, 1, &a, 1);
reg_pair[3].val = &ch_a_eq[i];
reg_pair[4].val = &ch_a_ctl2[j];
reg_pair[5].val = &ch_b_eq[i];
reg_pair[6].val = &ch_b_ctl2[j];
i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
for (k = 0; k < 10; k++) {
#ifndef CONFIG_DM_I2C
ret = i2c_write(i2c_phy_addr,
reg_pair[k].addr,
1, reg_pair[k].val, 1);
#else
ret = i2c_get_chip_for_busnum(0,
i2c_phy_addr,
1, &udev);
if (!ret)
ret = dm_i2c_write(udev,
reg_pair[k].addr,
reg_pair[k].val, 1);
#endif
if (ret)
goto error;
}
i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
a = 0x14;
i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
a = 0xb5;
i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
a = 0x20;
i2c_write(i2c_phy_addr, 4, 1, &a, 1);
mdelay(100);
ret = miiphy_read(dev, phy_addr, 0x11, &value);
if (ret > 0)

16
board/freescale/ls2080aqds/ls2080aqds.c
View File

@ -161,8 +161,16 @@ unsigned long get_board_ddr_clk(void)
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -225,7 +233,15 @@ int board_init(void)
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#ifdef CONFIG_DM_I2C
rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
#else
rtc_enable_32khz_output();
#endif
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif

41
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -164,7 +164,16 @@ int select_i2c_ch_pca9547(u8 ch)
{
int ret;
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, 0, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -410,11 +419,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int i;
u16 mc_memory_bank = 0;
u64 *base;
u64 *size;
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
if (mc_memory_base != 0)
mc_memory_bank++;
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
base = calloc(total_memory_banks, sizeof(u64));
size = calloc(total_memory_banks, sizeof(u64));
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@ -431,7 +456,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
fdt_fixup_memory_banks(blob, base, size, 2);
if (mc_memory_base != 0) {
for (i = 0; i <= total_memory_banks; i++) {
if (base[i] == 0 && size[i] == 0) {
base[i] = mc_memory_base;
size[i] = mc_memory_size;
break;
}
}
}
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);

59
board/freescale/lx2160a/lx2160a.c
View File

@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch)
{
int ret;
#ifndef CONFIG_DM_I2C
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
struct udevice *dev;
ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
if (!ret)
ret = dm_i2c_write(dev, 0, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
@ -402,6 +410,26 @@ int config_board_mux(void)
return 0;
}
#elif defined(CONFIG_TARGET_LX2160ARDB)
int config_board_mux(void)
{
u8 brdcfg;
brdcfg = QIXIS_READ(brdcfg[4]);
/* The BRDCFG4 register controls general board configuration.
*|-------------------------------------------|
*|Field | Function |
*|-------------------------------------------|
*|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
*|CAN_EN | 0= CAN transceivers are disabled. |
*| | 1= CAN transceivers are enabled. |
*|-------------------------------------------|
*/
brdcfg |= BIT_MASK(5);
QIXIS_WRITE(brdcfg[4], brdcfg);
return 0;
}
#else
int config_board_mux(void)
{
@ -529,11 +557,26 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
u16 mc_memory_bank = 0;
u64 *base;
u64 *size;
u64 mc_memory_base = 0;
u64 mc_memory_size = 0;
u16 total_memory_banks;
ft_cpu_setup(blob, bd);
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
if (mc_memory_base != 0)
mc_memory_bank++;
total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
base = calloc(total_memory_banks, sizeof(u64));
size = calloc(total_memory_banks, sizeof(u64));
/* fixup DT for the three GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@ -553,7 +596,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[2] = gd->arch.resv_ram - base[2];
#endif
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
if (mc_memory_base != 0) {
for (i = 0; i <= total_memory_banks; i++) {
if (base[i] == 0 && size[i] == 0) {
base[i] = mc_memory_base;
size[i] = mc_memory_size;
break;
}
}
}
fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
#ifdef CONFIG_USB
fsl_fdt_fixup_dr_usb(blob, bd);

10
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
@ -8,7 +9,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -31,6 +31,12 @@ CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@ -51,6 +57,8 @@ CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

10
configs/ls1028aqds_tfa_defconfig
View File

@ -1,13 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -34,6 +34,12 @@ CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@ -54,6 +60,8 @@ CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

10
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
@ -8,7 +9,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -31,6 +31,12 @@ CONFIG_NETCONSOLE=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@ -51,6 +57,8 @@ CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

10
configs/ls1028ardb_tfa_defconfig
View File

@ -1,13 +1,13 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -34,6 +34,12 @@ CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@ -54,6 +60,8 @@ CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_qspi_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
@ -47,6 +48,7 @@ CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

2
configs/ls1043aqds_sdcard_qspi_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
@ -61,6 +62,7 @@ CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

2
configs/ls1043aqds_tfa_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_PHYLIB=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
@ -58,6 +59,7 @@ CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y

10
configs/ls1088aqds_tfa_defconfig
View File

@ -2,13 +2,13 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -36,6 +36,12 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@ -53,6 +59,8 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

10
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
@ -9,7 +10,6 @@ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -34,6 +34,12 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@ -47,6 +53,8 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

10
configs/ls1088ardb_tfa_defconfig
View File

@ -2,13 +2,13 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -35,6 +35,12 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
@ -48,6 +54,8 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

8
configs/ls2088aqds_tfa_defconfig
View File

@ -26,7 +26,6 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
@ -38,6 +37,12 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@ -53,6 +58,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

10
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,13 +2,13 @@ CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -29,13 +29,18 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@ -54,6 +59,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y

10
configs/ls2088ardb_tfa_defconfig
View File

@ -2,12 +2,12 @@ CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
@ -28,7 +28,6 @@ CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
@ -39,6 +38,12 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
@ -58,6 +63,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y

9
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
View File

@ -61,3 +61,12 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_RTC=y
CONFIG_DM_GPIO=y
CONFIG_CMD_DATE=y
CONFIG_RTC_PCF2127=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y

9
configs/lx2160aqds_tfa_defconfig
View File

@ -57,3 +57,12 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_RTC=y
CONFIG_DM_GPIO=y
CONFIG_CMD_DATE=y
CONFIG_RTC_PCF2127=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y

7
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
View File

@ -58,3 +58,10 @@ CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_RTC=y
CONFIG_DM_GPIO=y
CONFIG_CMD_DATE=y
CONFIG_RTC_PCF2127=y

7
configs/lx2160ardb_tfa_defconfig
View File

@ -57,3 +57,10 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_DM_RTC=y
CONFIG_DM_GPIO=y
CONFIG_CMD_DATE=y
CONFIG_RTC_PCF2127=y

36
drivers/ddr/fsl/main.c
View File

@ -92,7 +92,10 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
uint8_t dummy = 0;
#endif
#ifndef CONFIG_DM_I2C
i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
#endif
#ifdef CONFIG_SYS_FSL_DDR4
/*
@ -101,6 +104,7 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
* To access the upper 256 bytes, we need to set EE page address to 1
* See Jedec standar No. 21-C for detail
*/
#ifndef CONFIG_DM_I2C
i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
if (!ret) {
@ -111,8 +115,38 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
(int)sizeof(generic_spd_eeprom_t) - 256));
}
#else
struct udevice *dev;
int read_len = min(256, (int)sizeof(generic_spd_eeprom_t) - 256);
ret = i2c_get_chip_for_busnum(0, SPD_SPA0_ADDRESS, 1, &dev);
if (!ret)
dm_i2c_write(dev, 0, &dummy, 1);
ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
if (!ret) {
if (!dm_i2c_read(dev, 0, (uchar *)spd, 256)) {
if (!i2c_get_chip_for_busnum(0, SPD_SPA1_ADDRESS,
1, &dev))
dm_i2c_write(dev, 0, &dummy, 1);
if (!i2c_get_chip_for_busnum(0, i2c_address, 1, &dev))
ret = dm_i2c_read(dev, 0,
(uchar *)((ulong)spd + 256),
read_len);
}
}
#endif
#else
#ifndef CONFIG_DM_I2C
ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
sizeof(generic_spd_eeprom_t));
sizeof(generic_spd_eeprom_t));
#else
ret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);
if (!ret)
ret = dm_i2c_read(dev, 0, (uchar *)spd,
sizeof(generic_spd_eeprom_t));
#endif
#endif
if (ret) {

15
drivers/i2c/mxc_i2c.c
View File

@ -558,6 +558,14 @@ static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
return 0;
}
int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
{
return 1;
}
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
__attribute__((weak, alias("__enable_i2c_clk")));
#ifndef CONFIG_DM_I2C
/*
* Read data from I2C device
@ -723,13 +731,6 @@ static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
}
int __enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
return 1;
}
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
__attribute__((weak, alias("__enable_i2c_clk")));
void bus_i2c_init(int index, int speed, int unused,
int (*idle_bus_fn)(void *p), void *idle_bus_data)
{

10
drivers/net/fsl-mc/mc.c
View File

@ -282,6 +282,16 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
MC_FIXUP_DPL);
}
void fdt_fixup_mc_ddr(u64 *base, u64 *size)
{
u64 mc_size = mc_get_dram_block_size();
if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
*base = mc_get_dram_addr() + mc_size;
*size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
}
}
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;

6
drivers/rtc/Kconfig
View File

@ -31,6 +31,12 @@ config TPL_DM_RTC
drivers to perform the actual functions. See rtc.h for a
description of the API.
config RTC_ENABLE_32KHZ_OUTPUT
bool "Enable RTC 32Khz output"
help
Some real-time clocks support the output of 32kHz square waves (such as ds3231),
the config symbol choose Real Time Clock device 32Khz output feature.
config RTC_PCF2127
bool "Enable PCF2127 driver"
depends on DM_RTC

17
drivers/rtc/ds3231.c
View File

@ -148,11 +148,13 @@ void rtc_reset (void)
/*
* Enable 32KHz output
*/
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
void rtc_enable_32khz_output(void)
{
rtc_write(RTC_STAT_REG_ADDR,
RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
}
#endif
/*
* Helper functions
@ -251,6 +253,21 @@ static int ds3231_probe(struct udevice *dev)
return 0;
}
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
int rtc_enable_32khz_output(int busnum, int chip_addr)
{
int ret;
struct udevice *dev;
ret = i2c_get_chip_for_busnum(busnum, chip_addr, 1, &dev);
if (!ret)
ret = dm_i2c_reg_write(dev, RTC_STAT_REG_ADDR,
RTC_STAT_BIT_BB32KHZ |
RTC_STAT_BIT_EN32KHZ);
return ret;
}
#endif
static const struct rtc_ops ds3231_rtc_ops = {
.get = ds3231_rtc_get,
.set = ds3231_rtc_set,

2
include/configs/ls1028a_common.h
View File

@ -42,7 +42,9 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1

1
include/configs/ls1028aqds.h
View File

@ -16,7 +16,6 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_EARLY_INIT
/*
* QIXIS Definitions

1
include/configs/ls1028ardb.h
View File

@ -22,7 +22,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_EARLY_INIT
/*
* QIXIS Definitions

1
include/configs/ls1043aqds.h
View File

@ -382,7 +382,6 @@ unsigned long get_board_ddr_clk(void);
/* QSPI device */
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
#define CONFIG_FSL_QSPI
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE (1 << 24)

3
include/configs/ls1046afrwy.h
View File

@ -103,6 +103,9 @@
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \
CONFIG_ENV_OFFSET)
/* FMan */
#ifdef CONFIG_SYS_DPAA_FMAN

3
include/configs/ls1088a_common.h
View File

@ -67,7 +67,10 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL

6
include/configs/ls1088aqds.h
View File

@ -17,6 +17,8 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_TFABOOT
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_MISC_INIT_R
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x500000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
@ -46,7 +48,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_DDR_CLK_FREQ 100000000
#else
#define CONFIG_QIXIS_I2C_ACCESS
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
#endif
@ -357,9 +361,7 @@ unsigned long get_board_ddr_clk(void);
* RTC configuration
*/
#define RTC
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
/* EEPROM */
#define CONFIG_ID_EEPROM

2
include/configs/ls1088ardb.h
View File

@ -269,9 +269,7 @@
* RTC configuration
*/
#define RTC
#define CONFIG_RTC_PCF8563 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#define CONFIG_CMD_DATE
#endif
/* EEPROM */

2
include/configs/ls2080a_common.h
View File

@ -75,7 +75,9 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
/* I2C */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#endif
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL

4
include/configs/ls2080aqds.h
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@ -16,7 +16,9 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
#endif
@ -324,7 +326,9 @@ unsigned long get_board_ddr_clk(void);
*/
#define RTC
#define CONFIG_RTC_DS3231 1
#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
/* EEPROM */
#define CONFIG_ID_EEPROM

2
include/configs/ls2080ardb.h
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@ -13,8 +13,10 @@
#ifdef CONFIG_TARGET_LS2081ARDB
#define CONFIG_QIXIS_I2C_ACCESS
#endif
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C_EARLY_INIT
#endif
#endif
#define I2C_MUX_CH_VOL_MONITOR 0xa
#define I2C_VOL_MONITOR_ADDR 0x38

1
include/fsl-mc/fsl_mc.h
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@ -55,6 +55,7 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
int is_lazy_dpl_addr_valid(void);
void fdt_fixup_mc_ddr(u64 *base, u64 *size);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif

6
include/rtc.h
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@ -166,11 +166,17 @@ int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep);
*/
int rtc_write32(struct udevice *dev, unsigned int reg, u32 value);
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
int rtc_enable_32khz_output(int busnum, int chip_addr);
#endif
#else
int rtc_get (struct rtc_time *);
int rtc_set (struct rtc_time *);
void rtc_reset (void);
#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
void rtc_enable_32khz_output(void);
#endif
/**
* rtc_read8() - Read an 8-bit register