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Merge tag 'u-boot-imx-master-20240108' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
- Removed fdt_addr from verdin-imx8mm to fix booting via bootefi.
- Support Ethernet PHY autodection on Data Modul i.MX8M Mini/Plus eDM
  SBC
- Add i.MX93 binman support
- Add support for imx93-var-som
This commit is contained in:
Tom Rini 2024-01-08 13:39:00 -05:00
commit c5e461fbf7
41 changed files with 3585 additions and 12 deletions
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3
arch/arm/dts/Makefile
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@ -1125,7 +1125,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-evk.dtb
imx93-11x11-evk.dtb \
imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \

6
arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi
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@ -51,12 +51,6 @@
};
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
bootph-pre-ram;
};

2
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
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@ -3,6 +3,8 @@
* Copyright 2022 NXP
*/
#include "imx93-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";

88
arch/arm/dts/imx93-u-boot.dtsi Normal file
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@ -0,0 +1,88 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Mathieu Othacehe <m.othacehe@gmail.com>
*/
/ {
binman: binman {
multiple-images;
};
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
ddr-1d-imem-fw {
filename = "lpddr4_imem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_dmem_1d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_imem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_dmem_2d_v202201.bin";
align-end = <4>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x2049A000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
u-boot-container {
filename = "u-boot-container.bin";
mkimage {
args = "-n u-boot-container.cfgout -T imx8image -e 0x0";
blob {
filename = "u-boot.bin";
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
filename = "spl.bin";
offset = <0x0>;
align-size = <0x400>;
align = <0x400>;
};
uboot: blob-ext@2 {
filename = "u-boot-container.bin";
};
};
};

266
arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi Normal file
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@ -0,0 +1,266 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
#include "imx93-u-boot.dtsi"
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
bootph-pre-ram;
bootph-some-ram;
};
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
bootph-all;
bootph-pre-ram;
};
&aips1 {
bootph-pre-ram;
bootph-all;
};
&aips2 {
bootph-pre-ram;
bootph-some-ram;
};
&aips3 {
bootph-pre-ram;
bootph-some-ram;
};
&iomuxc {
bootph-pre-ram;
bootph-some-ram;
};
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};
&pinctrl_uart1 {
bootph-pre-ram;
bootph-some-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio1 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio2 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio3 {
bootph-pre-ram;
bootph-some-ram;
};
&gpio4 {
bootph-pre-ram;
bootph-some-ram;
};
&lpuart1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc1 {
bootph-pre-ram;
bootph-some-ram;
};
&usdhc2 {
bootph-pre-ram;
bootph-some-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&ethphy0 {
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&ethphy1 {
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
&s4muap {
bootph-pre-ram;
bootph-some-ram;
status = "okay";
};
&clk {
bootph-all;
bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&osc_32k {
bootph-all;
bootph-pre-ram;
};
&osc_24m {
bootph-all;
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
bootph-pre-ram;
};
/*
* The two nodes below won't be needed once nxp,pca9451a
* support is added to the Linux kernel.
*/
&iomuxc {
pinctrl_lpi2c3: lpi2c3grp {
bootph-pre-ram;
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
};
&lpi2c3 {
bootph-pre-ram;
bootph-some-ram;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
pmic@25 {
bootph-pre-ram;
bootph-some-ram;
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
regulators {
bootph-pre-ram;
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

305
arch/arm/dts/imx93-var-som-symphony.dts Normal file
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@ -0,0 +1,305 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 NXP
* Copyright 2023 Variscite Ltd.
*/
/dts-v1/;
#include "imx93-var-som.dtsi"
/{
model = "Variscite VAR-SOM-MX93 on Symphony evaluation board";
compatible = "variscite,var-som-mx93-symphony",
"variscite,var-som-mx93", "fsl,imx93";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
chosen {
stdout-path = &lpuart1;
};
/*
* Needed only for Symphony <= v1.5
*/
reg_fec_phy: regulator-fec-phy {
compatible = "regulator-fixed";
regulator-name = "fec-phy";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <20000>;
gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <20000>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ethosu_mem: ethosu-region@88000000 {
compatible = "shared-dma-pool";
reusable;
reg = <0x0 0x88000000 0x0 0x8000000>;
};
vdev0vring0: vdev0vring0@87ee0000 {
reg = <0 0x87ee0000 0 0x8000>;
no-map;
};
vdev0vring1: vdev0vring1@87ee8000 {
reg = <0 0x87ee8000 0 0x8000>;
no-map;
};
vdev1vring0: vdev1vring0@87ef0000 {
reg = <0 0x87ef0000 0 0x8000>;
no-map;
};
vdev1vring1: vdev1vring1@87ef8000 {
reg = <0 0x87ef8000 0 0x8000>;
no-map;
};
rsc_table: rsc-table@2021f000 {
reg = <0 0x2021f000 0 0x1000>;
no-map;
};
vdevbuffer: vdevbuffer@87f00000 {
compatible = "shared-dma-pool";
reg = <0 0x87f00000 0 0x100000>;
no-map;
};
ele_reserved: ele-reserved@87de0000 {
compatible = "shared-dma-pool";
reg = <0 0x87de0000 0 0x100000>;
no-map;
};
};
};
/* Use external instead of internal RTC*/
&bbnsm_rtc {
status = "disabled";
};
&eqos {
mdio {
ethphy1: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <5>;
qca,disable-smarteee;
eee-broken-1000t;
reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <20000>;
vddio-supply = <&vddio1>;
vddio1: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec_phy>;
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&iomuxc {
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_CLK__CAN1_TX 0x139e
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
fsl,pins = <
MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
>;
};
pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
fsl,pins = <
MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e
MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e
>;
};
pinctrl_pca9534: pca9534grp {
fsl,pins = <
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
/* DS1337 RTC module */
rtc@68 {
compatible = "dallas,ds1337";
reg = <0x68>;
};
};
&lpi2c5 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c5>;
pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
pinctrl-2 = <&pinctrl_lpi2c5_gpio>;
scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
status = "okay";
pca9534: gpio@20 {
compatible = "nxp,pca9534";
reg = <0x20>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9534>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
#gpio-cells = <2>;
wakeup-source;
};
};
/* Console */
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
clock-names = "ipg", "per";
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
no-sdio;
no-mmc;
};
/* Watchdog */
&wdog3 {
status = "okay";
};

111
arch/arm/dts/imx93-var-som.dtsi Normal file
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@ -0,0 +1,111 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
/dts-v1/;
#include "imx93.dtsi"
/{
model = "Variscite VAR-SOM-MX93 module";
compatible = "variscite,var-som-mx93", "fsl,imx93";
mmc_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
reg_eqos_phy: regulator-eqos-phy {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eqos_phy>;
regulator-name = "eth_phy_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
regulator-always-on;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
phy-supply = <&reg_eqos_phy>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <1000000>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
};
};
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_reg_eqos_phy: regeqosgrp {
fsl,pins = <
MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};

1
arch/arm/include/asm/arch-imx9/clock.h
View File

@ -222,6 +222,7 @@ u32 mxc_get_clock(enum mxc_clock clk);
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
void set_arm_core_max_clk(void);
int configure_intpll(enum ccm_clk_src pll, u32 freq);

27
arch/arm/mach-imx/Makefile
View File

@ -129,6 +129,9 @@ DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctre
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
DEPFILE_EXISTS := 0
else ifeq ($(CONFIG_ARCH_IMX9), y)
IMAGE_TYPE := imx8image
DEPFILE_EXISTS := 0
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
@ -213,7 +216,29 @@ endif
endif
ifeq ($(CONFIG_ARCH_IMX9), y)
SPL:
quiet_cmd_imx9_check = CHECK $@
cmd_imx9_check = $(srctree)/tools/imx9_image.sh $@
SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout u-boot-container.cfgout FORCE
MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
flash.bin: MKIMAGEOUTPUT = flash.log
spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
$(call if_changed,imx9_check)
spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
u-boot-container.cfgout: $(IMX_CONTAINER_CFG) FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
$(call if_changed,imx9_check)
flash.bin: spl/u-boot-spl-ddr.bin container.cfgout FORCE
$(call if_changed,mkimage)
endif
else

8
arch/arm/mach-imx/imx9/Kconfig
View File

@ -29,11 +29,19 @@ choice
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
select BINMAN
select IMX93
config TARGET_IMX93_VAR_SOM
bool "imx93_var_som"
select BINMAN
select IMX93
select IMX9_LPDDR4X
endchoice
source "board/freescale/imx93_evk/Kconfig"
source "board/variscite/imx93_var_som/Kconfig"
endif

10
arch/arm/mach-imx/imx9/container.cfg Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2023 Mathieu Othacehe <m.othacehe@gmail.com>
*/
BOOT_FROM SD 0x400
SOC_TYPE IMX9
CONTAINER
IMAGE A55 bl31.bin 0x204E0000
IMAGE A55 u-boot.bin CONFIG_TEXT_BASE

10
arch/arm/mach-imx/imx9/imximage.cfg Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2023 Mathieu Othacehe <m.othacehe@gmail.com>
*/
BOOT_FROM SD 0x400
SOC_TYPE IMX9
APPEND mx93a0-ahab-container.img
CONTAINER
IMAGE A55 u-boot-spl-ddr.bin 0x2049A000

42
board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
View File

@ -5,9 +5,11 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <linux/bitfield.h>
#include <malloc.h>
#include <spl.h>
@ -34,3 +36,43 @@ int board_late_init(void)
return 0;
}
int fdtdec_board_setup(const void *fdt_blob)
{
const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
FIELD_GET(MUX_CTRL_OFS_MASK, IMX8MM_PAD_ENET_MDC_GPIO1_IO16);
const char *phy_compat = "ethernet-phy-ieee802.3-c22";
bool is_bcmphy;
int phy_node;
int ret;
/* Do nothing if not i.MX8MM eDM SBC */
ret = fdt_node_check_compatible(fdt_blob, 0, "dmo,imx8mm-data-modul-edm-sbc");
if (ret)
return 0;
/*
* If GPIO1_16 RGMII_MDC is HIGH, then R530 is populated.
* R530 is populated only on boards with AR8031 PHY.
*
* If GPIO1_16 RGMII_MDC is LOW, then the in-SoM pull down
* is the dominant pull resistor. This is the case on boards
* with BCM54213PE PHY.
*/
setbits_le32(mux, IOMUX_CONFIG_SION);
is_bcmphy = !(readl(GPIO1_BASE_ADDR) & BIT(16));
clrbits_le32(mux, IOMUX_CONFIG_SION);
phy_node = fdt_node_offset_by_compatible(fdt_blob, -1, phy_compat);
if (phy_node < 0)
return 0;
/*
* Update PHY MDC address in control DT based on the populated
* PHY type. AR8031 is at address 0, BCM54213PE is at address 1.
*/
fdt_setprop_inplace_u32((void *)fdt_blob, phy_node,
"reg", is_bcmphy ? 1 : 0);
return 0;
}

50
board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c
View File

@ -5,11 +5,13 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <env.h>
#include <env_internal.h>
#include <linux/bitfield.h>
#include <malloc.h>
#include <net.h>
#include <spl.h>
@ -65,3 +67,51 @@ int board_late_init(void)
return 0;
}
int fdtdec_board_setup(const void *fdt_blob)
{
const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_MDC__ENET_QOS_MDC);
const char *phy_compat = "ethernet-phy-ieee802.3-c22";
bool is_bcmphy;
int phy_node;
int ret;
/* Do nothing if not i.MX8MP eDM SBC */
ret = fdt_node_check_compatible(fdt_blob, 0, "dmo,imx8mp-data-modul-edm-sbc");
if (ret)
return 0;
/*
* If GPIO1_16 RGMII_MDC is HIGH, then R390 is populated.
* R390 is populated only on boards with AR8031 PHY.
*
* If GPIO1_16 RGMII_MDC is LOW, then the in-SoM pull down
* is the dominant pull resistor. This is the case on boards
* with BCM54213PE PHY.
*/
setbits_le32(mux, IOMUX_CONFIG_SION);
is_bcmphy = !(readl(GPIO1_BASE_ADDR) & BIT(16));
clrbits_le32(mux, IOMUX_CONFIG_SION);
phy_node = fdt_node_offset_by_compatible(fdt_blob, -1, phy_compat);
if (phy_node < 0)
return 0;
/*
* Update PHY MDC address in control DT based on the populated
* PHY type. AR8031 is at address 0, BCM54213PE is at address 1.
*/
fdt_setprop_inplace_u32((void *)fdt_blob, phy_node,
"reg", is_bcmphy ? 1 : 0);
/* Apply the same modification to EQoS PHY */
phy_node = fdt_node_offset_by_compatible(fdt_blob, phy_node, phy_compat);
if (phy_node < 0)
return 0;
fdt_setprop_inplace_u32((void *)fdt_blob, phy_node,
"reg", is_bcmphy ? 1 : 0);
return 0;
}

58
board/variscite/common/eth.c Normal file
View File

@ -0,0 +1,58 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2023 Variscite Ltd.
*/
#include <net.h>
#include <miiphy.h>
#include <env.h>
#include "../common/imx9_eeprom.h"
#define CHAR_BIT 8
static u64 mac2int(const u8 hwaddr[])
{
u8 i;
u64 ret = 0;
const u8 *p = hwaddr;
for (i = 6; i > 0; i--)
ret |= (u64)*p++ << (CHAR_BIT * (i - 1));
return ret;
}
static void int2mac(const u64 mac, u8 *hwaddr)
{
u8 i;
u8 *p = hwaddr;
for (i = 6; i > 0; i--)
*p++ = mac >> (CHAR_BIT * (i - 1));
}
int var_setup_mac(struct var_eeprom *eeprom)
{
int ret;
unsigned char enetaddr[6];
u64 addr;
unsigned char enet1addr[6];
ret = eth_env_get_enetaddr("ethaddr", enetaddr);
if (ret)
return 0;
ret = var_eeprom_get_mac(eeprom, enetaddr);
if (ret)
return ret;
if (!is_valid_ethaddr(enetaddr))
return -EINVAL;
eth_env_set_enetaddr("ethaddr", enetaddr);
addr = mac2int(enetaddr);
int2mac(addr + 1, enet1addr);
eth_env_set_enetaddr("eth1addr", enet1addr);
return 0;
}

12
board/variscite/common/eth.h Normal file
View File

@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2023 Variscite Ltd.
*
*/
#ifndef _MX9_ETH_H_
#define _MX9_ETH_H_
int var_setup_mac(struct var_eeprom *eeprom);
#endif /* _MX9_ETH_H_ */

190
board/variscite/common/imx9_eeprom.c Normal file
View File

@ -0,0 +1,190 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2023 Variscite Ltd.
*
*/
#include <command.h>
#include <dm.h>
#include <i2c.h>
#include <asm/io.h>
#include <cpu_func.h>
#include <u-boot/crc.h>
#include <asm/arch-imx9/ddr.h>
#include "imx9_eeprom.h"
static int var_eeprom_get_dev(struct udevice **devp)
{
int ret;
struct udevice *bus;
ret = uclass_get_device_by_name(UCLASS_I2C, VAR_SOM_EEPROM_I2C_NAME, &bus);
if (ret) {
printf("%s: No EEPROM I2C bus '%s'\n", __func__,
VAR_SOM_EEPROM_I2C_NAME);
return ret;
}
ret = dm_i2c_probe(bus, VAR_SOM_EEPROM_I2C_ADDR, 0, devp);
if (ret) {
printf("%s: I2C EEPROM probe failed\n", __func__);
return ret;
}
i2c_set_chip_offset_len(*devp, 1);
i2c_set_chip_addr_offset_mask(*devp, 1);
return 0;
}
int var_eeprom_read_header(struct var_eeprom *e)
{
int ret;
struct udevice *dev;
ret = var_eeprom_get_dev(&dev);
if (ret) {
printf("%s: Failed to detect I2C EEPROM\n", __func__);
return ret;
}
/* Read EEPROM header to memory */
ret = dm_i2c_read(dev, 0, (void *)e, sizeof(*e));
if (ret) {
printf("%s: EEPROM read failed, ret=%d\n", __func__, ret);
return ret;
}
return 0;
}
int var_eeprom_get_mac(struct var_eeprom *ep, u8 *mac)
{
flush_dcache_all();
if (!var_eeprom_is_valid(ep))
return -1;
memcpy(mac, ep->mac, sizeof(ep->mac));
return 0;
}
int var_eeprom_get_dram_size(struct var_eeprom *ep, phys_size_t *size)
{
/* No data in EEPROM - return default DRAM size */
if (!var_eeprom_is_valid(ep)) {
*size = DEFAULT_SDRAM_SIZE;
return 0;
}
*size = (ep->dramsize * 128UL) << 20;
return 0;
}
void var_eeprom_print_prod_info(struct var_eeprom *ep)
{
if (IS_ENABLED(CONFIG_SPL_BUILD))
return;
flush_dcache_all();
if (!var_eeprom_is_valid(ep))
return;
if (IS_ENABLED(CONFIG_TARGET_IMX93_VAR_SOM))
printf("\nPart number: VSM-MX93-%.*s\n",
(int)sizeof(ep->partnum), ep->partnum);
printf("Assembly: AS%.*s\n", (int)sizeof(ep->assembly), (char *)ep->assembly);
printf("Production date: %.*s %.*s %.*s\n",
4, /* YYYY */
(char *)ep->date,
3, /* MMM */
((char *)ep->date) + 4,
2, /* DD */
((char *)ep->date) + 4 + 3);
printf("Serial Number: %02x:%02x:%02x:%02x:%02x:%02x\n",
ep->mac[0], ep->mac[1], ep->mac[2], ep->mac[3], ep->mac[4], ep->mac[5]);
debug("EEPROM version: 0x%x\n", ep->version);
debug("SOM features: 0x%x\n", ep->features);
printf("SOM revision: 0x%x\n", ep->somrev);
printf("DRAM PN: VIC-%04d\n", ep->ddr_vic);
debug("DRAM size: %d GiB\n\n", (ep->dramsize * 128) / 1024);
}
int var_carrier_eeprom_read(const char *bus_name, int addr, struct var_carrier_eeprom *ep)
{
int ret;
struct udevice *bus;
struct udevice *dev;
ret = uclass_get_device_by_name(UCLASS_I2C, bus_name, &bus);
if (ret) {
printf("%s: No bus '%s'\n", __func__, bus_name);
return ret;
}
ret = dm_i2c_probe(bus, addr, 0, &dev);
if (ret) {
printf("%s: Carrier EEPROM I2C probe failed\n", __func__);
return ret;
}
/* Read EEPROM to memory */
ret = dm_i2c_read(dev, 0, (void *)ep, sizeof(*ep));
if (ret) {
printf("%s: Carrier EEPROM read failed, ret=%d\n", __func__, ret);
return ret;
}
return 0;
}
int var_carrier_eeprom_is_valid(struct var_carrier_eeprom *ep)
{
u32 crc, crc_offset = offsetof(struct var_carrier_eeprom, crc);
if (htons(ep->magic) != VAR_CARRIER_EEPROM_MAGIC) {
printf("Invalid carrier EEPROM magic 0x%x, expected 0x%x\n",
htons(ep->magic), VAR_CARRIER_EEPROM_MAGIC);
return 0;
}
if (ep->struct_ver < 1) {
printf("Invalid carrier EEPROM version 0x%x\n", ep->struct_ver);
return 0;
}
if (ep->struct_ver == 1)
return 1;
/* Only EEPROM structure above version 1 has CRC field */
crc = crc32(0, (void *)ep, crc_offset);
if (crc != ep->crc) {
printf("Carrier EEPROM CRC mismatch (%08x != %08x)\n",
crc, be32_to_cpu(ep->crc));
return 0;
}
return 1;
}
/*
* Returns carrier board revision string via 'rev' argument. For legacy
* carrier board revisions the "legacy" string is returned. For new carrier
* board revisions the actual carrier revision is returned. Symphony-Board
* 1.4 and below are legacy, 1.4a and above are new. DT8MCustomBoard 1.4 and
* below are legacy, 2.0 and above are new.
*
*/
void var_carrier_eeprom_get_revision(struct var_carrier_eeprom *ep, char *rev, size_t size)
{
if (var_carrier_eeprom_is_valid(ep))
strlcpy(rev, (const char *)ep->carrier_rev, size);
else
strlcpy(rev, "legacy", size);
}

83
board/variscite/common/imx9_eeprom.h Normal file
View File

@ -0,0 +1,83 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2023 Variscite Ltd.
*
*/
#ifndef _MX9_VAR_EEPROM_H_
#define _MX9_VAR_EEPROM_H_
#ifdef CONFIG_ARCH_IMX9
#include <asm/arch-imx9/ddr.h>
#endif
#define VAR_SOM_EEPROM_MAGIC 0x4D58 /* == HEX("MX") */
#define VAR_SOM_EEPROM_I2C_ADDR 0x52
/* Optional SOM features */
#define VAR_EEPROM_F_WIFI BIT(0)
#define VAR_EEPROM_F_ETH BIT(1)
#define VAR_EEPROM_F_AUDIO BIT(2)
/* SOM storage types */
enum som_storage {
SOM_STORAGE_EMMC,
SOM_STORAGE_NAND,
SOM_STORAGE_UNDEFINED,
};
/* Number of DRAM adjustment tables */
#define DRAM_TABLE_NUM 7
struct __packed var_eeprom
{
u16 magic; /* 00-0x00 - magic number */
u8 partnum[8]; /* 02-0x02 - part number */
u8 assembly[10]; /* 10-0x0a - assembly number */
u8 date[9]; /* 20-0x14 - build date */
u8 mac[6]; /* 29-0x1d - MAC address */
u8 somrev; /* 35-0x23 - SOM revision */
u8 version; /* 36-0x24 - EEPROM version */
u8 features; /* 37-0x25 - SOM features */
u8 dramsize; /* 38-0x26 - DRAM size */
u8 reserved[5]; /* 39 0x27 - reserved */
u32 ddr_crc32; /* 44-0x2c - CRC32 of DDR DATAi */
u16 ddr_vic; /* 48-0x30 - DDR VIC PN */
u16 off[DRAM_TABLE_NUM + 1]; /* 50-0x32 - DRAM table offsets */
};
#define VAR_EEPROM_DATA ((struct var_eeprom *)VAR_EEPROM_DRAM_START)
#define VAR_CARRIER_EEPROM_MAGIC 0x5643 /* == HEX("VC") */
#define CARRIER_REV_LEN 16
struct __packed var_carrier_eeprom
{
u16 magic; /* 00-0x00 - magic number */
u8 struct_ver; /* 01-0x01 - EEPROM structure version */
u8 carrier_rev[CARRIER_REV_LEN]; /* 02-0x02 - carrier board revision */
u32 crc; /* 10-0x0a - checksum */
};
static inline int var_eeprom_is_valid(struct var_eeprom *ep)
{
if (htons(ep->magic) != VAR_SOM_EEPROM_MAGIC) {
debug("Invalid EEPROM magic 0x%x, expected 0x%x\n",
htons(ep->magic), VAR_SOM_EEPROM_MAGIC);
return 0;
}
return 1;
}
int var_eeprom_read_header(struct var_eeprom *e);
int var_eeprom_get_dram_size(struct var_eeprom *e, phys_size_t *size);
int var_eeprom_get_mac(struct var_eeprom *e, u8 *mac);
void var_eeprom_print_prod_info(struct var_eeprom *e);
int var_carrier_eeprom_read(const char *bus_name, int addr, struct var_carrier_eeprom *ep);
int var_carrier_eeprom_is_valid(struct var_carrier_eeprom *ep);
void var_carrier_eeprom_get_revision(struct var_carrier_eeprom *ep, char *rev, size_t size);
#endif /* _MX9_VAR_EEPROM_H_ */

47
board/variscite/common/mmc.c Normal file
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@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
*/
#include <command.h>
#include <asm/arch/sys_proto.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <stdbool.h>
#include <mmc.h>
#include <vsprintf.h>
#include <env.h>
static int check_mmc_autodetect(void)
{
char *autodetect_str = env_get("mmcautodetect");
if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
return 1;
return 0;
}
/* This should be defined for each board */
__weak int mmc_map_to_kernel_blk(int dev_no)
{
return dev_no;
}
void board_late_mmc_env_init(void)
{
char cmd[32];
u32 dev_no = mmc_get_env_dev();
if (!check_mmc_autodetect())
return;
env_set_ulong("mmcdev", dev_no);
/* Set mmcblk env */
env_set_ulong("mmcblk", mmc_map_to_kernel_blk(dev_no));
sprintf(cmd, "mmc dev %d", dev_no);
run_command(cmd, 0);
}

12
board/variscite/imx93_var_som/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_IMX93_VAR_SOM
config SYS_BOARD
default "imx93_var_som"
config SYS_VENDOR
default "variscite"
config SYS_CONFIG_NAME
default "imx93_var_som"
endif

7
board/variscite/imx93_var_som/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
ARM i.MX93 VARISCITE VAR-SOM-MX93 MODULE
M: Mathieu Othacehe <m.othacehe@gmail.com>
S: Maintained
F: arch/arm/dts/imx93-var-som*
F: board/variscite/imx93_var_som/
F: configs/imx93_var_som_defconfig
F: include/configs/imx93_var_som.h

17
board/variscite/imx93_var_som/Makefile Normal file
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@ -0,0 +1,17 @@
#
# Copyright 2022 NXP
# Copyright 2023 Variscite Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx93_var_som.o
obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += ../common/imx9_eeprom.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_TARGET_IMX93_VAR_SOM) += lpddr4x_timing.o
else
obj-y += ../common/eth.o
obj-y += ../common/mmc.o
endif

126
board/variscite/imx93_var_som/imx93_var_som.c Normal file
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@ -0,0 +1,126 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
#include <env.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/global_data.h>
#include <asm/arch-imx9/ccm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx9/imx93_pins.h>
#include <asm/arch/clock.h>
#include <power/pmic.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include "../common/imx9_eeprom.h"
#include "../common/eth.h"
DECLARE_GLOBAL_DATA_PTR;
#define CARRIER_EEPROM_ADDR 0x54
#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t uart_pads[] = {
MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(LPUART1_CLK_ROOT);
return 0;
}
int board_phys_sdram_size(phys_size_t *size)
{
struct var_eeprom *ep = VAR_EEPROM_DATA;
var_eeprom_get_dram_size(ep, size);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
static int setup_eqos(void)
{
struct blk_ctrl_wakeupmix_regs *bctrl =
(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&bctrl->eqos_gpr,
BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
return set_clk_eqos(ENET_125MHZ);
}
int board_init(void)
{
set_clk_enet(ENET_125MHZ);
if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
setup_eqos();
return 0;
}
#define SDRAM_SIZE_STR_LEN 5
int board_late_init(void)
{
int ret;
struct var_eeprom *ep = VAR_EEPROM_DATA;
char sdram_size_str[SDRAM_SIZE_STR_LEN];
struct var_carrier_eeprom carrier_eeprom;
char carrier_rev[CARRIER_REV_LEN] = {0};
char som_rev[CARRIER_REV_LEN] = {0};
var_setup_mac(ep);
var_eeprom_print_prod_info(ep);
/* SDRAM ENV */
snprintf(sdram_size_str, SDRAM_SIZE_STR_LEN, "%d",
(int)(gd->ram_size / 1024 / 1024));
env_set("sdram_size", sdram_size_str);
/* Carrier Board ENV */
ret = var_carrier_eeprom_read(VAR_CARRIER_EEPROM_I2C_NAME,
CARRIER_EEPROM_ADDR, &carrier_eeprom);
if (!ret) {
var_carrier_eeprom_get_revision(&carrier_eeprom, carrier_rev,
sizeof(carrier_rev));
env_set("carrier_rev", carrier_rev);
}
/* SoM Rev ENV */
snprintf(som_rev, CARRIER_REV_LEN, "som_rev1%d", ep->somrev);
env_set("som_rev", som_rev);
if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
board_late_mmc_env_init();
env_set("sec_boot", "no");
if (IS_ENABLED(CONFIG_AHAB_BOOT))
env_set("sec_boot", "yes");
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
env_set("board_name", "VAR-SOM-MX93");
return 0;
}

99
board/variscite/imx93_var_som/imx93_var_som.env Normal file
View File

@ -0,0 +1,99 @@
initrd_addr=0x83800000
image=Image.gz
img_addr=0x82000000
console=ttyLP0,115200
fdt_addr_r=0x83000000
fdt_addr=0x83000000
cntr_addr=0x98000000
cntr_file=os_cntr_signed.bin
boot_fit=no
bootdir=/boot
fdt_file=undefined
bootm_size=0x10000000
mmcdev=0
mmcpart=1
mmcautodetect=yes
optargs=setenv bootargs ${bootargs} ${kernelargs};
mmcroot=root=/dev/mmcblk0p1
mmcargs=setenv bootargs ${jh_clk} console=${console} ${mmcroot} rootwait rw
loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootdir}/${script};
bootscript=echo Running bootscript from mmc ...; source
loadimage=load mmc ${mmcdev}:${mmcpart} ${img_addr} ${bootdir}/${image};
unzip ${img_addr} ${loadaddr}
findfdt=if test $fdt_file = undefined; then
setenv fdt_file CONFIG_DEFAULT_FDT_FILE ;
fi;
echo fdt_file=${fdt_file};
loadfdt=run findfdt;load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${bootdir}/${fdt_file}
loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}
auth_os=auth_cntr ${cntr_addr}
boot_os=booti ${loadaddr} - ${fdt_addr_r};
mmcboot=echo Booting from mmc ...;
run mmcargs;
run optargs;
if test ${sec_boot} = yes; then
if run auth_os; then
"run boot_os;
else
"echo ERR: failed to authenticate;
fi;
else
if test ${boot_fit} = yes || test ${boot_fit} = try; then
bootm ${loadaddr};
else
if run loadfdt; then
run boot_os;
else
echo WARN: Cannot load the DT;
fi;
fi;
fi;
netargs=setenv bootargs ${jh_clk} console=${console}
root=/dev/nfs
ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
etboot=echo Booting from net ...;
run netargs;
run optargs;
if test ${ip_dyn} = yes; then
setenv get_cmd dhcp;
else
setenv get_cmd tftp;
fi;
if test ${sec_boot} = yes; then
${get_cmd} ${cntr_addr} ${cntr_file};
if run auth_os; then
"run boot_os;
else
"echo ERR: failed to authenticate;
fi;
else
${get_cmd} ${img_addr} ${image}; unzip ${img_addr} ${loadaddr};
if test ${boot_fit} = yes || test ${boot_fit} = try; then
bootm ${loadaddr};
else
run findfdt;
if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then
run boot_os;
else
echo WARN: Cannot load the DT;
fi;
fi;
fi;
bsp_bootcmd=echo Running BSP bootcmd ...;
mmc dev ${mmcdev}; if mmc rescan; then
if run loadbootscript; then
run bootscript;
else
if test ${sec_boot} = yes; then
if run loadcntr; then
run mmcboot;
else run netboot;
fi;
else
if run loadimage; then
run mmcboot;
else run netboot;
fi;
fi;
fi;
fi;

1488
board/variscite/imx93_var_som/lpddr4x_timing.c Normal file
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File diff suppressed because it is too large Load Diff

143
board/variscite/imx93_var_som/spl.c Normal file
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@ -0,0 +1,143 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
#include <command.h>
#include <cpu_func.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx93_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/arch-mx7ulp/gpio.h>
#include <asm/sections.h>
#include <asm/mach-imx/syscounter.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <linux/delay.h>
#include <asm/arch/clock.h>
#include <asm/arch/ccm_regs.h>
#include <asm/arch/ddr.h>
#include <power/pmic.h>
#include <power/pca9450.h>
#include <asm/arch/trdc.h>
#include "../common/imx9_eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
static struct var_eeprom eeprom = {0};
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_board_init(void)
{
struct var_eeprom *ep = VAR_EEPROM_DATA;
puts("Normal Boot\n");
/* Copy EEPROM contents to DRAM */
memcpy(ep, &eeprom, sizeof(*ep));
}
void spl_dram_init(void)
{
/* EEPROM initialization */
var_eeprom_read_header(&eeprom);
ddr_init(&dram_timing);
}
int power_init_board(void)
{
struct udevice *dev;
int ret;
if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
puts("No pca9450@25\n");
return 0;
}
if (ret != 0)
return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
/* set standby voltage to 0.65V */
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
}
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
timer_init();
arch_cpu_init();
board_early_init_f();
spl_early_init();
preloader_console_init();
ret = arch_cpu_init();
if (ret) {
printf("Fail to init Sentinel API\n");
} else {
printf("SOC: 0x%x\n", gd->arch.soc_rev);
printf("LC: 0x%x\n", gd->arch.lifecycle);
}
power_init_board();
set_arm_core_max_clk();
/* Init power of mix */
soc_power_init();
/* Setup TRDC for DDR access */
trdc_init();
/* DDR initialization */
spl_dram_init();
/* Put M33 into CPUWAIT for following kick */
ret = m33_prepare();
if (!ret)
printf("M33 prepare ok\n");
board_init_r(NULL, 0);
}

2
common/spl/Kconfig
View File

@ -207,7 +207,7 @@ config SPL_BINMAN_SYMBOLS
config SPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in SPL"
depends on SPL_BINMAN_SYMBOLS
default n if ARCH_IMX8M
default n if ARCH_IMX8M || ARCH_IMX9
default y
help
This enables use of symbols in SPL which refer to U-Boot phases,

2
common/spl/Kconfig.tpl
View File

@ -23,7 +23,7 @@ config TPL_BINMAN_SYMBOLS
config TPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in TPL"
depends on TPL_BINMAN_SYMBOLS
default n if ARCH_IMX8M
default n if ARCH_IMX8M || ARCH_IMX9
default y
help
This enables use of symbols in TPL which refer to U-Boot phases,

2
common/spl/Kconfig.vpl
View File

@ -243,7 +243,7 @@ config VPL_BINMAN_SYMBOLS
config VPL_BINMAN_UBOOT_SYMBOLS
bool "Declare binman symbols for U-Boot phases in VPL"
depends on VPL_BINMAN_SYMBOLS
default n if ARCH_IMX8M
default n if ARCH_IMX8M || ARCH_IMX9
default y
help
This enables use of symbols in VPL which refer to U-Boot phases,

1
configs/imx8mm_data_modul_edm_sbc_defconfig
View File

@ -195,6 +195,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y

1
configs/imx8mp_data_modul_edm_sbc_defconfig
View File

@ -207,6 +207,7 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_MDIO=y

2
configs/imx93_11x11_evk_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000

2
configs/imx93_11x11_evk_ld_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
CONFIG_SPL_TEXT_BASE=0x2049A000

156
configs/imx93_var_som_defconfig Normal file
View File

@ -0,0 +1,156 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX9=y
CONFIG_TEXT_BASE=0x80200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x700000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg"
CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg"
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony"
CONFIG_SPL_TEXT_BASE=0x2049A000
CONFIG_TARGET_IMX93_VAR_SOM=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0x20519dd0
CONFIG_SPL=y
CONFIG_CMD_DEKBLOB=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
CONFIG_SPL_LOAD_IMX_CONTAINER=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_REMAKE_ELF=y
CONFIG_SYS_LOAD_ADDR=0x80400000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_BOOTCOMMAND="run bsp_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx93-var-som-symphony.dtb"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x26000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x2051a000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_CMD_ERASEENV=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_NET=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_BUS=3
CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=100
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_POWEROFF=y
CONFIG_BOOTP_PREFER_SERVERIP=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_IMX93=y
CONFIG_CLK_IMX93=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_BUF_ADDR=0x82800000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_GPIO_HOG=y
CONFIG_IMX_RGPIO2P=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_ADIN=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_MIPI_DPHY_HELPERS=y
CONFIG_PHY_IMX93_MIPI_DPHY=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX93_BLK_CTRL=y
CONFIG_DM_PMIC=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_CI_UDC=y
CONFIG_ULP_WATCHDOG=y
CONFIG_LZO=y
CONFIG_BZIP2=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_WATCHDOG=y
CONFIG_WDT=y
CONFIG_CMD_WDT=y
CONFIG_ETHPRIME="eth0"
CONFIG_SYS_I2C_SPEED=100000
CONFIG_IMX_BOOTAUX=y
CONFIG_CMD_READ=y
CONFIG_SERIAL_TAG=y

68
doc/board/nxp/imx93_11x11_evk.rst Normal file
View File

@ -0,0 +1,68 @@
.. SPDX-License-Identifier: GPL-2.0+
imx93_11x11_evk
=======================
U-Boot for the NXP i.MX93 EVK on the 11x11mm board
Quick Start
-----------
- Get and Build the ARM Trusted firmware
- Get the DDR firmware
- Get ahab-container.img
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
--------------------------------------
Note: srctree is U-Boot source directory
Get ATF from: https://github.com/nxp-imx/imx-atf/
branch: lf_v2.8
.. code-block:: bash
$ unset LDFLAGS
$ make PLAT=imx93 bl31
$ cp build/imx93/release/bl31.bin $(srctree)
Get the DDR firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
$ chmod +x firmware-imx-8.21.bin
$ ./firmware-imx-8.21.bin
$ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Get ahab-container.img
---------------------------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin
$ chmod +x firmware-sentinel-0.10.bin
$ ./firmware-sentinel-0.10.bin
$ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree)
Build U-Boot
------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx93_11x11_evk_defconfig
$ make
Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
Boot
----
Set Boot switch to SD boot

1
doc/board/nxp/index.rst
View File

@ -11,6 +11,7 @@ NXP Semiconductors
imx8mp_evk
imx8mq_evk
imx8qxp_mek
imx93_11x11_evk
imxrt1020-evk
imxrt1050-evk
ls1046ardb

68
doc/board/variscite/imx93_var_som.rst Normal file
View File

@ -0,0 +1,68 @@
.. SPDX-License-Identifier: GPL-2.0+
imx93_var_som
=======================
U-Boot for the Variscite VAR-SOM-MX93 Symphony evaluation board
Quick Start
-----------
- Get and Build the ARM Trusted firmware
- Get the DDR firmware
- Get ahab-container.img
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
--------------------------------------
Note: srctree is U-Boot source directory
Get ATF from: https://github.com/nxp-imx/imx-atf/
branch: lf_v2.8
.. code-block:: bash
$ unset LDFLAGS
$ make PLAT=imx93 bl31
$ cp build/imx93/release/bl31.bin $(srctree)
Get the DDR firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin
$ chmod +x firmware-imx-8.21.bin
$ ./firmware-imx-8.21.bin
$ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree)
Get ahab-container.img
---------------------------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin
$ chmod +x firmware-sentinel-0.10.bin
$ ./firmware-sentinel-0.10.bin
$ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree)
Build U-Boot
------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx93_var_som_defconfig
$ make
Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
Boot
----
Set Boot switch to SD boot

1
doc/board/variscite/index.rst
View File

@ -7,3 +7,4 @@ Variscite
:maxdepth: 2
imx8mn_var_som
imx93_var_som

48
include/configs/imx93_var_som.h Normal file
View File

@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2022 NXP
* Copyright 2023 Variscite Ltd.
*/
#ifndef __IMX93_VAR_SOM_H
#define __IMX93_VAR_SOM_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1)
#include <config_distro_bootcmd.h>
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS BOOTENV
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define DEFAULT_SDRAM_SIZE (512 * SZ_1M) /* 512MB Minimum DDR4, see get_dram_size */
#define VAR_EEPROM_DRAM_START (PHYS_SDRAM + (DEFAULT_SDRAM_SIZE >> 1))
#define VAR_SOM_EEPROM_I2C_NAME "i2c@42530000"
#define VAR_CARRIER_EEPROM_I2C_NAME "i2c@44340000"
#define CFG_SYS_FSL_USDHC_NUM 2
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG3_BASE_ADDR
#if defined(CONFIG_CMD_NET)
#define PHY_ANEG_TIMEOUT 20000
#endif
#endif

1
include/configs/verdin-imx8mm.h
View File

@ -40,7 +40,6 @@
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttymxc0\0" \
"fdt_addr=0x43000000\0" \
"fdt_board=dev\0" \
"initrd_addr=0x43800000\0" \
"initrd_high=0xffffffffffffffff\0" \

31
tools/imx9_image.sh Executable file
View File

@ -0,0 +1,31 @@
#!/bin/sh
# SPDX-License-Identifier: GPL-2.0+
#
# Script to check whether the file exists in mkimage cfg files for the i.MX9.
#
# usage: $0 <file.cfg>
file=$1
blobs=`awk '/^APPEND/ {print $2} /^IMAGE/ || /^DATA/ {print $3}' $file`
for f in $blobs; do
tmp=$srctree/$f
if [ $f = "u-boot-spl-ddr.bin" ]; then
continue
fi
if [ -f $f ]; then
continue
fi
if [ ! -f $tmp ]; then
echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2
# Comment-out the lines for un-existing files. This way,
# mkimage can keep working. This allows CI tests to pass even
# if the resulting binary won't boot.
sed -in "/$f/ s/./#&/" $file
fi
done
exit 0