CV1800B: Pinmux: Added pin functions.
Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
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GPG Key ID:
DB982239424FF8AC
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@ -6,81 +6,633 @@
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#ifndef DT_CV1800B_PINCTRL_H
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#define DT_CV1800B_PINCTRL_H
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#define CVI_CTRL_SD0_CLK (0x000U)
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#define CVI_CTRL_SD0_CMD (0x004U)
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#define CVI_CTRL_SD0_D0 (0x008U)
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#define CVI_CTRL_SD0_D1 (0x00CU)
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#define CVI_CTRL_SD0_D2 (0x010U)
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#define CVI_CTRL_SD0_D3 (0x014U)
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#define CVI_CTRL_SD0_CD (0x018U)
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#define CVI_CTRL_SD0_PWR_EN (0x01CU)
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#define CVI_CTRL_SPK_EN (0x020U)
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#define CVI_CTRL_UART0_TX (0x024U)
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#define CVI_CTRL_UART0_RX (0x028U)
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#define CVI_CTRL_SPINOR_HOLD_X (0x02CU)
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#define CVI_CTRL_SPINOR_SCK (0x030U)
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#define CVI_CTRL_SPINOR_MOSI (0x034U)
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#define CVI_CTRL_SPINOR_WP_X (0x038U)
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#define CVI_CTRL_SPINOR_MISO (0x03CU)
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#define CVI_CTRL_SPINOR_CS_X (0x040U)
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#define CVI_CTRL_JTAG_CPU_TMS (0x044U)
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#define CVI_CTRL_JTAG_CPU_TCK (0x048U)
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#define CVI_CTRL_IIC0_SCL (0x04CU)
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#define CVI_CTRL_IIC0_SDA (0x050U)
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#define CVI_CTRL_AUX0 (0x054U)
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#define CVI_CTRL_GPIO_ZQ (0x058U)
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#define CVI_CTRL_PWR_VBAT_DET (0x05CU)
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#define CVI_CTRL_PWR_RSTN (0x060U)
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#define CVI_CTRL_PWR_SEQ1 (0x064U)
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#define CVI_CTRL_PWR_SEQ2 (0x068U)
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#define CVI_CTRL_PWR_WAKEUP0 (0x06CU)
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#define CVI_CTRL_PWR_BUTTON1 (0x070U)
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#define CVI_CTRL_XTAL_XIN (0x074U)
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#define CVI_CTRL_PWR_GPIO0 (0x078U)
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#define CVI_CTRL_PWR_GPIO1 (0x07CU)
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#define CVI_CTRL_PWR_GPIO2 (0x080U)
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#define CVI_CTRL_SD1_GPIO1 (0x084U)
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#define CVI_CTRL_SD1_GPIO0 (0x088U)
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#define CVI_CTRL_SD1_D3 (0x08CU)
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#define CVI_CTRL_SD1_D2 (0x090U)
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#define CVI_CTRL_SD1_D1 (0x094U)
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#define CVI_CTRL_SD1_D0 (0x098U)
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#define CVI_CTRL_SD1_CMD (0x09CU)
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#define CVI_CTRL_SD1_CLK (0x0A0U)
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#define CVI_CTRL_PWM0_BUCK (0x0A4U)
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#define CVI_CTRL_ADC1 (0x0A8U)
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#define CVI_CTRL_USB_VBUS_DET (0x0ACU)
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#define CVI_CTRL_MUX_SPI1_MISO (0x0B0U)
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#define CVI_CTRL_MUX_SPI1_MOSI (0x0B4U)
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#define CVI_CTRL_MUX_SPI1_CS (0x0B8U)
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#define CVI_CTRL_MUX_SPI1_SCK (0x0BCU)
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#define CVI_CTRL_PAD_ETH_TXP (0x0C0U)
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#define CVI_CTRL_PAD_ETH_TXM (0x0C4U)
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#define CVI_CTRL_PAD_ETH_RXP (0x0C8U)
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#define CVI_CTRL_PAD_ETH_RXM (0x0CCU)
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#define CVI_CTRL_GPIO_RTX (0x0D0U)
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#define CVI_CTRL_PAD_MIPIRX4N (0x0D4U)
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#define CVI_CTRL_PAD_MIPIRX4P (0x0D8U)
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#define CVI_CTRL_PAD_MIPIRX3N (0x0DCU)
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#define CVI_CTRL_PAD_MIPIRX3P (0x0E0U)
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#define CVI_CTRL_PAD_MIPIRX2N (0x0E4U)
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#define CVI_CTRL_PAD_MIPIRX2P (0x0E8U)
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#define CVI_CTRL_PAD_MIPIRX1N (0x0ECU)
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#define CVI_CTRL_PAD_MIPIRX1P (0x0F0U)
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#define CVI_CTRL_PAD_MIPIRX0N (0x0F4U)
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#define CVI_CTRL_PAD_MIPIRX0P (0x0F8U)
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#define CVI_CTRL_PAD_MIPI_TXM2 (0x0FCU)
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#define CVI_CTRL_PAD_MIPI_TXP2 (0x100U)
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#define CVI_CTRL_PAD_MIPI_TXM1 (0x104U)
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#define CVI_CTRL_PAD_MIPI_TXP1 (0x108U)
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#define CVI_CTRL_PAD_MIPI_TXM0 (0x10CU)
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#define CVI_CTRL_PAD_MIPI_TXP0 (0x110U)
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#define CVI_CTRL_PKG_TYPE0 (0x114U)
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#define CVI_CTRL_PKG_TYPE1 (0x118U)
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#define CVI_CTRL_PKG_TYPE2 (0x11CU)
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#define CVI_CTRL_PAD_AUD_AINL_MIC (0x120U)
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#define CVI_CTRL_PAD_AUD_AINR_MIC (0x124U)
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#define CVI_CTRL_PAD_AUD_AOUTL (0x128U)
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#define CVI_CTRL_PAD_AUD_AOUTR (0x12CU)
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/* CTRL register offsets (from PINMUX base) */
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#define CTRL_SD0_CLK (0x00U)
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#define CTRL_SD0_CMD (0x01U)
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#define CTRL_SD0_D0 (0x02U)
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#define CTRL_SD0_D1 (0x03U)
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#define CTRL_SD0_D2 (0x04U)
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#define CTRL_SD0_D3 (0x05U)
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#define CTRL_SD0_CD (0x06U)
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#define CTRL_SD0_PWR_EN (0x07U)
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#define CTRL_SPK_EN (0x08U)
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#define CTRL_UART0_TX (0x09U)
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#define CTRL_UART0_RX (0x0AU)
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#define CTRL_SPINOR_HOLD_X (0x0BU)
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#define CTRL_SPINOR_SCK (0x0CU)
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#define CTRL_SPINOR_MOSI (0x0DU)
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#define CTRL_SPINOR_WP_X (0x0EU)
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#define CTRL_SPINOR_MISO (0x0FU)
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#define CTRL_SPINOR_CS_X (0x10U)
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#define CTRL_JTAG_CPU_TMS (0x11U)
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#define CTRL_JTAG_CPU_TCK (0x12U)
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#define CTRL_IIC0_SCL (0x13U)
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#define CTRL_IIC0_SDA (0x14U)
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#define CTRL_AUX0 (0x15U)
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#define CTRL_GPIO_ZQ (0x16U)
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#define CTRL_PWR_VBAT_DET (0x17U)
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#define CTRL_PWR_RSTN (0x18U)
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#define CTRL_PWR_SEQ1 (0x19U)
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#define CTRL_PWR_SEQ2 (0x1AU)
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#define CTRL_PWR_WAKEUP0 (0x1BU)
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#define CTRL_PWR_BUTTON1 (0x1CU)
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#define CTRL_XTAL_XIN (0x1DU)
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#define CTRL_PWR_GPIO0 (0x1EU)
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#define CTRL_PWR_GPIO1 (0x1FU)
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#define CTRL_PWR_GPIO2 (0x20U)
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#define CTRL_SD1_GPIO1 (0x21U)
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#define CTRL_SD1_GPIO0 (0x22U)
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#define CTRL_SD1_D3 (0x23U)
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#define CTRL_SD1_D2 (0x24U)
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#define CTRL_SD1_D1 (0x25U)
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#define CTRL_SD1_D0 (0x26U)
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#define CTRL_SD1_CMD (0x27U)
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#define CTRL_SD1_CLK (0x28U)
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#define CTRL_PWM0_BUCK (0x29U)
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#define CTRL_ADC1 (0x2AU)
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#define CTRL_USB_VBUS_DET (0x2BU)
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#define CTRL_MUX_SPI1_MISO (0x2CU)
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#define CTRL_MUX_SPI1_MOSI (0x2DU)
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#define CTRL_MUX_SPI1_CS (0x2EU)
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#define CTRL_MUX_SPI1_SCK (0x2FU)
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#define CTRL_PAD_ETH_TXP (0x30U)
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#define CTRL_PAD_ETH_TXM (0x31U)
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#define CTRL_PAD_ETH_RXP (0x32U)
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#define CTRL_PAD_ETH_RXM (0x33U)
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#define CTRL_GPIO_RTX (0x34U)
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#define CTRL_PAD_MIPIRX4N (0x35U)
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#define CTRL_PAD_MIPIRX4P (0x36U)
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#define CTRL_PAD_MIPIRX3N (0x37U)
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#define CTRL_PAD_MIPIRX3P (0x38U)
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#define CTRL_PAD_MIPIRX2N (0x39U)
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#define CTRL_PAD_MIPIRX2P (0x3AU)
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#define CTRL_PAD_MIPIRX1N (0x3BU)
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#define CTRL_PAD_MIPIRX1P (0x3CU)
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#define CTRL_PAD_MIPIRX0N (0x3DU)
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#define CTRL_PAD_MIPIRX0P (0x3EU)
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#define CTRL_PAD_MIPI_TXM2 (0x3FU)
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#define CTRL_PAD_MIPI_TXP2 (0x40U)
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#define CTRL_PAD_MIPI_TXM1 (0x41U)
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#define CTRL_PAD_MIPI_TXP1 (0x42U)
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#define CTRL_PAD_MIPI_TXM0 (0x43U)
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#define CTRL_PAD_MIPI_TXP0 (0x44U)
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#define CTRL_PKG_TYPE0 (0x45U)
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#define CTRL_PKG_TYPE1 (0x46U)
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#define CTRL_PKG_TYPE2 (0x47U)
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#define CTRL_PAD_AUD_AINL_MIC (0x48U)
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#define CTRL_PAD_AUD_AINR_MIC (0x49U)
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#define CTRL_PAD_AUD_AOUTL (0x4AU)
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#define CTRL_PAD_AUD_AOUTR (0x4BU)
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/* Function Lists */
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/* PAD SD0_CLK */
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#define FUNC_SD0_CLK_SDIO0_CLK (0x00U)
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#define FUNC_SD0_CLK_IIC1_SDA (0x01U)
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#define FUNC_SD0_CLK_SPI0_SCK (0x02U)
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#define FUNC_SD0_CLK_XGPIOA_7 (0x03U)
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#define FUNC_SD0_CLK_PWM_15 (0x05U)
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#define FUNC_SD0_CLK_EPHY_LNK_LED (0x06U)
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#define FUNC_SD0_CLK_DBG_0 (0x07U)
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/* PAD SD0_CMD */
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#define FUNC_SD0_CMD_SDIO0_CMD (0x00U)
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#define FUNC_SD0_CMD_IIC1_SCL (0x01U)
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#define FUNC_SD0_CMD_SPI0_SDO (0x02U)
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#define FUNC_SD0_CMD_XGPIOA_8 (0x03U)
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#define FUNC_SD0_CMD_PWM_14 (0x05U)
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#define FUNC_SD0_CMD_EPHY_SPD_LED (0x06U)
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#define FUNC_SD0_CMD_DBG_1 (0x07U)
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/* PAD SD0_D0 */
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#define FUNC_SD0_D0_SDIO0_D_0 (0x00U)
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#define FUNC_SD0_D0_CAM_MCLK1 (0x01U)
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#define FUNC_SD0_D0_SPI0_SDI (0x02U)
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#define FUNC_SD0_D0_XGPIOA_9 (0x03U)
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#define FUNC_SD0_D0_UART3_TX (0x04U)
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#define FUNC_SD0_D0_PWM_13 (0x05U)
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#define FUNC_SD0_D0_WG0_D0 (0x06U)
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#define FUNC_SD0_D0_DBG_2 (0x07U)
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/* PAD SD0_D1 */
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#define FUNC_SD0_D1_SDIO0_D_1 (0x00U)
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#define FUNC_SD0_D1_IIC1_SDA (0x01U)
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#define FUNC_SD0_D1_AUX0 (0x02U)
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#define FUNC_SD0_D1_XGPIOA_10 (0x03U)
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#define FUNC_SD0_D1_UART1_TX (0x04U)
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#define FUNC_SD0_D1_PWM_12 (0x05U)
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#define FUNC_SD0_D1_WG0_D1 (0x06U)
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#define FUNC_SD0_D1_DBG_3 (0x07U)
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/* PAD SD0_D2 */
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#define FUNC_SD0_D2_SDIO0_D_2 (0x00U)
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#define FUNC_SD0_D2_IIC1_SCL (0x01U)
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#define FUNC_SD0_D2_AUX1 (0x02U)
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#define FUNC_SD0_D2_XGPIOA_11 (0x03U)
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#define FUNC_SD0_D2_UART1_RX (0x04U)
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#define FUNC_SD0_D2_PWM_11 (0x05U)
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#define FUNC_SD0_D2_WG1_D0 (0x06U)
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#define FUNC_SD0_D2_DBG_4 (0x07U)
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/* PAD SD0_D3 */
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#define FUNC_SD0_D3_SDIO0_D_3 (0x00U)
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#define FUNC_SD0_D3_CAM_MCLK0 (0x01U)
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#define FUNC_SD0_D3_SPI0_CS_X (0x02U)
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#define FUNC_SD0_D3_XGPIOA_12 (0x03U)
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#define FUNC_SD0_D3_UART3_RX (0x04U)
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#define FUNC_SD0_D3_PWM_10 (0x05U)
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#define FUNC_SD0_D3_WG1_D1 (0x06U)
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#define FUNC_SD0_D3_DBG_5 (0x07U)
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/* PAD SD0_CD */
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#define FUNC_SD0_CD_SDIO0_CD (0x00U)
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#define FUNC_SD0_CD_XGPIOA_13 (0x03U)
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/* PAD SD0_PWR_EN */
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#define FUNC_SD0_PWR_EN_SDIO0_PWR_EN (0x00U)
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#define FUNC_SD0_PWR_EN_XGPIOA_14 (0x03U)
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/* PAD SPK_EN */
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#define FUNC_SPK_EN_XGPIOA_15 (0x03U)
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/* PAD UART0_TX */
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#define FUNC_UART0_TX_UART0_TX (0x00U)
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#define FUNC_UART0_TX_CAM_MCLK1 (0x01U)
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#define FUNC_UART0_TX_PWM_4 (0x02U)
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#define FUNC_UART0_TX_XGPIOA_16 (0x03U)
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#define FUNC_UART0_TX_UART1_TX (0x04U)
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#define FUNC_UART0_TX_AUX1 (0x05U)
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#define FUNC_UART0_TX_JTAG_TMS (0x06U)
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#define FUNC_UART0_TX_DBG_6 (0x07U)
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/* PAD UART0_RX */
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#define FUNC_UART0_RX_UART0_RX (0x00U)
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#define FUNC_UART0_RX_CAM_MCLK0 (0x01U)
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#define FUNC_UART0_RX_PWM_5 (0x02U)
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#define FUNC_UART0_RX_XGPIOA_17 (0x03U)
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#define FUNC_UART0_RX_UART1_RX (0x04U)
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#define FUNC_UART0_RX_AUX0 (0x05U)
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#define FUNC_UART0_RX_JTAG_TCK (0x06U)
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#define FUNC_UART0_RX_DBG_7 (0x07U)
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/* PAD SPINOR_HOLD_X */
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#define FUNC_SPINOR_HOLD_X_SPINOR_HOLD_X (0x01U)
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#define FUNC_SPINOR_HOLD_X_SPINAND_HOLD (0x02U)
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#define FUNC_SPINOR_HOLD_X_XGPIOA_26 (0x03U)
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/* PAD SPINOR_SCK */
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#define FUNC_SPINOR_SCK_SPINOR_SCK (0x01U)
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#define FUNC_SPINOR_SCK_SPINAND_CLK (0x02U)
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#define FUNC_SPINOR_SCK_XGPIOA_22 (0x03U)
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/* PAD SPINOR_MOSI */
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#define FUNC_SPINOR_MOSI_SPINOR_MOSI (0x01U)
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#define FUNC_SPINOR_MOSI_SPINAND_MOSI (0x02U)
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#define FUNC_SPINOR_MOSI_XGPIOA_25 (0x03U)
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/* PAD SPINOR_WP_X */
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#define FUNC_SPINOR_WP_X_SPINOR_WP_X (0x01U)
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#define FUNC_SPINOR_WP_X_SPINAND_WP (0x02U)
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#define FUNC_SPINOR_WP_X_XGPIOA_27 (0x03U)
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/* PAD SPINOR_MISO */
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#define FUNC_SPINOR_MISO_SPINOR_MISO (0x01U)
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#define FUNC_SPINOR_MISO_SPINAND_MISO (0x02U)
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#define FUNC_SPINOR_MISO_XGPIOA_23 (0x03U)
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/* PAD SPINOR_CS_X */
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#define FUNC_SPINOR_CS_X_SPINOR_CS_X (0x01U)
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#define FUNC_SPINOR_CS_X_SPINAND_CS (0x02U)
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#define FUNC_SPINOR_CS_X_XGPIOA_24 (0x03U)
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/* PAD JTAG_CPU_TMS */
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#define FUNC_JTAG_CPU_TMS_JTAG_TMS (0x00U)
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#define FUNC_JTAG_CPU_TMS_CAM_MCLK0 (0x01U)
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#define FUNC_JTAG_CPU_TMS_PWM_7 (0x02U)
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#define FUNC_JTAG_CPU_TMS_XGPIOA_19 (0x03U)
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#define FUNC_JTAG_CPU_TMS_UART1_RTS (0x04U)
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#define FUNC_JTAG_CPU_TMS_AUX0 (0x05U)
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#define FUNC_JTAG_CPU_TMS_UART1_TX (0x06U)
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/* PAD JTAG_CPU_TCK */
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#define FUNC_JTAG_CPU_TCK_JTAG_TCK (0x00U)
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#define FUNC_JTAG_CPU_TCK_CAM_MCLK1 (0x01U)
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#define FUNC_JTAG_CPU_TCK_PWM_6 (0x02U)
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#define FUNC_JTAG_CPU_TCK_XGPIOA_18 (0x03U)
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#define FUNC_JTAG_CPU_TCK_UART1_CTS (0x04U)
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#define FUNC_JTAG_CPU_TCK_AUX1 (0x05U)
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#define FUNC_JTAG_CPU_TCK_UART1_RX (0x06U)
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/* PAD IIC0_SCL */
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#define FUNC_IIC0_SCL_CV_SCL0__CR_4WTDI (0x00U)
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#define FUNC_IIC0_SCL_JTAG_TDI (0x00U)
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#define FUNC_IIC0_SCL_UART1_TX (0x01U)
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#define FUNC_IIC0_SCL_UART2_TX (0x02U)
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#define FUNC_IIC0_SCL_XGPIOA_28 (0x03U)
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#define FUNC_IIC0_SCL_IIC0_SCL (0x04U)
|
||||
#define FUNC_IIC0_SCL_WG0_D0 (0x05U)
|
||||
#define FUNC_IIC0_SCL_DBG_10 (0x07U)
|
||||
|
||||
/* PAD IIC0_SDA */
|
||||
#define FUNC_IIC0_SDA_CV_SDA0__CR_4WTDO (0x00U)
|
||||
#define FUNC_IIC0_SDA_JTAG_TDO (0x00U)
|
||||
#define FUNC_IIC0_SDA_UART1_RX (0x01U)
|
||||
#define FUNC_IIC0_SDA_UART2_RX (0x02U)
|
||||
#define FUNC_IIC0_SDA_XGPIOA_29 (0x03U)
|
||||
#define FUNC_IIC0_SDA_IIC0_SDA (0x04U)
|
||||
#define FUNC_IIC0_SDA_WG0_D1 (0x05U)
|
||||
#define FUNC_IIC0_SDA_WG1_D0 (0x06U)
|
||||
#define FUNC_IIC0_SDA_DBG_11 (0x07U)
|
||||
|
||||
/* PAD AUX0 */
|
||||
#define FUNC_AUX0_AUX0 (0x00U)
|
||||
#define FUNC_AUX0_XGPIOA_30 (0x03U)
|
||||
#define FUNC_AUX0_IIS1_MCLK (0x04U)
|
||||
#define FUNC_AUX0_WG1_D1 (0x06U)
|
||||
#define FUNC_AUX0_DBG_12 (0x07U)
|
||||
|
||||
/* PAD GPIO_ZQ */
|
||||
#define FUNC_GPIO_ZQ_PWR_GPIO_24 (0x03U)
|
||||
#define FUNC_GPIO_ZQ_PWM_2 (0x04U)
|
||||
|
||||
/* PAD PWR_VBAT_DET */
|
||||
#define FUNC_PWR_VBAT_DET_PWR_VBAT_DET (0x00U)
|
||||
|
||||
/* PAD PWR_RSTN */
|
||||
#define FUNC_PWR_RSTN_PWR_RSTN (0x00U)
|
||||
|
||||
/* PAD PWR_SEQ1 */
|
||||
#define FUNC_PWR_SEQ1_PWR_SEQ1 (0x00U)
|
||||
#define FUNC_PWR_SEQ1_PWR_GPIO_3 (0x03U)
|
||||
|
||||
/* PAD PWR_SEQ2 */
|
||||
#define FUNC_PWR_SEQ2_PWR_SEQ2 (0x00U)
|
||||
#define FUNC_PWR_SEQ2_PWR_GPIO_4 (0x03U)
|
||||
|
||||
/* PAD PWR_WAKEUP0 */
|
||||
#define FUNC_PWR_WAKEUP0_PWR_WAKEUP0 (0x00U)
|
||||
#define FUNC_PWR_WAKEUP0_PWR_IR0 (0x01U)
|
||||
#define FUNC_PWR_WAKEUP0_PWR_UART0_TX (0x02U)
|
||||
#define FUNC_PWR_WAKEUP0_PWR_GPIO_6 (0x03U)
|
||||
#define FUNC_PWR_WAKEUP0_UART1_TX (0x04U)
|
||||
#define FUNC_PWR_WAKEUP0_IIC4_SCL (0x05U)
|
||||
#define FUNC_PWR_WAKEUP0_EPHY_LNK_LED (0x06U)
|
||||
#define FUNC_PWR_WAKEUP0_WG2_D0 (0x07U)
|
||||
|
||||
/* PAD PWR_BUTTON1 */
|
||||
#define FUNC_PWR_BUTTON1_PWR_BUTTON1 (0x00U)
|
||||
#define FUNC_PWR_BUTTON1_PWR_GPIO_8 (0x03U)
|
||||
#define FUNC_PWR_BUTTON1_UART1_RX (0x04U)
|
||||
#define FUNC_PWR_BUTTON1_IIC4_SDA (0x05U)
|
||||
#define FUNC_PWR_BUTTON1_EPHY_SPD_LED (0x06U)
|
||||
#define FUNC_PWR_BUTTON1_WG2_D1 (0x07U)
|
||||
|
||||
/* PAD XTAL_XIN */
|
||||
#define FUNC_XTAL_XIN_PWR_XTAL_CLKIN (0x00U)
|
||||
|
||||
/* PAD PWR_GPIO0 */
|
||||
#define FUNC_PWR_GPIO0_PWR_GPIO_0 (0x00U)
|
||||
#define FUNC_PWR_GPIO0_UART2_TX (0x01U)
|
||||
#define FUNC_PWR_GPIO0_PWR_UART0_RX (0x02U)
|
||||
#define FUNC_PWR_GPIO0_PWM_8 (0x04U)
|
||||
|
||||
/* PAD PWR_GPIO1 */
|
||||
#define FUNC_PWR_GPIO1_PWR_GPIO_1 (0x00U)
|
||||
#define FUNC_PWR_GPIO1_UART2_RX (0x01U)
|
||||
#define FUNC_PWR_GPIO1_EPHY_LNK_LED (0x03U)
|
||||
#define FUNC_PWR_GPIO1_PWM_9 (0x04U)
|
||||
#define FUNC_PWR_GPIO1_PWR_IIC_SCL (0x05U)
|
||||
#define FUNC_PWR_GPIO1_IIC2_SCL (0x06U)
|
||||
#define FUNC_PWR_GPIO1_IIC0_SDA (0x07U)
|
||||
|
||||
/* PAD PWR_GPIO2 */
|
||||
#define FUNC_PWR_GPIO2_PWR_GPIO_2 (0x00U)
|
||||
#define FUNC_PWR_GPIO2_PWR_SECTICK (0x02U)
|
||||
#define FUNC_PWR_GPIO2_EPHY_SPD_LED (0x03U)
|
||||
#define FUNC_PWR_GPIO2_PWM_10 (0x04U)
|
||||
#define FUNC_PWR_GPIO2_PWR_IIC_SDA (0x05U)
|
||||
#define FUNC_PWR_GPIO2_IIC2_SDA (0x06U)
|
||||
#define FUNC_PWR_GPIO2_IIC0_SCL (0x07U)
|
||||
|
||||
/* PAD SD1_GPIO1 */
|
||||
#define FUNC_SD1_GPIO1_UART4_TX (0x01U)
|
||||
#define FUNC_SD1_GPIO1_PWR_GPIO_26 (0x03U)
|
||||
#define FUNC_SD1_GPIO1_PWM_10 (0x07U)
|
||||
|
||||
/* PAD SD1_GPIO0 */
|
||||
#define FUNC_SD1_GPIO0_UART4_RX (0x01U)
|
||||
#define FUNC_SD1_GPIO0_PWR_GPIO_25 (0x03U)
|
||||
#define FUNC_SD1_GPIO0_PWM_11 (0x07U)
|
||||
|
||||
/* PAD SD1_D3 */
|
||||
#define FUNC_SD1_D3_PWR_SD1_D3 (0x00U)
|
||||
#define FUNC_SD1_D3_SPI2_CS_X (0x01U)
|
||||
#define FUNC_SD1_D3_IIC1_SCL (0x02U)
|
||||
#define FUNC_SD1_D3_PWR_GPIO_18 (0x03U)
|
||||
#define FUNC_SD1_D3_CAM_MCLK0 (0x04U)
|
||||
#define FUNC_SD1_D3_UART3_CTS (0x05U)
|
||||
#define FUNC_SD1_D3_PWR_SPINOR1_CS_X (0x06U)
|
||||
#define FUNC_SD1_D3_PWM_4 (0x07U)
|
||||
|
||||
/* PAD SD1_D2 */
|
||||
#define FUNC_SD1_D2_PWR_SD1_D2 (0x00U)
|
||||
#define FUNC_SD1_D2_IIC1_SCL (0x01U)
|
||||
#define FUNC_SD1_D2_UART2_TX (0x02U)
|
||||
#define FUNC_SD1_D2_PWR_GPIO_19 (0x03U)
|
||||
#define FUNC_SD1_D2_CAM_MCLK0 (0x04U)
|
||||
#define FUNC_SD1_D2_UART3_TX (0x05U)
|
||||
#define FUNC_SD1_D2_PWR_SPINOR1_HOLD_X (0x06U)
|
||||
#define FUNC_SD1_D2_PWM_5 (0x07U)
|
||||
|
||||
/* PAD SD1_D1 */
|
||||
#define FUNC_SD1_D1_PWR_SD1_D1 (0x00U)
|
||||
#define FUNC_SD1_D1_IIC1_SDA (0x01U)
|
||||
#define FUNC_SD1_D1_UART2_RX (0x02U)
|
||||
#define FUNC_SD1_D1_PWR_GPIO_20 (0x03U)
|
||||
#define FUNC_SD1_D1_CAM_MCLK1 (0x04U)
|
||||
#define FUNC_SD1_D1_UART3_RX (0x05U)
|
||||
#define FUNC_SD1_D1_PWR_SPINOR1_WP_X (0x06U)
|
||||
#define FUNC_SD1_D1_PWM_6 (0x07U)
|
||||
|
||||
/* PAD SD1_D0 */
|
||||
#define FUNC_SD1_D0_PWR_SD1_D0 (0x00U)
|
||||
#define FUNC_SD1_D0_SPI2_SDI (0x01U)
|
||||
#define FUNC_SD1_D0_IIC1_SDA (0x02U)
|
||||
#define FUNC_SD1_D0_PWR_GPIO_21 (0x03U)
|
||||
#define FUNC_SD1_D0_CAM_MCLK1 (0x04U)
|
||||
#define FUNC_SD1_D0_UART3_RTS (0x05U)
|
||||
#define FUNC_SD1_D0_PWR_SPINOR1_MISO (0x06U)
|
||||
#define FUNC_SD1_D0_PWM_7 (0x07U)
|
||||
|
||||
/* PAD SD1_CMD */
|
||||
#define FUNC_SD1_CMD_PWR_SD1_CMD (0x00U)
|
||||
#define FUNC_SD1_CMD_SPI2_SDO (0x01U)
|
||||
#define FUNC_SD1_CMD_IIC3_SCL (0x02U)
|
||||
#define FUNC_SD1_CMD_PWR_GPIO_22 (0x03U)
|
||||
#define FUNC_SD1_CMD_CAM_VS0 (0x04U)
|
||||
#define FUNC_SD1_CMD_EPHY_LNK_LED (0x05U)
|
||||
#define FUNC_SD1_CMD_PWR_SPINOR1_MOSI (0x06U)
|
||||
#define FUNC_SD1_CMD_PWM_8 (0x07U)
|
||||
|
||||
/* PAD SD1_CLK */
|
||||
#define FUNC_SD1_CLK_PWR_SD1_CLK (0x00U)
|
||||
#define FUNC_SD1_CLK_SPI2_SCK (0x01U)
|
||||
#define FUNC_SD1_CLK_IIC3_SDA (0x02U)
|
||||
#define FUNC_SD1_CLK_PWR_GPIO_23 (0x03U)
|
||||
#define FUNC_SD1_CLK_CAM_HS0 (0x04U)
|
||||
#define FUNC_SD1_CLK_EPHY_SPD_LED (0x05U)
|
||||
#define FUNC_SD1_CLK_PWR_SPINOR1_SCK (0x06U)
|
||||
#define FUNC_SD1_CLK_PWM_9 (0x07U)
|
||||
|
||||
/* PAD PWM0_BUCK */
|
||||
#define FUNC_PWM0_BUCK_PWM_0 (0x00U)
|
||||
#define FUNC_PWM0_BUCK_XGPIOB_0 (0x03U)
|
||||
|
||||
/* PAD ADC1 */
|
||||
#define FUNC_ADC1_XGPIOB_3 (0x03U)
|
||||
#define FUNC_ADC1_KEY_COL2 (0x04U)
|
||||
#define FUNC_ADC1_PWM_3 (0x06U)
|
||||
|
||||
/* PAD USB_VBUS_DET */
|
||||
#define FUNC_USB_VBUS_DET_USB_VBUS_DET (0x00U)
|
||||
#define FUNC_USB_VBUS_DET_XGPIOB_6 (0x03U)
|
||||
#define FUNC_USB_VBUS_DET_CAM_MCLK0 (0x04U)
|
||||
#define FUNC_USB_VBUS_DET_CAM_MCLK1 (0x05U)
|
||||
#define FUNC_USB_VBUS_DET_PWM_4 (0x06U)
|
||||
|
||||
/* PAD MUX_SPI1_MISO */
|
||||
#define FUNC_MUX_SPI1_MISO_UART3_RTS (0x01U)
|
||||
#define FUNC_MUX_SPI1_MISO_IIC1_SDA (0x02U)
|
||||
#define FUNC_MUX_SPI1_MISO_XGPIOB_8 (0x03U)
|
||||
#define FUNC_MUX_SPI1_MISO_PWM_9 (0x04U)
|
||||
#define FUNC_MUX_SPI1_MISO_KEY_COL1 (0x05U)
|
||||
#define FUNC_MUX_SPI1_MISO_SPI1_SDI (0x06U)
|
||||
#define FUNC_MUX_SPI1_MISO_DBG_14 (0x07U)
|
||||
|
||||
/* PAD MUX_SPI1_MOSI */
|
||||
#define FUNC_MUX_SPI1_MOSI_UART3_RX (0x01U)
|
||||
#define FUNC_MUX_SPI1_MOSI_IIC1_SCL (0x02U)
|
||||
#define FUNC_MUX_SPI1_MOSI_XGPIOB_7 (0x03U)
|
||||
#define FUNC_MUX_SPI1_MOSI_PWM_8 (0x04U)
|
||||
#define FUNC_MUX_SPI1_MOSI_KEY_COL0 (0x05U)
|
||||
#define FUNC_MUX_SPI1_MOSI_SPI1_SDO (0x06U)
|
||||
#define FUNC_MUX_SPI1_MOSI_DBG_13 (0x07U)
|
||||
|
||||
/* PAD MUX_SPI1_CS */
|
||||
#define FUNC_MUX_SPI1_CS_UART3_CTS (0x01U)
|
||||
#define FUNC_MUX_SPI1_CS_CAM_MCLK0 (0x02U)
|
||||
#define FUNC_MUX_SPI1_CS_XGPIOB_10 (0x03U)
|
||||
#define FUNC_MUX_SPI1_CS_PWM_11 (0x04U)
|
||||
#define FUNC_MUX_SPI1_CS_KEY_ROW3 (0x05U)
|
||||
#define FUNC_MUX_SPI1_CS_SPI1_CS_X (0x06U)
|
||||
#define FUNC_MUX_SPI1_CS_DBG_16 (0x07U)
|
||||
|
||||
/* PAD MUX_SPI1_SCK */
|
||||
#define FUNC_MUX_SPI1_SCK_UART3_TX (0x01U)
|
||||
#define FUNC_MUX_SPI1_SCK_CAM_MCLK1 (0x02U)
|
||||
#define FUNC_MUX_SPI1_SCK_XGPIOB_9 (0x03U)
|
||||
#define FUNC_MUX_SPI1_SCK_PWM_10 (0x04U)
|
||||
#define FUNC_MUX_SPI1_SCK_KEY_ROW2 (0x05U)
|
||||
#define FUNC_MUX_SPI1_SCK_SPI1_SCK (0x06U)
|
||||
#define FUNC_MUX_SPI1_SCK_DBG_15 (0x07U)
|
||||
|
||||
/* PAD ETH_TXP */
|
||||
#define FUNC_PAD_ETH_TXP_UART3_RX (0x01U)
|
||||
#define FUNC_PAD_ETH_TXP_IIC1_SCL (0x02U)
|
||||
#define FUNC_PAD_ETH_TXP_XGPIOB_25 (0x03U)
|
||||
#define FUNC_PAD_ETH_TXP_PWM_13 (0x04U)
|
||||
#define FUNC_PAD_ETH_TXP_CAM_MCLK0 (0x05U)
|
||||
#define FUNC_PAD_ETH_TXP_SPI1_SDO (0x06U)
|
||||
#define FUNC_PAD_ETH_TXP_IIS2_LRCK (0x07U)
|
||||
|
||||
/* PAD ETH_TXM */
|
||||
#define FUNC_PAD_ETH_TXM_UART3_RTS (0x01U)
|
||||
#define FUNC_PAD_ETH_TXM_IIC1_SDA (0x02U)
|
||||
#define FUNC_PAD_ETH_TXM_XGPIOB_24 (0x03U)
|
||||
#define FUNC_PAD_ETH_TXM_PWM_12 (0x04U)
|
||||
#define FUNC_PAD_ETH_TXM_CAM_MCLK1 (0x05U)
|
||||
#define FUNC_PAD_ETH_TXM_SPI1_SDI (0x06U)
|
||||
#define FUNC_PAD_ETH_TXM_IIS2_BCLK (0x07U)
|
||||
|
||||
/* PAD ETH_RXP */
|
||||
#define FUNC_PAD_ETH_RXP_UART3_TX (0x01U)
|
||||
#define FUNC_PAD_ETH_RXP_CAM_MCLK1 (0x02U)
|
||||
#define FUNC_PAD_ETH_RXP_XGPIOB_27 (0x03U)
|
||||
#define FUNC_PAD_ETH_RXP_PWM_15 (0x04U)
|
||||
#define FUNC_PAD_ETH_RXP_CAM_HS0 (0x05U)
|
||||
#define FUNC_PAD_ETH_RXP_SPI1_SCK (0x06U)
|
||||
#define FUNC_PAD_ETH_RXP_IIS2_DO (0x07U)
|
||||
|
||||
/* PAD ETH_RXM */
|
||||
#define FUNC_PAD_ETH_RXM_UART3_CTS (0x01U)
|
||||
#define FUNC_PAD_ETH_RXM_CAM_MCLK0 (0x02U)
|
||||
#define FUNC_PAD_ETH_RXM_XGPIOB_26 (0x03U)
|
||||
#define FUNC_PAD_ETH_RXM_PWM_14 (0x04U)
|
||||
#define FUNC_PAD_ETH_RXM_CAM_VS0 (0x05U)
|
||||
#define FUNC_PAD_ETH_RXM_SPI1_CS_X (0x06U)
|
||||
#define FUNC_PAD_ETH_RXM_IIS2_DI (0x07U)
|
||||
|
||||
/* PAD GPIO_RTX */
|
||||
#define FUNC_GPIO_RTX_VI0_D_15 (0x01U)
|
||||
#define FUNC_GPIO_RTX_XGPIOB_23 (0x03U)
|
||||
#define FUNC_GPIO_RTX_PWM_1 (0x04U)
|
||||
#define FUNC_GPIO_RTX_CAM_MCLK0 (0x05U)
|
||||
#define FUNC_GPIO_RTX_IIS2_MCLK (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX4N */
|
||||
#define FUNC_PAD_MIPIRX4N_VI0_CLK (0x01U)
|
||||
#define FUNC_PAD_MIPIRX4N_IIC0_SCL (0x02U)
|
||||
#define FUNC_PAD_MIPIRX4N_XGPIOC_2 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX4N_IIC1_SDA (0x04U)
|
||||
#define FUNC_PAD_MIPIRX4N_CAM_MCLK0 (0x05U)
|
||||
#define FUNC_PAD_MIPIRX4N_KEY_ROW0 (0x06U)
|
||||
#define FUNC_PAD_MIPIRX4N_MUX_SPI1_SCK (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX4P */
|
||||
#define FUNC_PAD_MIPIRX4P_VI0_D_0 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX4P_IIC0_SDA (0x02U)
|
||||
#define FUNC_PAD_MIPIRX4P_XGPIOC_3 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX4P_IIC1_SCL (0x04U)
|
||||
#define FUNC_PAD_MIPIRX4P_CAM_MCLK1 (0x05U)
|
||||
#define FUNC_PAD_MIPIRX4P_KEY_ROW1 (0x06U)
|
||||
#define FUNC_PAD_MIPIRX4P_MUX_SPI1_CS (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX3N */
|
||||
#define FUNC_PAD_MIPIRX3N_VI0_D_1 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX3N_XGPIOC_4 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX3N_CAM_MCLK0 (0x04U)
|
||||
#define FUNC_PAD_MIPIRX3N_MUX_SPI1_MISO (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX3P */
|
||||
#define FUNC_PAD_MIPIRX3P_VI0_D_2 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX3P_XGPIOC_5 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX3P_MUX_SPI1_MOSI (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX2N */
|
||||
#define FUNC_PAD_MIPIRX2N_VI0_D_3 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX2N_XGPIOC_6 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX2N_IIC4_SCL (0x05U)
|
||||
#define FUNC_PAD_MIPIRX2N_DBG_6 (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX2P */
|
||||
#define FUNC_PAD_MIPIRX2P_VI0_D_4 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX2P_XGPIOC_7 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX2P_IIC4_SDA (0x05U)
|
||||
#define FUNC_PAD_MIPIRX2P_DBG_7 (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX1N */
|
||||
#define FUNC_PAD_MIPIRX1N_VI0_D_5 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX1N_XGPIOC_8 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX1N_KEY_ROW3 (0x06U)
|
||||
#define FUNC_PAD_MIPIRX1N_DBG_8 (0x07U)
|
||||
|
||||
/* PAD PAD_MIPIRX1P */
|
||||
#define FUNC_PAD_MIPIRX1P_VI0_D_6 (0x01U)
|
||||
#define FUNC_PAD_MIPIRX1P_XGPIOC_9 (0x03U)
|
||||
#define FUNC_PAD_MIPIRX1P_IIC1_SDA (0x04U)
|
||||
#define FUNC_PAD_MIPIRX1P_KEY_ROW2 (0x06U)
|
||||
#define FUNC_PAD_MIPIRX1P_DBG_9 (0x07U)
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/* PAD PAD_MIPIRX0N */
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#define FUNC_PAD_MIPIRX0N_VI0_D_7 (0x01U)
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#define FUNC_PAD_MIPIRX0N_XGPIOC_10 (0x03U)
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#define FUNC_PAD_MIPIRX0N_IIC1_SCL (0x04U)
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#define FUNC_PAD_MIPIRX0N_CAM_MCLK1 (0x05U)
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#define FUNC_PAD_MIPIRX0N_DBG_10 (0x07U)
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/* PAD PAD_MIPIRX0P */
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#define FUNC_PAD_MIPIRX0P_VI0_D_8 (0x01U)
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#define FUNC_PAD_MIPIRX0P_XGPIOC_11 (0x03U)
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#define FUNC_PAD_MIPIRX0P_CAM_MCLK0 (0x04U)
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#define FUNC_PAD_MIPIRX0P_DBG_11 (0x07U)
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/* PAD PAD_MIPI_TXM2 */
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#define FUNC_PAD_MIPI_TXM2_VI0_D_13 (0x01U)
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#define FUNC_PAD_MIPI_TXM2_IIC0_SDA (0x02U)
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#define FUNC_PAD_MIPI_TXM2_XGPIOC_16 (0x03U)
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#define FUNC_PAD_MIPI_TXM2_IIC1_SDA (0x04U)
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#define FUNC_PAD_MIPI_TXM2_PWM_8 (0x05U)
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#define FUNC_PAD_MIPI_TXM2_SPI0_SCK (0x06U)
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|
||||
/* PAD PAD_MIPI_TXP2 */
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#define FUNC_PAD_MIPI_TXP2_VI0_D_14 (0x01U)
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#define FUNC_PAD_MIPI_TXP2_IIC0_SCL (0x02U)
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#define FUNC_PAD_MIPI_TXP2_XGPIOC_17 (0x03U)
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#define FUNC_PAD_MIPI_TXP2_IIC1_SCL (0x04U)
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#define FUNC_PAD_MIPI_TXP2_PWM_9 (0x05U)
|
||||
#define FUNC_PAD_MIPI_TXP2_SPI0_CS_X (0x06U)
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#define FUNC_PAD_MIPI_TXP2_IIS1_MCLK (0x07U)
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|
||||
/* PAD PAD_MIPI_TXM1 */
|
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#define FUNC_PAD_MIPI_TXM1_SPI3_SDO (0x00U)
|
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#define FUNC_PAD_MIPI_TXM1_VI0_D_11 (0x01U)
|
||||
#define FUNC_PAD_MIPI_TXM1_IIS1_LRCK (0x02U)
|
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#define FUNC_PAD_MIPI_TXM1_XGPIOC_14 (0x03U)
|
||||
#define FUNC_PAD_MIPI_TXM1_IIC2_SDA (0x04U)
|
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#define FUNC_PAD_MIPI_TXM1_PWM_10 (0x05U)
|
||||
#define FUNC_PAD_MIPI_TXM1_SPI0_SDO (0x06U)
|
||||
#define FUNC_PAD_MIPI_TXM1_DBG_14 (0x07U)
|
||||
|
||||
/* PAD PAD_MIPI_TXP1 */
|
||||
#define FUNC_PAD_MIPI_TXP1_SPI3_SDI (0x00U)
|
||||
#define FUNC_PAD_MIPI_TXP1_VI0_D_12 (0x01U)
|
||||
#define FUNC_PAD_MIPI_TXP1_IIS1_DO (0x02U)
|
||||
#define FUNC_PAD_MIPI_TXP1_XGPIOC_15 (0x03U)
|
||||
#define FUNC_PAD_MIPI_TXP1_IIC2_SCL (0x04U)
|
||||
#define FUNC_PAD_MIPI_TXP1_PWM_11 (0x05U)
|
||||
#define FUNC_PAD_MIPI_TXP1_SPI0_SDI (0x06U)
|
||||
#define FUNC_PAD_MIPI_TXP1_DBG_15 (0x07U)
|
||||
|
||||
/* PAD PAD_MIPI_TXM0 */
|
||||
#define FUNC_PAD_MIPI_TXM0_SPI3_SCK (0x00U)
|
||||
#define FUNC_PAD_MIPI_TXM0_VI0_D_9 (0x01U)
|
||||
#define FUNC_PAD_MIPI_TXM0_IIS1_DI (0x02U)
|
||||
#define FUNC_PAD_MIPI_TXM0_XGPIOC_12 (0x03U)
|
||||
#define FUNC_PAD_MIPI_TXM0_CAM_MCLK1 (0x04U)
|
||||
#define FUNC_PAD_MIPI_TXM0_PWM_14 (0x05U)
|
||||
#define FUNC_PAD_MIPI_TXM0_CAM_VS0 (0x06U)
|
||||
#define FUNC_PAD_MIPI_TXM0_DBG_12 (0x07U)
|
||||
|
||||
/* PAD PAD_MIPI_TXP0 */
|
||||
#define FUNC_PAD_MIPI_TXP0_SPI3_CS_X (0x00U)
|
||||
#define FUNC_PAD_MIPI_TXP0_VI0_D_10 (0x01U)
|
||||
#define FUNC_PAD_MIPI_TXP0_IIS1_BCLK (0x02U)
|
||||
#define FUNC_PAD_MIPI_TXP0_XGPIOC_13 (0x03U)
|
||||
#define FUNC_PAD_MIPI_TXP0_CAM_MCLK0 (0x04U)
|
||||
#define FUNC_PAD_MIPI_TXP0_PWM_15 (0x05U)
|
||||
#define FUNC_PAD_MIPI_TXP0_CAM_HS0 (0x06U)
|
||||
#define FUNC_PAD_MIPI_TXP0_DBG_13 (0x07U)
|
||||
|
||||
/* PAD PKG_TYPE0 */
|
||||
#define FUNC_PKG_TYPE0_PKG_TYPE0 (0x00U)
|
||||
|
||||
/* PAD PKG_TYPE1 */
|
||||
#define FUNC_PKG_TYPE1_PKG_TYPE1 (0x00U)
|
||||
|
||||
/* PAD PKG_TYPE2 */
|
||||
#define FUNC_PKG_TYPE2_PKG_TYPE2 (0x00U)
|
||||
|
||||
/* PAD PAD_AUD_AINL_MIC */
|
||||
#define FUNC_PAD_AUD_AINL_MIC_XGPIOC_23 (0x03U)
|
||||
#define FUNC_PAD_AUD_AINL_MIC_IIS1_BCLK (0x04U)
|
||||
#define FUNC_PAD_AUD_AINL_MIC_IIS2_BCLK (0x05U)
|
||||
|
||||
/* PAD PAD_AUD_AINR_MIC */
|
||||
#define FUNC_PAD_AUD_AINR_MIC_XGPIOC_22 (0x03U)
|
||||
#define FUNC_PAD_AUD_AINR_MIC_IIS1_DO (0x04U)
|
||||
#define FUNC_PAD_AUD_AINR_MIC_IIS2_DI (0x05U)
|
||||
#define FUNC_PAD_AUD_AINR_MIC_IIS1_DI (0x06U)
|
||||
|
||||
/* PAD PAD_AUD_AOUTL */
|
||||
#define FUNC_PAD_AUD_AOUTL_XGPIOC_25 (0x03U)
|
||||
#define FUNC_PAD_AUD_AOUTL_IIS1_LRCK (0x04U)
|
||||
#define FUNC_PAD_AUD_AOUTL_IIS2_LRCK (0x05U)
|
||||
|
||||
/* PAD PAD_AUD_AOUTR */
|
||||
#define FUNC_PAD_AUD_AOUTR_XGPIOC_24 (0x03U)
|
||||
#define FUNC_PAD_AUD_AOUTR_IIS1_DI (0x04U)
|
||||
#define FUNC_PAD_AUD_AOUTR_IIS2_DO (0x05U)
|
||||
#define FUNC_PAD_AUD_AOUTR_IIS1_DO (0x06U)
|
||||
|
||||
#endif /* DT_CV1800B_PINCTRL_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue