board: rockchip: Add Pine64 SOQuartz on Blade
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz CM4-compatible compute module. It features PoE, an M.2 slot, an SD card slot, HDMI, USB, serial and ethernet. Features tested with a SOQuartz 4GB v1.1 2022-07-11: - SD-card boot - eMMC boot - PCIe/NVMe - USB host Device tree is imported from linux v6.4. Co-developed-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
Kever Yang
parent
651492bfb2
commit
d0026e5908
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@ -174,6 +174,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3566-quartz64-a.dtb \
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rk3566-quartz64-b.dtb \
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rk3566-radxa-cm3-io.dtb \
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rk3566-soquartz-blade.dtb \
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rk3566-soquartz-model-a.dtb \
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rk3568-evb.dtb \
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rk3568-nanopi-r5c.dtb \
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3
arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
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3
arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
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@ -0,0 +1,3 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include "rk3566-soquartz-u-boot.dtsi"
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194
arch/arm/dts/rk3566-soquartz-blade.dts
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194
arch/arm/dts/rk3566-soquartz-blade.dts
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@ -0,0 +1,194 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include "rk3566-soquartz.dtsi"
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/ {
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model = "PINE64 RK3566 SOQuartz on Blade carrier board";
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compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
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/* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
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vcc3v0_sd: vcc3v0-sd-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v0_sd";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc3v3_sys>;
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};
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/* labeled VCC_SSD in schematic */
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vcc3v3_pcie_p: vcc3v3-pcie-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie_p";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vbus>;
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};
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vcc5v_dcin: vcc5v-dcin-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v_dcin";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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&combphy2 {
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phy-supply = <&vcc3v3_sys>;
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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};
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/*
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* i2c1 is exposed on CM1 / Module1A
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* pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
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* pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
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*/
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&i2c1 {
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status = "okay";
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};
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/*
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* i2c2 is exposed on CM1 / Module1A - to PI40
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* pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
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* pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
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*/
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&i2c2 {
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status = "disabled";
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};
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/*
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* i2c3 is exposed on CM1 / Module1A - to PI40
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* pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
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* pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
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*/
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&i2c3 {
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status = "disabled";
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};
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/*
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* i2c4 is exposed on CM2 / Module1B - to PI40
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* pin 45 - GPIO24 - i2c4_scl_m1
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* pin 47 - GPIO23 - i2c4_sda_m1
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*/
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&i2c4 {
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status = "disabled";
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};
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/*
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* i2s1_8ch is exposed on CM1 / Module1A - to PI40
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* pin 24 - GPIO26 - i2s1_sdi1_m1
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* pin 25 - GPIO21 - i2s1_sdo0_m1
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* pin 26 - GPIO19 - i2s1_lrck_tx_m1
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* pin 27 - GPIO20 - i2s1_sdi0_m1
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* pin 29 - GPIO16 - i2s1_sdi3_m1
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* pin 30 - GPIO6 - i2s1_sdi2_m1
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* pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
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* pin 41 - GPIO25 - i2s1_sdo2_m1
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* pin 49 - GPIO18 - i2s1_sclk_tx_m1
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* pin 50 - GPIO17 - i2s1_mclk_m1
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* pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
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*/
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&i2s1_8ch {
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status = "disabled";
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};
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&led_diy {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_DISK_ACTIVITY;
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linux,default-trigger = "disk-activity";
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status = "okay";
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};
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&led_work {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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linux,default-trigger = "heartbeat";
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status = "okay";
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};
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&pcie2x1 {
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vpcie3v3-supply = <&vcc3v3_pcie_p>;
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status = "okay";
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};
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&rgmii_phy1 {
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status = "okay";
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};
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/*
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* saradc is exposed on CM1 / Module1A - to J2
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* pin 94 - AIN1 - saradc_vin3
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* pin 96 - AIN0 - saradc_vin2
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*/
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&saradc {
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status = "disabled";
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};
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&sdmmc0 {
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vmmc-supply = <&vcc3v0_sd>;
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status = "okay";
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};
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/*
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* spi3 is exposed on CM1 / Module1A - to PI40
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* pin 37 - GPIO7 - spi3_cs1_m0
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* pin 38 - GPIO11 - spi3_clk_m0
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* pin 39 - GPIO8 - spi3_cs0_m0
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* pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
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* pin 44 - GPIO10 - spi3_mosi_m0
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*/
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&spi3 {
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status = "disabled";
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};
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/*
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* uart2 is exposed on CM1 / Module1A - to PI40
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* pin 51 - GPIO15 - uart2_rx_m0
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* pin 55 - GPIO14 - uart2_tx_m0
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*/
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&uart2 {
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status = "okay";
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};
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/*
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* uart7 is exposed on CM1 / Module1A - to PI40
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* pin 46 - GPIO22 - uart7_tx_m2
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* pin 47 - GPIO23 - uart7_rx_m2
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*/
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&uart7 {
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status = "okay";
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};
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&usb2phy0 {
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status = "okay";
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};
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&usb2phy0_otg {
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phy-supply = <&vbus>;
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status = "okay";
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};
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&usb_host0_xhci {
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status = "okay";
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};
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&vbus {
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vin-supply = <&vcc5v_dcin>;
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};
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@ -6,6 +6,7 @@ F: board/pine64/quartz64_rk3566/
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F: include/configs/quartz64_rk3566.h
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F: configs/quartz64-a-rk3566_defconfig
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F: configs/quartz64-b-rk3566_defconfig
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F: configs/soquartz-blade-rk3566_defconfig
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F: configs/soquartz-model-a-rk3566_defconfig
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F: arch/arm/dts/rk3566-quartz64-a.dts
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F: arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi
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@ -13,5 +14,7 @@ F: arch/arm/dts/rk3566-quartz64-b.dts
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F: arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi
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F: arch/arm/dts/rk3566-soquartz.dtsi
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F: arch/arm/dts/rk3566-soquartz-u-boot.dtsi
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F: arch/arm/dts/rk3566-soquartz-blade.dts
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F: arch/arm/dts/rk3566-soquartz-blade-u-boot.dtsi
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F: arch/arm/dts/rk3566-soquartz-model-a.dts
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F: arch/arm/dts/rk3566-soquartz-model-a-u-boot.dtsi
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90
configs/soquartz-blade-rk3566_defconfig
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90
configs/soquartz-blade-rk3566_defconfig
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@ -0,0 +1,90 @@
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00a00000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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CONFIG_DEFAULT_DEVICE_TREE="rk3566-soquartz-blade"
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CONFIG_ROCKCHIP_RK3568=y
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CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK_R_ADDR=0x600000
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CONFIG_TARGET_QUARTZ64_RK3566=y
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CONFIG_SPL_STACK=0x400000
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CONFIG_DEBUG_UART_BASE=0xFE660000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0xc00800
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CONFIG_PCI=y
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CONFIG_DEBUG_UART=y
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CONFIG_AHCI=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x4000000
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CONFIG_SPL_BSS_MAX_SIZE=0x4000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_ATF=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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# CONFIG_SPL_DOS_PARTITION is not set
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_SCSI_AHCI=y
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CONFIG_AHCI_PCI=y
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CONFIG_SPL_CLK=y
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CONFIG_GPIO_HOG=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_SUPPORT_EMMC_RPMB=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_NVME_PCI=y
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CONFIG_PCIE_DW_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_SPL_RAM=y
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CONFIG_SCSI=y
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CONFIG_DM_SCSI=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_ERRNO_STR=y
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@ -98,6 +98,7 @@ List of mainline supported Rockchip boards:
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- Hardkernel ODROID-M1 (odroid-m1-rk3568)
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- Pine64 Quartz64-A Board (quartz64-a-rk3566_defconfig)
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- Pine64 Quartz64-B Board (quartz64-b-rk3566_defconfig)
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- Pine64 SOQuartz on Blade (soquartz-blade-rk3566_defconfig)
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- Pine64 SOQuartz on Model A (soquartz-model-a-rk3566_defconfig)
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* rk3588
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