imx8mm-phg: Add board support
Add the board support for the i.MX8MM Cloos PHG board. This board uses a imx8mm-tqma8mqml SoM from TQ-Group. imx8mm-phg.dts and imx8mm-tqma8mqml.dtsi are taken directly from Linux 6.2-rc3. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
6e91c06a73
commit
d12618b927
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@ -960,6 +960,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-kontron-bl.dtb \
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imx8mm-kontron-bl-osm-s.dtb \
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imx8mm-mx8menlo.dtb \
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imx8mm-phg.dtb \
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imx8mm-venice.dtb \
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imx8mm-venice-gw71xx-0x.dtb \
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imx8mm-venice-gw72xx-0x.dtb \
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137
arch/arm/dts/imx8mm-phg-u-boot.dtsi
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137
arch/arm/dts/imx8mm-phg-u-boot.dtsi
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@ -0,0 +1,137 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include "imx8mm-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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u-boot,dm-spl;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&aips4 {
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u-boot,dm-spl;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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};
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&pinctrl_reg_usdhc2_vmmc {
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u-boot,dm-spl;
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};
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&pinctrl_uart2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2_gpio {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc3 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&uart2 {
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u-boot,dm-spl;
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};
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&usbmisc1 {
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u-boot,dm-spl;
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};
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&usbphynop1 {
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u-boot,dm-spl;
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};
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&usbotg1 {
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u-boot,dm-spl;
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};
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&usdhc1 {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
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};
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&usdhc3 {
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u-boot,dm-spl;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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/*
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* prevents voltage switch warn: driver will switch even at
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* fixed voltage
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*/
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/delete-property/ vmmc-supply;
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/delete-property/ vqmmc-supply;
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assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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u-boot,dm-spl;
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};
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&pinctrl_i2c1 {
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u-boot,dm-spl;
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};
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&pinctrl_pmic {
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u-boot,dm-spl;
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};
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&wdog1 {
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u-boot,dm-spl;
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};
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266
arch/arm/dts/imx8mm-phg.dts
Normal file
266
arch/arm/dts/imx8mm-phg.dts
Normal file
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@ -0,0 +1,266 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Fabio Estevam <festevam@denx.de>
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*/
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/dts-v1/;
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#include "imx8mm-tqma8mqml.dtsi"
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/ {
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model = "Cloos i.MX8MM PHG board";
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compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
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aliases {
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mmc0 = &usdhc3;
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mmc1 = &usdhc2;
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};
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chosen {
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stdout-path = &uart2;
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};
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beeper {
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compatible = "gpio-beeper";
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pinctrl-0 = <&pinctrl_beeper>;
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gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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led-0 {
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label = "status1";
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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led-1 {
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label = "status2";
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gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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led-2 {
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label = "status3";
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gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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};
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led-3 {
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label = "run";
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gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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led-4 {
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label = "powerled";
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gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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};
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};
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&usbphynop1 {
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power-domains = <&pgc_otg1>;
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};
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&usbphynop2 {
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power-domains = <&pgc_otg2>;
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};
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&usbotg1 {
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dr_mode = "host";
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vbus-supply = <®_usb_otg_vbus>;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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disable-wp;
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no-mmc;
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no-sdio;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_beeper: beepergrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
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MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
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MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
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MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14
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MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10
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>;
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};
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pinctrl_gpio_led: gpioledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
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MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
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MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
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MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
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>;
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};
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};
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341
arch/arm/dts/imx8mm-tqma8mqml.dtsi
Normal file
341
arch/arm/dts/imx8mm-tqma8mqml.dtsi
Normal file
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@ -0,0 +1,341 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright 2020-2021 TQ-Systems GmbH
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*/
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#include <dt-bindings/phy/phy-imx8-pcie.h>
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#include "imx8mm.dtsi"
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/ {
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model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
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compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
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memory@40000000 {
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device_type = "memory";
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/* our minimum RAM config will be 1024 MiB */
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reg = <0x00000000 0x40000000 0 0x40000000>;
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};
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/* e-MMC IO, needed for HS modes */
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reg_vcc1v8: regulator-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "TQMA8MXML_VCC1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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/* identical to buck4_reg, but should never change */
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reg_vcc3v3: regulator-vcc3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "TQMA8MXML_VCC3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* global autoconfigured region for contiguous allocations */
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
/* 640 MiB */
|
||||
size = <0 0x28000000>;
|
||||
/* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
|
||||
alloc-ranges = <0 0x40000000 0 0x78000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <84000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpu_2d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu_3d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
sensor0: temperature-sensor-eeprom@1b {
|
||||
compatible = "nxp,se97", "jedec,jc-42.4-temp";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
|
||||
pca9450: pmic@25 {
|
||||
compatible = "nxp,pca9450a";
|
||||
reg = <0x25>;
|
||||
|
||||
/* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
/* V_0V85_SOC: 0.85 */
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
/* VDD_ARM */
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
/* V_0V85_GPU / DRAM / VPU */
|
||||
buck3_reg: BUCK3 {
|
||||
regulator-name = "BUCK3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
/* VCC3V3 -> VMMC, ... must not be changed */
|
||||
buck4_reg: BUCK4 {
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
|
||||
buck5_reg: BUCK5 {
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V1 -> RAM, ... must not be changed */
|
||||
buck6_reg: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V8_SNVS */
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_0V8_SNVS */
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_1V8_ANA */
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* V_0V9_MIPI */
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* VCC SD IO - switched using SD2 VSELECT */
|
||||
ldo5_reg: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
pcf85063: rtc@51 {
|
||||
compatible = "nxp,pcf85063a";
|
||||
reg = <0x51>;
|
||||
quartz-load-femtofarads = <7000>;
|
||||
};
|
||||
|
||||
eeprom1: eeprom@53 {
|
||||
compatible = "nxp,se97b", "atmel,24c02";
|
||||
read-only;
|
||||
reg = <0x53>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom0: eeprom@57 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x57>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
vmmc-supply = <®_vcc3v3>;
|
||||
vqmmc-supply = <®_vcc1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Attention:
|
||||
* wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
|
||||
* without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
|
||||
*/
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_flexspi: flexspigrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>,
|
||||
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
|
||||
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>,
|
||||
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>,
|
||||
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>,
|
||||
<MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>,
|
||||
<MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1gpiogrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>,
|
||||
<MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
|
||||
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
|
||||
/* option USDHC3_RESET_B not defined, only in RM */
|
||||
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
|
||||
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
|
||||
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
|
||||
/* option USDHC3_RESET_B not defined, only in RM */
|
||||
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
|
||||
<MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
|
||||
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
|
||||
<MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
|
||||
/* option USDHC3_RESET_B not defined, only in RM */
|
||||
<MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
|
||||
};
|
||||
};
|
||||
|
|
@ -94,6 +94,13 @@ config TARGET_IMX8MM_MX8MENLO
|
|||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MM_PHG
|
||||
bool "i.MX8MM PHG board"
|
||||
select BINMAN
|
||||
select IMX8MM
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MM_VENICE
|
||||
bool "Support Gateworks Venice iMX8M Mini module"
|
||||
select BINMAN
|
||||
|
|
@ -305,6 +312,7 @@ source "board/advantech/imx8mp_rsb3720a1/Kconfig"
|
|||
source "board/beacon/imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mn/Kconfig"
|
||||
source "board/bsh/imx8mn_smm_s2/Kconfig"
|
||||
source "board/cloos/imx8mm_phg/Kconfig"
|
||||
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
|
||||
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
|
||||
source "board/dhelectronics/dh_imx8mp/Kconfig"
|
||||
|
|
|
|||
15
board/cloos/imx8mm_phg/Kconfig
Normal file
15
board/cloos/imx8mm_phg/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_IMX8MM_PHG
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8mm_phg"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "cloos"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8mm_phg"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg"
|
||||
|
||||
endif
|
||||
6
board/cloos/imx8mm_phg/MAINTAINERS
Normal file
6
board/cloos/imx8mm_phg/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
i.MX8MM PHG BOARD
|
||||
M: Fabio Estevam <festevam@denx.de>
|
||||
S: Maintained
|
||||
F: board/cloos/imx8mm_phg/
|
||||
F: include/configs/imx8mm_phg.h
|
||||
F: configs/imx8mm_phg_defconfig
|
||||
12
board/cloos/imx8mm_phg/Makefile
Normal file
12
board/cloos/imx8mm_phg/Makefile
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright 2018 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += imx8mm_phg.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
50
board/cloos/imx8mm_phg/imx8mm_phg.c
Normal file
50
board/cloos/imx8mm_phg/imx8mm_phg.c
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <init.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Use 125MHz anatop REF_CLK1 for ENET1, not from external */
|
||||
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
setup_fec();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
|
||||
env_set("board_name", "PHG");
|
||||
env_set("board_rev", "iMX8MM");
|
||||
}
|
||||
|
||||
if (is_usb_boot()) {
|
||||
env_set("bootcmd", "ums 0 mmc 0");
|
||||
env_set("bootdelay", "0");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
8
board/cloos/imx8mm_phg/imx8mm_phg.env
Normal file
8
board/cloos/imx8mm_phg/imx8mm_phg.env
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
fdt_addr_r=0x43000000
|
||||
mmcdev=0
|
||||
fdtfile=imx8mm-phg.dtb
|
||||
mmcargs=setenv bootargs console=ttymxc1,115200 root=/dev/mmcblk${mmcdev}p${mmcpart} rw rootwait quiet
|
||||
bootcmd=env exists mmcpart || setenv mmcpart 1; run mmcargs; \
|
||||
mmc dev ${mmcdev}; load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/Image; \
|
||||
load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} boot/${fdtfile}; \
|
||||
booti ${loadaddr} - ${fdt_addr_r}
|
||||
8
board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg
Normal file
8
board/cloos/imx8mm_phg/imximage-8mm-lpddr4.cfg
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
|
||||
BOOT_FROM sd
|
||||
LOADER u-boot-spl-ddr.bin 0x7E1000
|
||||
1846
board/cloos/imx8mm_phg/lpddr4_timing.c
Normal file
1846
board/cloos/imx8mm_phg/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load Diff
147
board/cloos/imx8mm_phg/spl.c
Normal file
147
board/cloos/imx8mm_phg/spl.c
Normal file
|
|
@ -0,0 +1,147 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <cpu_func.h>
|
||||
#include <hang.h>
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <spl.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx8mm_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/device-internal.h>
|
||||
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
switch (boot_dev_spl) {
|
||||
case USB_BOOT:
|
||||
return BOOT_DEVICE_BOARD;
|
||||
case SD2_BOOT:
|
||||
case MMC2_BOOT:
|
||||
return BOOT_DEVICE_MMC1;
|
||||
case SD3_BOOT:
|
||||
case MMC3_BOOT:
|
||||
return BOOT_DEVICE_MMC2;
|
||||
default:
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
if (is_usb_boot())
|
||||
puts("USB Boot\n");
|
||||
else
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = pmic_get("pmic@25", &dev);
|
||||
if (ret == -ENODEV) {
|
||||
puts("No pmic\n");
|
||||
return 0;
|
||||
}
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
||||
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/* Buck 1 DVS control through PMIC_STBY_REQ */
|
||||
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
|
||||
|
||||
/* Set DVS1 to 0.8V for suspend */
|
||||
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
|
||||
|
||||
/* increase VDD_DRAM to 0.95V for 3GHz DDR */
|
||||
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
|
||||
|
||||
/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
|
||||
pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
|
||||
|
||||
/* set VDD_SNVS_0V8 from default 0.85V */
|
||||
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
|
||||
|
||||
/* set WDOG_B_CFG to cold reset */
|
||||
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(1);
|
||||
|
||||
timer_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
debug("spl_early_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_CLK,
|
||||
"clock-controller@30380000",
|
||||
&dev);
|
||||
if (ret < 0) {
|
||||
printf("Failed to find clock node. Check device tree\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
120
configs/imx8mm_phg_defconfig
Normal file
120
configs/imx8mm_phg_defconfig
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_ENV_OFFSET=0x200000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phg"
|
||||
CONFIG_SPL_TEXT_BASE=0x7E1000
|
||||
CONFIG_TARGET_IMX8MM_PHG=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x204000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x910000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0x920000
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_USB_HOST=y
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_USB_SDP_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_MD5SUM=y
|
||||
CONFIG_MD5SUM_VERIFY=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB_SDP=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_SPL_CLK_IMX8MM=y
|
||||
CONFIG_CLK_IMX8MM=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SPL_PHY=y
|
||||
CONFIG_SPL_NOP_PHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_SPL_DM_PMIC_PCA9450=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_MXC_USB_OTG_HACTIVE=y
|
||||
# CONFIG_USB_STORAGE is not set
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_SDP_LOADADDR=0x40400000
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
55
doc/board/cloos/imx8mm_phg.rst
Normal file
55
doc/board/cloos/imx8mm_phg.rst
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Cloos i.MX8MM PHG board
|
||||
=======================
|
||||
|
||||
U-Boot for the Cloos i.MX8MM PHG board
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Get and Build the ARM Trusted firmware
|
||||
- Get the DDR firmware
|
||||
- Build U-Boot
|
||||
- Flash U-Boot into the eMMC
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
--------------------------------------
|
||||
|
||||
Note: builddir is U-Boot build directory (source directory for in-tree builds)
|
||||
Get ATF from: https://github.com/nxp-imx/imx-atf
|
||||
branch: lf_v2.6
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ make PLAT=imx8mm bl31
|
||||
$ cp build/imx8mm/release/bl31.bin $(builddir)
|
||||
|
||||
Get the DDR firmware
|
||||
--------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
|
||||
$ chmod +x firmware-imx-8.9.bin
|
||||
$ ./firmware-imx-8.9
|
||||
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ export CROSS_COMPILE=aarch64-poky-linux-
|
||||
$ make imx8mm_phg_defconfig
|
||||
$ make
|
||||
|
||||
Flash U-Boot into the eMMC
|
||||
--------------------------
|
||||
|
||||
Program flash.bin to the eMMC at offset 33KB:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ ums 0 mmc 0
|
||||
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=33; sync
|
||||
9
doc/board/cloos/index.rst
Normal file
9
doc/board/cloos/index.rst
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Cloos
|
||||
=====
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
imx8mm_phg
|
||||
|
|
@ -16,6 +16,7 @@ Board-specific doc
|
|||
atmel/index
|
||||
broadcom/index
|
||||
bsh/index
|
||||
cloos/index
|
||||
congatec/index
|
||||
coreboot/index
|
||||
emulation/index
|
||||
|
|
|
|||
41
include/configs/imx8mm_phg.h
Normal file
41
include/configs/imx8mm_phg.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MM_PHG_H
|
||||
#define __IMX8MM_PHG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define CFG_SYS_UBOOT_BASE \
|
||||
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
||||
#define CFG_MALLOC_F_ADDR 0x930000
|
||||
#endif
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 2) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CFG_EXTRA_ENV_SETTINGS BOOTENV
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x200000
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user