Merge tag 'u-boot-rockchip-20231007' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Add Board: rk3568 Bananapi R2Pro; - Update pcie bifurcation support; - dwc_eth_qos controller support for rk3568 and rk3588; - Compressed binary support for U-Boot on rockchip platform; - dts and config updates for different board and soc; [ trini: Fix conflict on include/spl.h ] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
commit
d9bb6d779b
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@ -177,6 +177,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
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rk3566-soquartz-blade.dtb \
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rk3566-soquartz-cm4.dtb \
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rk3566-soquartz-model-a.dtb \
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rk3568-bpi-r2-pro.dtb \
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rk3568-evb.dtb \
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rk3568-lubancat-2.dtb \
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rk3568-nanopi-r5c.dtb \
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19
arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
Normal file
19
arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
Normal file
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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#include "rk356x-u-boot.dtsi"
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/ {
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chosen {
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stdout-path = &uart2;
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};
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};
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&uart2 {
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clock-frequency = <24000000>;
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bootph-pre-ram;
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status = "okay";
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};
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852
arch/arm/dts/rk3568-bpi-r2-pro.dts
Normal file
852
arch/arm/dts/rk3568-bpi-r2-pro.dts
Normal file
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@ -0,0 +1,852 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Author: Frank Wunderlich <frank-w@public-files.de>
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*
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,vop2.h>
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#include "rk3568.dtsi"
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/ {
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model = "Bananapi-R2 Pro (RK3568) DDR4 Board";
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compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568";
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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mmc0 = &sdmmc0;
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mmc1 = &sdhci;
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};
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chosen: chosen {
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stdout-path = "serial2:1500000n8";
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&blue_led_pin &green_led_pin>;
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blue_led: led-0 {
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color = <LED_COLOR_ID_BLUE>;
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default-state = "off";
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function = LED_FUNCTION_STATUS;
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gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
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};
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green_led: led-1 {
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color = <LED_COLOR_ID_GREEN>;
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default-state = "on";
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
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};
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};
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dc_12v: dc-12v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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hdmi-con {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi_out_con>;
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};
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};
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};
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ir-receiver {
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compatible = "gpio-ir-receiver";
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gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&ir_receiver_pin>;
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};
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vcc3v3_sys: vcc3v3-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_sys: vcc5v0-sys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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pcie30_avdd0v9: pcie30-avdd0v9-regulator {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd0v9";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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vin-supply = <&vcc3v3_sys>;
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};
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pcie30_avdd1v8: pcie30-avdd1v8-regulator {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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/* pi6c pcie clock generator feeds both ports */
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vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <200000>;
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vin-supply = <&vcc5v0_sys>;
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};
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/* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
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vcc3v3_minipcie: vcc3v3-minipcie-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_minipcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&minipcie_enable_h>;
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startup-delay-us = <50000>;
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vin-supply = <&vcc3v3_pi6c_05>;
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};
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/* actually fed by vcc3v3_sys, dependent on pi6c clock generator */
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vcc3v3_ngff: vcc3v3-ngff-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_ngff";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&ngffpcie_enable_h>;
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startup-delay-us = <50000>;
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vin-supply = <&vcc3v3_pi6c_05>;
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};
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vcc5v0_usb: vcc5v0-usb-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_usb_host: vcc5v0-usb-host-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_usb_host_en>;
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regulator-name = "vcc5v0_usb_host";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usb>;
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};
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vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_usb_otg_en>;
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regulator-name = "vcc5v0_usb_otg";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usb>;
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};
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};
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&combphy0 {
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/* used for USB3 */
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status = "okay";
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};
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&combphy1 {
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/* used for USB3 */
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status = "okay";
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};
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&combphy2 {
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/* used for SATA */
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status = "okay";
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};
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&gmac0 {
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assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
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clock_in_out = "input";
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_bus>;
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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tx_delay = <0x4f>;
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rx_delay = <0x0f>;
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status = "okay";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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&gmac1 {
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
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clock_in_out = "output";
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phy-handle = <&rgmii_phy1>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus>;
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snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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tx_delay = <0x3c>;
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rx_delay = <0x2f>;
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status = "okay";
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};
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&gpu {
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mali-supply = <&vdd_gpu>;
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status = "okay";
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};
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&hdmi {
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avdd-0v9-supply = <&vdda0v9_image>;
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avdd-1v8-supply = <&vcca1v8_image>;
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status = "okay";
|
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};
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|
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&hdmi_in {
|
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hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "rtcic_32kout";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
/* pin 3 (SDA) + 4 (SCL) of header con2 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
/* hdmi sound */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@0 {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
phy-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
/* M.2 slot */
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_reset_h>;
|
||||
reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
/* mPCIe slot */
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_minipcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
blue_led_pin: blue-led-pin {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
green_led_pin: green-led-pin {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
ir-receiver {
|
||||
ir_receiver_pin: ir-receiver-pin {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
minipcie_enable_h: minipcie-enable-h {
|
||||
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
|
||||
};
|
||||
|
||||
minipcie_reset_h: minipcie-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
|
||||
};
|
||||
|
||||
ngffpcie_reset_h: ngffpcie-reset-h {
|
||||
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins =
|
||||
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_3v3>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm8 {
|
||||
/* fan 5v - gnd - pwm */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm10 {
|
||||
/* pin 7 of header con2 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm11 {
|
||||
/* pin 15 of header con2 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm12 {
|
||||
/* pin 21 of header con2 */
|
||||
/* shared with uart9 + spi3 */
|
||||
pinctrl-0 = <&pwm12m1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm13 {
|
||||
/* pin 24 of header con2 */
|
||||
/* shared with uart9 */
|
||||
pinctrl-0 = <&pwm13m1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm14 {
|
||||
/* pin 23 of header con2 */
|
||||
/* shared with spi3 */
|
||||
pinctrl-0 = <&pwm14m1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm15 {
|
||||
/* pin 19 of header con2 */
|
||||
/* shared with spi3 */
|
||||
pinctrl-0 = <&pwm15m1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
/* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */
|
||||
/* shared with pwm12/14/15 and uart9 */
|
||||
pinctrl-0 = <&spi3m1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
/* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
/* debug-uart */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
/* pin 11 (TX) + 13 (RX) of header con2 */
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
/* pin 21 (TX) + 24 (RX) of header con2 */
|
||||
/* shared with pwm13 and pwm12/spi3 */
|
||||
pinctrl-0 = <&uart9m1_xfer>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
/* USB for PCIe/M2 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
14
arch/arm/dts/rk3568-generic-u-boot.dtsi
Normal file
14
arch/arm/dts/rk3568-generic-u-boot.dtsi
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include "rk356x-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
bootph-pre-ram;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
38
arch/arm/dts/rk3568-generic.dts
Normal file
38
arch/arm/dts/rk3568-generic.dts
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Minimal generic DT for RK3566/RK3568 with eMMC and SD-card enabled
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk356x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Generic RK3566/RK3568";
|
||||
compatible = "rockchip,rk3568";
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "rk3568-nanopi-r5s-u-boot.dtsi"
|
||||
|
||||
&pcie3x2 {
|
||||
/delete-property/ vpcie3v3-supply;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@
|
|||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,10 +11,13 @@
|
|||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
/delete-property/ vpcie3v3-supply;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
|
|
@ -29,3 +32,8 @@
|
|||
bootph-all;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vcc5v0_usb_host {
|
||||
/delete-property/ regulator-always-on;
|
||||
/delete-property/ regulator-boot-on;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,6 +64,10 @@
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_none_smt {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&pcfg_pull_none {
|
||||
bootph-all;
|
||||
};
|
||||
|
|
@ -100,6 +104,10 @@
|
|||
bootph-all;
|
||||
};
|
||||
|
||||
&i2c0_xfer {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&sdmmc0_bus4 {
|
||||
bootph-all;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
u-boot,spl-boot-order = &sdmmc;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@
|
|||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -11,12 +11,6 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
u-boot,spl-boot-order = &sdmmc;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,7 +21,73 @@
|
|||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "hym8563";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* FAN */
|
||||
&pwm2 {
|
||||
pinctrl-0 = <&pwm2m1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s3>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* RS232 */
|
||||
&uart6 {
|
||||
pinctrl-0 = <&uart6m0_xfer>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* RS485 */
|
||||
&uart7 {
|
||||
pinctrl-0 = <&uart7m2_xfer>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,6 +18,42 @@
|
|||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
|
|
@ -25,8 +61,329 @@
|
|||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
||||
|
||||
pmic@0 {
|
||||
compatible = "rockchip,rk806";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc5v0_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc5v0_sys>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_log_s0: dcdc-reg3 {
|
||||
regulator-name = "vdd_log_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-init-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg5 {
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg6 {
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
regulator-name = "vdd_2v0_pldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: dcdc-reg8 {
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg9 {
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s3: dcdc-reg10 {
|
||||
regulator-name = "vcc_1v8_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avcc_1v8_s0: pldo-reg1 {
|
||||
regulator-name = "avcc_1v8_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: pldo-reg2 {
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_1v2_s0: pldo-reg3 {
|
||||
regulator-name = "avdd_1v2_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s0: pldo-reg4 {
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-name = "vccio_sd_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
pldo6_s3: pldo-reg6 {
|
||||
regulator-name = "pldo6_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-name = "vdd_ddr_pll_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_0v75_s0: nldo-reg3 {
|
||||
regulator-name = "avdd_0v75_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v85_s0: nldo-reg4 {
|
||||
regulator-name = "vdd_0v85_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s0: nldo-reg5 {
|
||||
regulator-name = "vdd_0v75_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,6 +38,20 @@
|
|||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
|
|
@ -47,6 +61,62 @@
|
|||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usbdcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usbdcin>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
|
|
@ -106,6 +176,12 @@
|
|||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
|
|
@ -117,13 +193,655 @@
|
|||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
num-cs = <2>;
|
||||
|
||||
pmic@0 {
|
||||
compatible = "rockchip,rk806";
|
||||
reg = <0x0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
pinctrl-names = "default";
|
||||
spi-max-frequency = <1000000>;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc5v0_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc5v0_sys>;
|
||||
vcc13-supply = <&vcc5v0_sys>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
|
||||
regulators {
|
||||
vdd_gpu_s0: dcdc-reg1 {
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu_s0: dcdc-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_npu_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_log_s0: dcdc-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_log_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_s0: dcdc-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
vdd_gpu_mem_s0: dcdc-reg5 {
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
regulator-name = "vdd_gpu_mem_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
vdd_npu_mem_s0: dcdc-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_npu_mem_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_2v0_pldo_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_mem_s0: dcdc-reg8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_vdenc_mem_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: dcdc-reg10 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1100000>;
|
||||
};
|
||||
};
|
||||
|
||||
avcc_1v8_s0: pldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "avcc_1v8_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd1_1v8_ddr_s3: pldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd1_1v8_ddr_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avcc_1v8_codec_s0: pldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "avcc_1v8_codec_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: pldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vccio_sd_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_1v8_s3: pldo-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vccio_1v8_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2l_0v9_ddr_s3: nldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdd2l_0v9_ddr_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_hdmi_edp_s0: nldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdd_0v75_hdmi_edp_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_0v75_s0: nldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "avdd_0v75_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v85_s0: nldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdd_0v85_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmic@1 {
|
||||
compatible = "rockchip,rk806";
|
||||
reg = <0x01>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,
|
||||
<&rk806_slave_dvs3_null>;
|
||||
pinctrl-names = "default";
|
||||
spi-max-frequency = <1000000>;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc5v0_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc5v0_sys>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
rk806_slave_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl1";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_slave_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_slave_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_cpu_big1_s0: dcdc-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_big1_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_big0_s0: dcdc-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_big0_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: dcdc-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s0: dcdc-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_big1_mem_s0: dcdc-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_big1_mem_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
vdd_cpu_big0_mem_s0: dcdc-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_big0_mem_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: dcdc-reg7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_mem_s0: dcdc-reg8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_lit_mem_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg10 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_cam_s0: pldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_1v8_cam_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
avdd1v8_ddr_pll_s0: pldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "avdd1v8_ddr_pll_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v8_pll_s0: pldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_1v8_pll_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_sd_s0: pldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_3v3_sd_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_2v8_cam_s0: pldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_2v8_cam_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
pldo6_s3: pldo-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "pldo6_s3";
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_pll_s0: nldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_0v75_pll_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdd_ddr_pll_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_0v85_s0: nldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "avdd_0v85_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_1v2_cam_s0: nldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "avdd_1v2_cam_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_1v2_s0: nldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "avdd_1v2_s0";
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,10 +10,6 @@
|
|||
#include <dt-bindings/usb/pd.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
|
||||
};
|
||||
|
|
@ -27,6 +23,19 @@
|
|||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie3_vcc3v3_en>;
|
||||
};
|
||||
|
||||
vcc5v0_usbdcin: vcc5v0-usbdcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usbdcin";
|
||||
|
|
@ -37,18 +46,6 @@
|
|||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
|
|
@ -87,6 +84,18 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie3_rst>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcie {
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
|
|
@ -97,11 +106,13 @@
|
|||
rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
|
||||
<3 RK_PD0 4 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
pcie3_rst: pcie3-rst {
|
||||
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -116,17 +127,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
|
||||
};
|
||||
|
||||
&sfc {
|
||||
|
|
@ -148,23 +152,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
companion = <&usb_host0_ohci>;
|
||||
phys = <&u2phy2_host>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
phys = <&u2phy2_host>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy2_grf {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -174,28 +161,15 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
clock-output-names = "usb480m_phy2";
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
companion = <&usb_host1_ohci>;
|
||||
phys = <&u2phy3_host>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
phys = <&u2phy3_host>;
|
||||
phy-names = "usb2-phy";
|
||||
&usb2phy2_grf {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
@ -203,16 +177,12 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
clock-output-names = "usb480m_phy3";
|
||||
status = "okay";
|
||||
&usb_host0_ehci {
|
||||
companion = <&usb_host0_ohci>;
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
&usb_host1_ehci {
|
||||
companion = <&usb_host1_ohci>;
|
||||
};
|
||||
|
||||
&usbdp_phy0 {
|
||||
|
|
@ -241,12 +211,24 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy1 {
|
||||
rockchip,dp-lane-mux = <2 3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy1_u3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
|
||||
port {
|
||||
|
|
@ -259,27 +241,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
&usbdp_phy1 {
|
||||
rockchip,dp-lane-mux = <2 3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdp_phy1_u3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-0 = <&i2c4m1_xfer>;
|
||||
status = "okay";
|
||||
|
|
@ -350,4 +311,3 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
|
||||
|
|
@ -18,17 +19,9 @@
|
|||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 95 145 195 255>;
|
||||
fan-supply = <&vcc5v0_sys>;
|
||||
pwms = <&pwm1 0 50000 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
sound {
|
||||
analog-sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "Analog";
|
||||
label = "rk3588-es8316";
|
||||
|
||||
widgets = "Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones";
|
||||
|
|
@ -43,6 +36,28 @@
|
|||
pinctrl-0 = <&hp_detect>;
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 95 145 195 255>;
|
||||
fan-supply = <&vcc5v0_sys>;
|
||||
pwms = <&pwm1 0 50000 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
|
|
@ -51,6 +66,16 @@
|
|||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
|
|
@ -69,6 +94,22 @@
|
|||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0m2_xfer>;
|
||||
|
|
@ -133,6 +174,8 @@
|
|||
reg = <0x11>;
|
||||
clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
|
|
@ -173,24 +216,407 @@
|
|||
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&avcc_1v8_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
max-frequency = <200000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s3>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
||||
num-cs = <1>;
|
||||
|
||||
pmic@0 {
|
||||
compatible = "rockchip,rk806";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0x0>;
|
||||
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc5v0_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc5v0_sys>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_log_s0: dcdc-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_log_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vdd_2v0_pldo_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: dcdc-reg8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s3: dcdc-reg10 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avcc_1v8_s0: pldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "avcc_1v8_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: pldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_1v2_s0: pldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-name = "avdd_1v2_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s0: pldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-name = "vccio_sd_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
pldo6_s3: pldo-reg6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "pldo6_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdd_ddr_pll_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_0v75_s0: nldo-reg3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "avdd_0v75_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v85_s0: nldo-reg4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-name = "vdd_0v85_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s0: nldo-reg5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-name = "vdd_0v75_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
/* connected to USB hub, which is powered by vcc5v0_sys */
|
||||
phy-supply = <&vcc5v0_sys>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,6 +7,16 @@
|
|||
#include "rk3588-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
pcie30_phy_grf: syscon@fd5b8000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5b8000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
pipe_phy1_grf: syscon@fd5c0000 {
|
||||
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c0000 0x0 0x100>;
|
||||
};
|
||||
|
||||
i2s8_8ch: i2s@fddc8000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc8000 0x0 0x1000>;
|
||||
|
|
@ -75,6 +85,159 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie3x4: pcie@fe150000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0x0f>;
|
||||
clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
|
||||
<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
|
||||
<&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
|
||||
<0 0 0 2 &pcie3x4_intc 1>,
|
||||
<0 0 0 3 &pcie3x4_intc 2>,
|
||||
<0 0 0 4 &pcie3x4_intc 3>;
|
||||
linux,pci-domain = <0>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x0000 &its1 0x0000 0x1000>;
|
||||
num-lanes = <4>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40000000 0x0 0x00400000>,
|
||||
<0x0 0xfe150000 0x0 0x00010000>,
|
||||
<0x0 0xf0000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie3x4_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3x2: pcie@fe160000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x10 0x1f>;
|
||||
clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
|
||||
<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
|
||||
<&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
|
||||
<0 0 0 2 &pcie3x2_intc 1>,
|
||||
<0 0 0 3 &pcie3x2_intc 2>,
|
||||
<0 0 0 4 &pcie3x2_intc 3>;
|
||||
linux,pci-domain = <1>;
|
||||
max-link-speed = <3>;
|
||||
msi-map = <0x1000 &its1 0x1000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40400000 0x0 0x00400000>,
|
||||
<0x0 0xfe160000 0x0 0x00010000>,
|
||||
<0x0 0xf1000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
|
||||
reset-names = "pwr", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie3x2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2x1l0: pcie@fe170000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
|
||||
<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
|
||||
<&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l0_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l0_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l0_intc 3>;
|
||||
linux,pci-domain = <2>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x2000 &its0 0x2000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40800000 0x0 0x00400000>,
|
||||
<0x0 0xfe170000 0x0 0x00010000>,
|
||||
<0x0 0xf2000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l0_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@fe1b0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1b0000 0x0 0x10000>;
|
||||
|
|
@ -123,4 +286,56 @@
|
|||
queue1 {};
|
||||
};
|
||||
};
|
||||
|
||||
sata1: sata@fe220000 {
|
||||
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfe220000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
|
||||
<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
|
||||
<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
|
||||
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
||||
ports-implemented = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
reg = <0>;
|
||||
hba-port-cap = <HBA_PORT_FBSCP>;
|
||||
phys = <&combphy1_ps PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
snps,rx-ts-max = <32>;
|
||||
snps,tx-ts-max = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
combphy1_ps: phy@fee10000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee10000 0x0 0x100>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
|
||||
reset-names = "phy", "apb";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie30phy: phy@fee80000 {
|
||||
compatible = "rockchip,rk3588-pcie3-phy";
|
||||
reg = <0x0 0xfee80000 0x0 0x20000>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
|
||||
clock-names = "pclk";
|
||||
resets = <&cru SRST_PCIE30_PHY>;
|
||||
reset-names = "phy";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,phy-grf = <&pcie30_phy_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -10,25 +10,13 @@
|
|||
#include <dt-bindings/usb/pd.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3588s.dtsi"
|
||||
|
||||
|
|
@ -12,12 +13,252 @@
|
|||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
|
||||
analog-sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "rk3588-es8316";
|
||||
|
||||
widgets = "Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones";
|
||||
|
||||
routing = "MIC2", "Mic Jack",
|
||||
"Headphones", "HPOL",
|
||||
"Headphones", "HPOR";
|
||||
|
||||
dais = <&i2s0_8ch_p0>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&io_led>;
|
||||
|
||||
io-led {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_STATUS;
|
||||
gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 95 145 195 255>;
|
||||
fan-supply = <&vcc_5v0>;
|
||||
pwms = <&pwm3 0 50000 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc_5v0: vcc-5v0-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_5v0_en>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v1_nldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_big0_s0>;
|
||||
};
|
||||
|
||||
&cpu_b2 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_b3 {
|
||||
cpu-supply = <&vdd_cpu_big1_s0>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_lit_s0>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0m2_xfer>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_big0_s0: regulator@42 {
|
||||
compatible = "rockchip,rk8602";
|
||||
reg = <0x42>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu_big0_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_big1_s0: regulator@43 {
|
||||
compatible = "rockchip,rk8603", "rockchip,rk8602";
|
||||
reg = <0x43>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu_big1_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
vdd_npu_s0: regulator@42 {
|
||||
compatible = "rockchip,rk8602";
|
||||
reg = <0x42>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_npu_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "belling,bl24c16a", "atmel,24c16";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5m2_xfer>;
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
|
||||
es8316: audio-codec@11 {
|
||||
compatible = "everest,es8316";
|
||||
reg = <0x11>;
|
||||
clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
es8316_p0_0: endpoint {
|
||||
remote-endpoint = <&i2s0_8ch_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s0_8ch {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0_lrck
|
||||
&i2s0_mclk
|
||||
&i2s0_sclk
|
||||
&i2s0_sdi0
|
||||
&i2s0_sdo0>;
|
||||
status = "okay";
|
||||
|
||||
i2s0_8ch_p0: port {
|
||||
i2s0_8ch_p0_0: endpoint {
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
remote-endpoint = <&es8316_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
|
|
@ -49,11 +290,62 @@
|
|||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
io_led: io-led {
|
||||
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
power {
|
||||
vcc_5v0_en: vcc-5v0-en {
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
rtl8211f {
|
||||
rtl8211f_rst: rtl8211f-rst {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wifibt {
|
||||
wl_reset: wl-reset {
|
||||
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
wl_dis: wl-dis {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
|
||||
wl_wake_host: wl-wake-host {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
bt_dis: bt-dis {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
|
||||
bt_wake_host: bt-wake-host {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&avcc_1v8_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
|
|
@ -61,13 +353,384 @@
|
|||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
max-frequency = <200000000>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
max-frequency = <150000000>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_3v3_s0>;
|
||||
vqmmc-supply = <&vccio_sd_s0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
status = "okay";
|
||||
assigned-clocks = <&cru CLK_SPI2>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
|
||||
|
||||
pmic@0 {
|
||||
compatible = "rockchip,rk806";
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
|
||||
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
|
||||
spi-max-frequency = <1000000>;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc5v0_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc_2v0_pldo_s3>;
|
||||
vcc12-supply = <&vcc5v0_sys>;
|
||||
vcc13-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcc14-supply = <&vcc_1v1_nldo_s3>;
|
||||
vcca-supply = <&vcc5v0_sys>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
rk806_dvs1_null: dvs1-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs2_null: dvs2-null-pins {
|
||||
pins = "gpio_pwrctrl2";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
rk806_dvs3_null: dvs3-null-pins {
|
||||
pins = "gpio_pwrctrl3";
|
||||
function = "pin_fun0";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
|
||||
regulator-name = "vdd_gpu_s0";
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-enable-ramp-delay = <400>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
||||
regulator-name = "vdd_cpu_lit_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_log_s0: dcdc-reg3 {
|
||||
regulator-name = "vdd_log_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
||||
regulator-name = "vdd_vdenc_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <550000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_s0: dcdc-reg5 {
|
||||
regulator-name = "vdd_ddr_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <675000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd2_ddr_s3: dcdc-reg6 {
|
||||
regulator-name = "vdd2_ddr_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
regulator-name = "vdd_2v0_pldo_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: dcdc-reg8 {
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vddq_ddr_s0: dcdc-reg9 {
|
||||
regulator-name = "vddq_ddr_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s3: dcdc-reg10 {
|
||||
regulator-name = "vcc_1v8_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avcc_1v8_s0: pldo-reg1 {
|
||||
regulator-name = "avcc_1v8_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8_s0: pldo-reg2 {
|
||||
regulator-name = "vcc_1v8_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_1v2_s0: pldo-reg3 {
|
||||
regulator-name = "avdd_1v2_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s0: pldo-reg4 {
|
||||
regulator-name = "vcc_3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd_s0: pldo-reg5 {
|
||||
regulator-name = "vccio_sd_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
pldo6_s3: pldo-reg6 {
|
||||
regulator-name = "pldo6_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s3: nldo-reg1 {
|
||||
regulator-name = "vdd_0v75_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <750000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr_pll_s0: nldo-reg2 {
|
||||
regulator-name = "vdd_ddr_pll_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <850000>;
|
||||
};
|
||||
};
|
||||
|
||||
avdd_0v75_s0: nldo-reg3 {
|
||||
regulator-name = "avdd_0v75_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v85_s0: nldo-reg4 {
|
||||
regulator-name = "vdd_0v85_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v75_s0: nldo-reg5 {
|
||||
regulator-name = "vdd_0v75_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&u2phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy2_host {
|
||||
status = "okay";
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-0 = <&uart2m0_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>;
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -53,57 +53,12 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fc800000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xfc800000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ohci: usb@fc840000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xfc840000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ehci: usb@fc880000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xfc880000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ohci: usb@fc8c0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xfc8c0000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu1_grf: syscon@fd58a000 {
|
||||
bootph-all;
|
||||
compatible = "rockchip,rk3588-pmu1-grf", "syscon";
|
||||
reg = <0x0 0xfd58a000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pipe_phy0_grf: syscon@fd5bc000 {
|
||||
compatible = "rockchip,pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5bc000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usb2phy0_grf: syscon@fd5d0000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
|
||||
"simple-mfd";
|
||||
|
|
@ -131,29 +86,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb2phy2_grf: syscon@fd5d8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
|
||||
"simple-mfd";
|
||||
reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy2: usb2-phy@8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x8000 0x10>;
|
||||
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy2_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vo0_grf: syscon@fd5a6000 {
|
||||
compatible = "rockchip,rk3588-vo-grf", "syscon";
|
||||
reg = <0x0 0xfd5a6000 0x0 0x2000>;
|
||||
|
|
@ -165,89 +97,11 @@
|
|||
reg = <0x0 0xfd5ac000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
usb2phy3_grf: syscon@fd5dc000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
|
||||
"simple-mfd";
|
||||
reg = <0x0 0xfd5dc000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy3: usb2-phy@c000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0xc000 0x10>;
|
||||
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy3_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usbdpphy0_grf: syscon@fd5c8000 {
|
||||
compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c8000 0x0 0x4000>;
|
||||
};
|
||||
|
||||
pcie2x1l2: pcie@fe190000 {
|
||||
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x40 0x4f>;
|
||||
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
|
||||
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
|
||||
<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l2_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l2_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l2_intc 3>;
|
||||
linux,pci-domain = <4>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x4000 &gic 0x4000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x41000000 0x0 0x00400000>,
|
||||
<0x0 0xfe190000 0x0 0x00010000>,
|
||||
<0x0 0xf4000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
|
||||
reset-names = "pcie", "periph";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sfc: spi@fe2b0000 {
|
||||
compatible = "rockchip,sfc";
|
||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
|
|
@ -293,22 +147,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
combphy0_ps: phy@fee00000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee00000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "refclk", "apbclk", "phpclk";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
|
||||
reset-names = "combphy-apb", "combphy";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&emmc_bus8 {
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/power/rk3588-power.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/ata/ahci.h>
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3588";
|
||||
|
|
@ -397,6 +399,50 @@
|
|||
};
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fc800000 {
|
||||
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
||||
reg = <0x0 0xfc800000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
|
||||
phys = <&u2phy2_host>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ohci: usb@fc840000 {
|
||||
compatible = "rockchip,rk3588-ohci", "generic-ohci";
|
||||
reg = <0x0 0xfc840000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
|
||||
phys = <&u2phy2_host>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ehci: usb@fc880000 {
|
||||
compatible = "rockchip,rk3588-ehci", "generic-ehci";
|
||||
reg = <0x0 0xfc880000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
|
||||
phys = <&u2phy3_host>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ohci: usb@fc8c0000 {
|
||||
compatible = "rockchip,rk3588-ohci", "generic-ohci";
|
||||
reg = <0x0 0xfc8c0000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
|
||||
phys = <&u2phy3_host>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sys_grf: syscon@fd58c000 {
|
||||
compatible = "rockchip,rk3588-sys-grf", "syscon";
|
||||
reg = <0x0 0xfd58c000 0x0 0x1000>;
|
||||
|
|
@ -407,6 +453,66 @@
|
|||
reg = <0x0 0xfd5b0000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pipe_phy0_grf: syscon@fd5bc000 {
|
||||
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5bc000 0x0 0x100>;
|
||||
};
|
||||
|
||||
pipe_phy2_grf: syscon@fd5c4000 {
|
||||
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5c4000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usb2phy2_grf: syscon@fd5d8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy2: usb2-phy@8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x8000 0x10>;
|
||||
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy2";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy2_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb2phy3_grf: syscon@fd5dc000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfd5dc000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy3: usb2-phy@c000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0xc000 0x10>;
|
||||
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
clock-output-names = "usb480m_phy3";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy3_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ioc: syscon@fd5f0000 {
|
||||
compatible = "rockchip,rk3588-ioc", "syscon";
|
||||
reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
||||
|
|
@ -830,6 +936,57 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2s4_8ch: i2s@fddc0000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddc0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 0>;
|
||||
dma-names = "tx";
|
||||
power-domains = <&power RK3588_PD_VO0>;
|
||||
resets = <&cru SRST_M_I2S4_8CH_TX>;
|
||||
reset-names = "tx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s5_8ch: i2s@fddf0000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddf0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 2>;
|
||||
dma-names = "tx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S5_8CH_TX>;
|
||||
reset-names = "tx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2s9_8ch: i2s@fddfc000 {
|
||||
compatible = "rockchip,rk3588-i2s-tdm";
|
||||
reg = <0x0 0xfddfc000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
|
||||
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_AUPLL>;
|
||||
dmas = <&dmac2 23>;
|
||||
dma-names = "rx";
|
||||
power-domains = <&power RK3588_PD_VO1>;
|
||||
resets = <&cru SRST_M_I2S9_8CH_RX>;
|
||||
reset-names = "rx-m";
|
||||
#sound-dai-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qos_gpu_m0: qos@fdf35000 {
|
||||
compatible = "rockchip,rk3588-qos", "syscon";
|
||||
reg = <0x0 0xfdf35000 0x0 0x20>;
|
||||
|
|
@ -1070,6 +1227,108 @@
|
|||
reg = <0x0 0xfdf82200 0x0 0x20>;
|
||||
};
|
||||
|
||||
pcie2x1l1: pcie@fe180000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x30 0x3f>;
|
||||
clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
|
||||
<&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
|
||||
<&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l1_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l1_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l1_intc 3>;
|
||||
linux,pci-domain = <3>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x3000 &its0 0x3000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy2_psu PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x40c00000 0x0 0x00400000>,
|
||||
<0x0 0xfe180000 0x0 0x00010000>,
|
||||
<0x0 0xf3000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l1_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2x1l2: pcie@fe190000 {
|
||||
compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
|
||||
bus-range = <0x40 0x4f>;
|
||||
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
|
||||
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
|
||||
<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l2_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l2_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l2_intc 3>;
|
||||
linux,pci-domain = <4>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x4000 &its0 0x4000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x41000000 0x0 0x00400000>,
|
||||
<0x0 0xfe190000 0x0 0x00010000>,
|
||||
<0x0 0xf4000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
|
||||
reset-names = "pwr", "pipe";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: ethernet@fe1c0000 {
|
||||
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
||||
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
||||
|
|
@ -1119,6 +1378,52 @@
|
|||
};
|
||||
};
|
||||
|
||||
sata0: sata@fe210000 {
|
||||
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfe210000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
|
||||
<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
|
||||
<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
|
||||
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
||||
ports-implemented = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
reg = <0>;
|
||||
hba-port-cap = <HBA_PORT_FBSCP>;
|
||||
phys = <&combphy0_ps PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
snps,rx-ts-max = <32>;
|
||||
snps,tx-ts-max = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
sata2: sata@fe230000 {
|
||||
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
|
||||
reg = <0 0xfe230000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
|
||||
<&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
|
||||
<&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
|
||||
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
|
||||
ports-implemented = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
sata-port@0 {
|
||||
reg = <0>;
|
||||
hba-port-cap = <HBA_PORT_FBSCP>;
|
||||
phys = <&combphy2_psu PHY_TYPE_SATA>;
|
||||
phy-names = "sata-phy";
|
||||
snps,rx-ts-max = <32>;
|
||||
snps,tx-ts-max = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc: mmc@fe2c0000 {
|
||||
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
||||
|
|
@ -1134,6 +1439,21 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio: mmc@fe2d0000 {
|
||||
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x00 0xfe2d0000 0x00 0x4000>;
|
||||
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
|
||||
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
||||
fifo-depth = <0x100>;
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdiom1_pins>;
|
||||
power-domains = <&power RK3588_PD_SDIO>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: mmc@fe2e0000 {
|
||||
compatible = "rockchip,rk3588-dwcmshc";
|
||||
reg = <0x0 0xfe2e0000 0x0 0x10000>;
|
||||
|
|
@ -1145,6 +1465,9 @@
|
|||
<&cru TMCLK_EMMC>;
|
||||
clock-names = "core", "bus", "axi", "block", "timer";
|
||||
max-frequency = <200000000>;
|
||||
pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
|
||||
<&emmc_cmd>, <&emmc_data_strobe>;
|
||||
pinctrl-names = "default";
|
||||
resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
|
||||
<&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
|
||||
<&cru SRST_T_EMMC>;
|
||||
|
|
@ -1742,6 +2065,18 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
saradc: adc@fec10000 {
|
||||
compatible = "rockchip,rk3588-saradc";
|
||||
reg = <0x0 0xfec10000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#io-channel-cells = <1>;
|
||||
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
||||
clock-names = "saradc", "apb_pclk";
|
||||
resets = <&cru SRST_P_SARADC>;
|
||||
reset-names = "saradc-apb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@fec80000 {
|
||||
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
||||
reg = <0x0 0xfec80000 0x0 0x1000>;
|
||||
|
|
@ -1862,6 +2197,38 @@
|
|||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
combphy0_ps: phy@fee00000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee00000 0x0 0x100>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
|
||||
reset-names = "phy", "apb";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy2_psu: phy@fee20000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee20000 0x0 0x100>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "ref", "apb", "pipe";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
#phy-cells = <1>;
|
||||
resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
|
||||
reset-names = "phy", "apb";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system_sram2: sram@ff001000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x0 0xff001000 0x0 0xef000>;
|
||||
|
|
|
|||
|
|
@ -56,10 +56,21 @@
|
|||
#else
|
||||
arch = "arm";
|
||||
#endif
|
||||
#if defined(CONFIG_SPL_GZIP)
|
||||
compression = "gzip";
|
||||
#elif defined(CONFIG_SPL_LZMA)
|
||||
compression = "lzma";
|
||||
#else
|
||||
compression = "none";
|
||||
#endif
|
||||
load = <CONFIG_TEXT_BASE>;
|
||||
entry = <CONFIG_TEXT_BASE>;
|
||||
u-boot-nodtb {
|
||||
#if defined(CONFIG_SPL_GZIP)
|
||||
compress = "gzip";
|
||||
#elif defined(CONFIG_SPL_LZMA)
|
||||
compress = "lzma";
|
||||
#endif
|
||||
};
|
||||
#ifdef CONFIG_SPL_FIT_SIGNATURE
|
||||
hash {
|
||||
|
|
|
|||
|
|
@ -166,7 +166,6 @@ config ROCKCHIP_RK3308
|
|||
imply SPL_SYSCON
|
||||
imply SPL_RAM
|
||||
imply SPL_SERIAL
|
||||
imply TPL_SERIAL
|
||||
imply SPL_SEPARATE_BSS
|
||||
help
|
||||
The Rockchip RK3308 is a ARM-based Soc which embedded with quad
|
||||
|
|
@ -436,7 +435,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
|
|||
|
||||
config ROCKCHIP_EXTERNAL_TPL
|
||||
bool "Use external TPL binary"
|
||||
default y if ROCKCHIP_RK3568 || ROCKCHIP_RK3588
|
||||
default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
|
||||
help
|
||||
Some Rockchip SoCs require an external TPL to initialize DRAM.
|
||||
Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
BANANAPI-BPI-R2-PRO
|
||||
M: Frank Wunderlich <frank-w@public-files.de>
|
||||
S: Maintained
|
||||
F: configs/bpi-r2-pro-rk3568_defconfig
|
||||
F: arch/arm/dts/rk3568-bpi-r2-pro.dts
|
||||
F: arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi
|
||||
|
||||
EVB-RK3568
|
||||
M: Joseph Chen <chenjh@rock-chips.com>
|
||||
S: Maintained
|
||||
|
|
@ -7,6 +14,13 @@ F: configs/evb-rk3568_defconfig
|
|||
F: arch/arm/dts/rk3568-evb-u-boot.dtsi
|
||||
F: arch/arm/dts/rk3568-evb.dts
|
||||
|
||||
GENERIC-RK3568
|
||||
M: Jonas Karlman <jonas@kwiboo.se>
|
||||
S: Maintained
|
||||
F: configs/generic-rk3568_defconfig
|
||||
F: arch/arm/dts/rk3568-generic.dts
|
||||
F: arch/arm/dts/rk3568-generic-u-boot.dtsi
|
||||
|
||||
LUBANCAT-2
|
||||
M: Andy Yan <andyshrk@163.com>
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -240,14 +240,14 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector,
|
|||
bool external_data = false;
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
|
||||
(IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
|
||||
(IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) {
|
||||
if (fit_image_get_type(fit, node, &type))
|
||||
puts("Cannot get image type.\n");
|
||||
else
|
||||
debug("%s ", genimg_get_type_name(type));
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_GZIP)) {
|
||||
if (spl_decompression_enabled()) {
|
||||
fit_image_get_comp(fit, node, &image_comp);
|
||||
debug("%s ", genimg_get_comp_name(image_comp));
|
||||
}
|
||||
|
|
@ -282,7 +282,11 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
|
||||
if (spl_decompression_enabled() &&
|
||||
(image_comp == IH_COMP_GZIP || image_comp == IH_COMP_LZMA))
|
||||
src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR, ARCH_DMA_MINALIGN), len);
|
||||
else
|
||||
src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
|
||||
length = len;
|
||||
|
||||
overhead = get_aligned_image_overhead(info, offset);
|
||||
|
|
@ -327,6 +331,16 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector,
|
|||
return -EIO;
|
||||
}
|
||||
length = size;
|
||||
} else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
|
||||
size = CONFIG_SYS_BOOTM_LEN;
|
||||
ulong loadEnd;
|
||||
|
||||
if (image_decomp(IH_COMP_LZMA, CONFIG_SYS_LOAD_ADDR, 0, 0,
|
||||
load_ptr, src, length, size, &loadEnd)) {
|
||||
puts("Uncompressing error\n");
|
||||
return -EIO;
|
||||
}
|
||||
length = loadEnd - CONFIG_SYS_LOAD_ADDR;
|
||||
} else {
|
||||
memcpy(load_ptr, src, length);
|
||||
}
|
||||
|
|
|
|||
93
configs/bpi-r2-pro-rk3568_defconfig
Normal file
93
configs/bpi-r2-pro-rk3568_defconfig
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00a00000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro"
|
||||
CONFIG_SYS_PROMPT="BPI-R2PRO> "
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_BOOTSTD_FULL=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_SYSBOOT=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_DWC_AHCI=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_GENERIC=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
@ -23,6 +23,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
|
|
@ -46,7 +47,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
|
|||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
# CONFIG_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ CONFIG_CMD_REGULATOR=y
|
|||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -58,8 +59,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
|
|
|
|||
|
|
@ -58,8 +58,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
|
|
|
|||
64
configs/generic-rk3568_defconfig
Normal file
64
configs/generic-rk3568_defconfig
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00a00000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_ROCKCHIP_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
# CONFIG_ROCKCHIP_IODOMAIN is not set
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
@ -61,6 +61,9 @@ CONFIG_MMC_SDHCI=y
|
|||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
# CONFIG_SPI_FLASH is not set
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00a00000
|
||||
|
|
@ -17,10 +18,13 @@ CONFIG_SPL_STACK=0x400000
|
|||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
|
@ -37,14 +41,16 @@ CONFIG_CMD_GPIO=y
|
|||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_WARN=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -52,19 +58,20 @@ CONFIG_ROCKCHIP_GPIO=y
|
|||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
|
|
@ -72,7 +79,6 @@ CONFIG_BAUDRATE=1500000
|
|||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
CONFIG_COUNTER_FREQUENCY=24000000
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_TEXT_BASE=0x00a00000
|
||||
|
|
@ -17,10 +18,13 @@ CONFIG_SPL_STACK=0x400000
|
|||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
|
|
@ -37,14 +41,16 @@ CONFIG_CMD_GPIO=y
|
|||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_WARN=y
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -52,19 +58,24 @@ CONFIG_ROCKCHIP_GPIO=y
|
|||
CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
|
|
@ -72,7 +83,6 @@ CONFIG_BAUDRATE=1500000
|
|||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
|
|
|
|||
|
|
@ -53,8 +53,6 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
|
|
|
|||
|
|
@ -53,8 +53,6 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
|
|
|
|||
|
|
@ -82,6 +82,9 @@ CONFIG_SF_DEFAULT_BUS=4
|
|||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -52,6 +52,7 @@ CONFIG_CMD_GPT=y
|
|||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
|
|
@ -80,6 +81,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
|||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_PHY_MOTORCOMM=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ CONFIG_CMD_GPT=y
|
|||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
|
|
@ -78,6 +79,9 @@ CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
|||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ CONFIG_CMD_REGULATOR=y
|
|||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -59,8 +60,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@ CONFIG_ANDROID_BOOT_IMAGE=y
|
|||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
|
|
@ -46,7 +47,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
|
|||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
# CONFIG_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@ CONFIG_CMD_GPT=y
|
|||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
|
|
@ -76,8 +77,9 @@ CONFIG_SF_DEFAULT_BUS=4
|
|||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3308=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
|
|
@ -23,7 +24,7 @@ CONFIG_DEBUG_UART=y
|
|||
CONFIG_ANDROID_BOOT_IMAGE=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
|
|
@ -47,7 +48,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
|
|||
# CONFIG_CMD_ITEST is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
# CONFIG_DOS_PARTITION is not set
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
|
|
|
|||
|
|
@ -58,8 +58,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
|
|
|
|||
|
|
@ -78,9 +78,9 @@ CONFIG_SF_DEFAULT_BUS=5
|
|||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
|
|
|
|||
|
|
@ -67,6 +67,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_MOTORCOMM=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -67,6 +67,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_MOTORCOMM=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ CONFIG_CMD_GPT=y
|
|||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_POWEROFF=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
|
|
@ -67,6 +68,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_PHY_MOTORCOMM=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
CONFIG_NVME_PCI=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
|
|
|
|||
|
|
@ -38,16 +38,8 @@ Building
|
|||
(or you can use another cross compiler if you prefer)
|
||||
|
||||
2. To build RK3308 board:
|
||||
- Get the rkbin
|
||||
=> git clone https://github.com/rockchip-linux/rkbin.git
|
||||
|
||||
- Compile U-Boot
|
||||
=> cd /path/to/u-boot
|
||||
=> export BL31=/path/to/rkbin/bin/rk33/rk3308_bl31_v2.22.elf
|
||||
=> make roc-cc-rk3308_defconfig
|
||||
=> make CROSS_COMPILE=aarch64-linux-gnu- all
|
||||
=> ./tools/mkimage -n rk3308 -T rksd -d /path/to/rkbin/bin/rk33/rk3308_ddr_589MHz_uart2_m0_v1.26.bin idbloader.img
|
||||
=> cat spl/u-boot-spl.bin >> idbloader.img
|
||||
See doc/board/rockchip/rockchip.rst
|
||||
|
||||
3. To build RK3399 board:
|
||||
|
||||
|
|
|
|||
|
|
@ -53,6 +53,7 @@ List of mainline supported Rockchip boards:
|
|||
- Google Speedy (chromebook_speedy)
|
||||
- Amarula Vyasa-RK3288 (vyasa-rk3288)
|
||||
* rk3308
|
||||
- Radxa ROCK Pi S (rock-pi-s-rk3308)
|
||||
- Rockchip Evb-RK3308 (evb-rk3308)
|
||||
- Roc-cc-RK3308 (roc-cc-rk3308)
|
||||
* rk3326
|
||||
|
|
@ -101,9 +102,11 @@ List of mainline supported Rockchip boards:
|
|||
|
||||
* rk3568
|
||||
- Rockchip Evb-RK3568 (evb-rk3568)
|
||||
- Banana Pi BPI-R2 Pro (bpi-r2-pro-rk3568)
|
||||
- EmbedFire LubanCat 2 (lubancat-2-rk3568)
|
||||
- FriendlyElec NanoPi R5C (nanopi-r5c-rk3568)
|
||||
- FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
|
||||
- Generic RK3566/RK3568 (generic-rk3568)
|
||||
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
|
||||
- Radxa E25 Carrier Board (radxa-e25-rk3568)
|
||||
- Radxa ROCK 3 Model A (rock-3a-rk3568)
|
||||
|
|
@ -142,6 +145,19 @@ To build TF-A:
|
|||
|
||||
Specify the PLAT= with desired Rockchip platform to build TF-A for.
|
||||
|
||||
For SoCs whose TF-A code is not available as open source, use BL31 binary provided by Rockchip:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
git clone --depth 1 https://github.com/rockchip-linux/rkbin
|
||||
|
||||
TPL
|
||||
^^^
|
||||
|
||||
For some SoCs U-Boot sources lack of support to inizialize DRAM.
|
||||
In these cases, to get a fully functional image following :ref:`PackageWithTPLandSPL`, use DDR binary provided by Rockchip rkbin repository as ROCKCHIP_TPL when building U-Boot.
|
||||
Otherwise, follow :ref:`PackageWithRockchipMiniloader`.
|
||||
|
||||
U-Boot
|
||||
^^^^^^
|
||||
|
||||
|
|
@ -172,6 +188,15 @@ To build rk3288 boards:
|
|||
make evb-rk3288_defconfig
|
||||
make CROSS_COMPILE=arm-linux-gnueabihf-
|
||||
|
||||
To build rk3308 boards:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
export BL31=../rkbin/bin/rk33/rk3308_bl31_v2.26.elf
|
||||
export ROCKCHIP_TPL=../rkbin/bin/rk33/rk3308_ddr_589MHz_uartX_mY_v2.07.bin
|
||||
make evb-rk3308_defconfig
|
||||
make CROSS_COMPILE=aarch64-linux-gnu-
|
||||
|
||||
To build rk3328 boards:
|
||||
|
||||
.. code-block:: bash
|
||||
|
|
@ -218,11 +243,13 @@ To build rk3588 boards:
|
|||
Flashing
|
||||
--------
|
||||
|
||||
.. _`PackageWithTPLandSPL`:
|
||||
|
||||
1. Package the image with U-Boot TPL/SPL
|
||||
-----------------------------------------
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
SD Card
|
||||
^^^^^^^
|
||||
"""""""
|
||||
|
||||
All Rockchip platforms (except rk3128 which doesn't use SPL) are now
|
||||
supporting a single boot image using binman.
|
||||
|
|
@ -235,7 +262,7 @@ To write an image that boots from a SD card (assumed to be /dev/sda):
|
|||
sync
|
||||
|
||||
eMMC
|
||||
^^^^
|
||||
""""
|
||||
|
||||
eMMC flash would probe on mmc0 in most of the Rockchip platforms.
|
||||
|
||||
|
|
@ -274,7 +301,7 @@ For Rockchip 32-bit platforms the U-Boot proper image
|
|||
is u-boot-dtb.img
|
||||
|
||||
SPI
|
||||
^^^
|
||||
"""
|
||||
|
||||
Write u-boot-rockchip-spi.bin to offset 0 of SPI flash.
|
||||
|
||||
|
|
@ -286,8 +313,10 @@ Copy u-boot-rockchip-spi.bin into SD card and boot from SD:
|
|||
load mmc 1:1 $kernel_addr_r u-boot-rockchip-spi.bin
|
||||
sf update $fileaddr 0 $filesize
|
||||
|
||||
.. _`PackageWithRockchipMiniloader`:
|
||||
|
||||
2. Package the image with Rockchip miniloader
|
||||
---------------------------------------------
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Image package with Rockchip miniloader requires rkbin [1].
|
||||
|
||||
|
|
@ -327,14 +356,14 @@ Note:
|
|||
2. 0x200000 is a load address and is an option for some platforms.
|
||||
|
||||
3. Package the RK3066 image with U-Boot TPL/SPL on NAND
|
||||
-------------------------------------------------------
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support.
|
||||
If all other boot options fail then it enters into a BootROM mode on the USB OTG port.
|
||||
This method loads TPL/SPL on NAND with U-Boot and kernel on SD card.
|
||||
|
||||
SD Card
|
||||
^^^^^^^
|
||||
"""""""
|
||||
|
||||
U-Boot expects a GPT partition map and a boot directory structure with files on the SD card.
|
||||
|
||||
|
|
@ -369,7 +398,7 @@ To write a U-Boot image to the SD card (assumed to be /dev/sda):
|
|||
sync
|
||||
|
||||
NAND
|
||||
^^^^
|
||||
""""
|
||||
|
||||
Bring device in BootROM mode:
|
||||
|
||||
|
|
|
|||
|
|
@ -101,6 +101,15 @@ config ROCKCHIP_OTP
|
|||
addressing and a length or through child-nodes that are generated
|
||||
based on the e-fuse map retrieved from the DTS.
|
||||
|
||||
config ROCKCHIP_IODOMAIN
|
||||
bool "Rockchip IO-domain driver support"
|
||||
depends on DM_REGULATOR && ARCH_ROCKCHIP
|
||||
default y if ROCKCHIP_RK3568
|
||||
help
|
||||
Enable support for IO-domains in Rockchip SoCs. It is necessary
|
||||
for the IO-domain setting of the SoC to match the voltage supplied
|
||||
by the regulators.
|
||||
|
||||
config SIFIVE_OTP
|
||||
bool "SiFive eMemory OTP driver"
|
||||
depends on MISC
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ obj-$(CONFIG_SANDBOX) += qfw_sandbox.o
|
|||
endif
|
||||
obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
|
||||
obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o
|
||||
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o
|
||||
obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o
|
||||
obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o
|
||||
obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
|
||||
|
|
|
|||
167
drivers/misc/rockchip-io-domain.c
Normal file
167
drivers/misc/rockchip-io-domain.c
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Rockchip IO Voltage Domain driver
|
||||
*
|
||||
* Ported from linux drivers/soc/rockchip/io-domain.c
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <regmap.h>
|
||||
#include <syscon.h>
|
||||
#include <power/regulator.h>
|
||||
|
||||
#define MAX_SUPPLIES 16
|
||||
|
||||
/*
|
||||
* The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
|
||||
* "Recommended Operating Conditions" for "Digital GPIO". When the typical
|
||||
* is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
|
||||
*
|
||||
* They are used like this:
|
||||
* - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
|
||||
* SoC we're at 3.3.
|
||||
* - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
|
||||
* that to be an error.
|
||||
*/
|
||||
#define MAX_VOLTAGE_1_8 1980000
|
||||
#define MAX_VOLTAGE_3_3 3600000
|
||||
|
||||
#define RK3568_PMU_GRF_IO_VSEL0 0x0140
|
||||
#define RK3568_PMU_GRF_IO_VSEL1 0x0144
|
||||
#define RK3568_PMU_GRF_IO_VSEL2 0x0148
|
||||
|
||||
struct rockchip_iodomain_soc_data {
|
||||
int grf_offset;
|
||||
const char *supply_names[MAX_SUPPLIES];
|
||||
int (*write)(struct regmap *grf, int idx, int uV);
|
||||
};
|
||||
|
||||
static int rk3568_iodomain_write(struct regmap *grf, int idx, int uV)
|
||||
{
|
||||
u32 is_3v3 = uV > MAX_VOLTAGE_1_8;
|
||||
u32 val0, val1;
|
||||
int b;
|
||||
|
||||
switch (idx) {
|
||||
case 0: /* pmuio1 */
|
||||
break;
|
||||
case 1: /* pmuio2 */
|
||||
b = idx;
|
||||
val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
|
||||
b = idx + 4;
|
||||
val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
|
||||
|
||||
regmap_write(grf, RK3568_PMU_GRF_IO_VSEL2, val0);
|
||||
regmap_write(grf, RK3568_PMU_GRF_IO_VSEL2, val1);
|
||||
break;
|
||||
case 3: /* vccio2 */
|
||||
break;
|
||||
case 2: /* vccio1 */
|
||||
case 4: /* vccio3 */
|
||||
case 5: /* vccio4 */
|
||||
case 6: /* vccio5 */
|
||||
case 7: /* vccio6 */
|
||||
case 8: /* vccio7 */
|
||||
b = idx - 1;
|
||||
val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
|
||||
val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
|
||||
|
||||
regmap_write(grf, RK3568_PMU_GRF_IO_VSEL0, val0);
|
||||
regmap_write(grf, RK3568_PMU_GRF_IO_VSEL1, val1);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = {
|
||||
.grf_offset = 0x140,
|
||||
.supply_names = {
|
||||
NULL,
|
||||
"pmuio2-supply",
|
||||
"vccio1-supply",
|
||||
NULL,
|
||||
"vccio3-supply",
|
||||
"vccio4-supply",
|
||||
"vccio5-supply",
|
||||
"vccio6-supply",
|
||||
"vccio7-supply",
|
||||
},
|
||||
.write = rk3568_iodomain_write,
|
||||
};
|
||||
|
||||
static const struct udevice_id rockchip_iodomain_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3568-pmu-io-voltage-domain",
|
||||
.data = (ulong)&soc_data_rk3568_pmu,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static int rockchip_iodomain_bind(struct udevice *dev)
|
||||
{
|
||||
/*
|
||||
* According to the Hardware Design Guide, IO-domain configuration must
|
||||
* be consistent with the power supply voltage (1.8V or 3.3V).
|
||||
* Probe after bind to configure IO-domain voltage early during boot.
|
||||
*/
|
||||
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_iodomain_probe(struct udevice *dev)
|
||||
{
|
||||
struct rockchip_iodomain_soc_data *soc_data =
|
||||
(struct rockchip_iodomain_soc_data *)dev_get_driver_data(dev);
|
||||
struct regmap *grf;
|
||||
int ret;
|
||||
|
||||
grf = syscon_get_regmap(dev_get_parent(dev));
|
||||
if (IS_ERR(grf))
|
||||
return PTR_ERR(grf);
|
||||
|
||||
for (int i = 0; i < MAX_SUPPLIES; i++) {
|
||||
const char *supply_name = soc_data->supply_names[i];
|
||||
struct udevice *reg;
|
||||
int uV;
|
||||
|
||||
if (!supply_name)
|
||||
continue;
|
||||
|
||||
ret = device_get_supply_regulator(dev, supply_name, ®);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
ret = regulator_autoset(reg);
|
||||
if (ret && ret != -EALREADY && ret != -EMEDIUMTYPE &&
|
||||
ret != -ENOSYS)
|
||||
continue;
|
||||
|
||||
uV = regulator_get_value(reg);
|
||||
if (uV <= 0)
|
||||
continue;
|
||||
|
||||
if (uV > MAX_VOLTAGE_3_3) {
|
||||
dev_crit(dev, "%s: %d uV is too high. May damage SoC!\n",
|
||||
supply_name, uV);
|
||||
continue;
|
||||
}
|
||||
|
||||
soc_data->write(grf, i, uV);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(rockchip_iodomain) = {
|
||||
.name = "rockchip_iodomain",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = rockchip_iodomain_ids,
|
||||
.bind = rockchip_iodomain_bind,
|
||||
.probe = rockchip_iodomain_probe,
|
||||
};
|
||||
|
|
@ -225,6 +225,14 @@ config DWC_ETH_QOS_IMX
|
|||
The Synopsys Designware Ethernet QOS IP block with the specific
|
||||
configuration used in IMX soc.
|
||||
|
||||
config DWC_ETH_QOS_ROCKCHIP
|
||||
bool "Synopsys DWC Ethernet QOS device support for Rockchip SoCs"
|
||||
depends on DWC_ETH_QOS
|
||||
select DM_ETH_PHY
|
||||
help
|
||||
The Synopsys Designware Ethernet QOS IP block with specific
|
||||
configuration used in Rockchip SoCs.
|
||||
|
||||
config DWC_ETH_QOS_STM32
|
||||
bool "Synopsys DWC Ethernet QOS device support for STM32"
|
||||
depends on DWC_ETH_QOS
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
|
|||
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
|
||||
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
|
||||
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
|
||||
obj-$(CONFIG_DWC_ETH_QOS_ROCKCHIP) += dwc_eth_qos_rockchip.o
|
||||
obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
|
||||
obj-$(CONFIG_DWC_ETH_QOS_STARFIVE) += dwc_eth_qos_starfive.o
|
||||
obj-$(CONFIG_E1000) += e1000.o
|
||||
|
|
|
|||
|
|
@ -812,6 +812,7 @@ static int eqos_start(struct udevice *dev)
|
|||
|
||||
if (!eqos->phy) {
|
||||
pr_err("phy_connect() failed");
|
||||
ret = -ENODEV;
|
||||
goto err_stop_resets;
|
||||
}
|
||||
|
||||
|
|
@ -839,6 +840,7 @@ static int eqos_start(struct udevice *dev)
|
|||
|
||||
if (!eqos->phy->link) {
|
||||
pr_err("No link");
|
||||
ret = -EAGAIN;
|
||||
goto err_shutdown_phy;
|
||||
}
|
||||
|
||||
|
|
@ -1192,14 +1194,12 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
|
|||
struct eqos_desc *rx_desc;
|
||||
int length;
|
||||
|
||||
debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
|
||||
|
||||
rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
|
||||
eqos->config->ops->eqos_inval_desc(rx_desc);
|
||||
if (rx_desc->des3 & EQOS_DESC3_OWN) {
|
||||
debug("%s: RX packet not available\n", __func__);
|
||||
if (rx_desc->des3 & EQOS_DESC3_OWN)
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
|
||||
|
||||
*packetp = eqos->rx_dma_buf +
|
||||
(eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
|
||||
|
|
@ -1315,22 +1315,12 @@ static int eqos_probe_resources_core(struct udevice *dev)
|
|||
}
|
||||
debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
|
||||
|
||||
eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
|
||||
if (!eqos->rx_pkt) {
|
||||
debug("%s: malloc(rx_pkt) failed\n", __func__);
|
||||
ret = -ENOMEM;
|
||||
goto err_free_rx_dma_buf;
|
||||
}
|
||||
debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
|
||||
|
||||
eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
|
||||
EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
|
||||
|
||||
debug("%s: OK\n", __func__);
|
||||
return 0;
|
||||
|
||||
err_free_rx_dma_buf:
|
||||
free(eqos->rx_dma_buf);
|
||||
err_free_tx_dma_buf:
|
||||
free(eqos->tx_dma_buf);
|
||||
err_free_descs:
|
||||
|
|
@ -1349,7 +1339,6 @@ static int eqos_remove_resources_core(struct udevice *dev)
|
|||
|
||||
debug("%s(dev=%p):\n", __func__, dev);
|
||||
|
||||
free(eqos->rx_pkt);
|
||||
free(eqos->rx_dma_buf);
|
||||
free(eqos->tx_dma_buf);
|
||||
eqos_free_descs(eqos->rx_descs);
|
||||
|
|
@ -1719,7 +1708,16 @@ static const struct udevice_id eqos_ids[] = {
|
|||
.data = (ulong)&eqos_imx_config
|
||||
},
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
|
||||
{
|
||||
.compatible = "rockchip,rk3568-gmac",
|
||||
.data = (ulong)&eqos_rockchip_config
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3588-gmac",
|
||||
.data = (ulong)&eqos_rockchip_config
|
||||
},
|
||||
#endif
|
||||
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
|
||||
{
|
||||
.compatible = "qcom,qcs404-ethqos",
|
||||
|
|
@ -1732,7 +1730,6 @@ static const struct udevice_id eqos_ids[] = {
|
|||
.data = (ulong)&eqos_jh7110_config
|
||||
},
|
||||
#endif
|
||||
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@ struct eqos_mac_regs {
|
|||
#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
|
||||
#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
|
||||
#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
|
||||
#define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1
|
||||
#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
|
||||
#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
|
||||
#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
|
||||
|
|
@ -273,7 +274,6 @@ struct eqos_priv {
|
|||
unsigned int desc_per_cacheline;
|
||||
void *tx_dma_buf;
|
||||
void *rx_dma_buf;
|
||||
void *rx_pkt;
|
||||
bool started;
|
||||
bool reg_access_ok;
|
||||
bool clk_ck_enabled;
|
||||
|
|
@ -288,5 +288,6 @@ void eqos_flush_buffer_generic(void *buf, size_t size);
|
|||
int eqos_null_ops(struct udevice *dev);
|
||||
|
||||
extern struct eqos_config eqos_imx_config;
|
||||
extern struct eqos_config eqos_rockchip_config;
|
||||
extern struct eqos_config eqos_qcom_config;
|
||||
extern struct eqos_config eqos_jh7110_config;
|
||||
|
|
|
|||
531
drivers/net/dwc_eth_qos_rockchip.c
Normal file
531
drivers/net/dwc_eth_qos_rockchip.c
Normal file
|
|
@ -0,0 +1,531 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright Contributors to the U-Boot project.
|
||||
*
|
||||
* rk_gmac_ops ported from linux drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
|
||||
*
|
||||
* Ported code is intentionally left as close as possible with linux counter
|
||||
* part in order to simplify future porting of fixes and support for other SoCs.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <net.h>
|
||||
#include <phy.h>
|
||||
#include <regmap.h>
|
||||
#include <reset.h>
|
||||
#include <syscon.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "dwc_eth_qos.h"
|
||||
|
||||
struct rk_gmac_ops {
|
||||
const char *compatible;
|
||||
int (*set_to_rgmii)(struct udevice *dev,
|
||||
int tx_delay, int rx_delay);
|
||||
int (*set_to_rmii)(struct udevice *dev);
|
||||
int (*set_gmac_speed)(struct udevice *dev);
|
||||
void (*set_clock_selection)(struct udevice *dev, bool enable);
|
||||
u32 regs[3];
|
||||
};
|
||||
|
||||
struct rockchip_platform_data {
|
||||
struct reset_ctl_bulk resets;
|
||||
const struct rk_gmac_ops *ops;
|
||||
int id;
|
||||
bool clock_input;
|
||||
struct regmap *grf;
|
||||
struct regmap *php_grf;
|
||||
};
|
||||
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
#define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16))
|
||||
#define GRF_CLR_BIT(nr) (BIT((nr) + 16))
|
||||
|
||||
#define RK3568_GRF_GMAC0_CON0 0x0380
|
||||
#define RK3568_GRF_GMAC0_CON1 0x0384
|
||||
#define RK3568_GRF_GMAC1_CON0 0x0388
|
||||
#define RK3568_GRF_GMAC1_CON1 0x038c
|
||||
|
||||
/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
|
||||
#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
|
||||
(GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
|
||||
#define RK3568_GMAC_PHY_INTF_SEL_RMII \
|
||||
(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
|
||||
#define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
|
||||
#define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
|
||||
#define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
|
||||
#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
|
||||
#define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
|
||||
#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
|
||||
|
||||
/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
|
||||
#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
|
||||
#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
|
||||
|
||||
static int rk3568_set_to_rgmii(struct udevice *dev,
|
||||
int tx_delay, int rx_delay)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 con0, con1;
|
||||
|
||||
con0 = (data->id == 1) ? RK3568_GRF_GMAC1_CON0 :
|
||||
RK3568_GRF_GMAC0_CON0;
|
||||
con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
|
||||
RK3568_GRF_GMAC0_CON1;
|
||||
|
||||
regmap_write(data->grf, con0,
|
||||
RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
||||
RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
|
||||
|
||||
regmap_write(data->grf, con1,
|
||||
RK3568_GMAC_PHY_INTF_SEL_RGMII |
|
||||
RK3568_GMAC_RXCLK_DLY_ENABLE |
|
||||
RK3568_GMAC_TXCLK_DLY_ENABLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3568_set_to_rmii(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 con1;
|
||||
|
||||
con1 = (data->id == 1) ? RK3568_GRF_GMAC1_CON1 :
|
||||
RK3568_GRF_GMAC0_CON1;
|
||||
regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3568_set_gmac_speed(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
ulong rate;
|
||||
int ret;
|
||||
|
||||
switch (eqos->phy->speed) {
|
||||
case SPEED_10:
|
||||
rate = 2500000;
|
||||
break;
|
||||
case SPEED_100:
|
||||
rate = 25000000;
|
||||
break;
|
||||
case SPEED_1000:
|
||||
rate = 125000000;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_set_rate(&eqos->clk_tx, rate);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* sys_grf */
|
||||
#define RK3588_GRF_GMAC_CON7 0x031c
|
||||
#define RK3588_GRF_GMAC_CON8 0x0320
|
||||
#define RK3588_GRF_GMAC_CON9 0x0324
|
||||
|
||||
#define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
|
||||
#define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
|
||||
#define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
|
||||
#define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
|
||||
|
||||
#define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
|
||||
#define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
|
||||
|
||||
/* php_grf */
|
||||
#define RK3588_GRF_GMAC_CON0 0x0008
|
||||
#define RK3588_GRF_CLK_CON1 0x0070
|
||||
|
||||
#define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \
|
||||
(GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6))
|
||||
#define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \
|
||||
(GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6))
|
||||
|
||||
#define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
|
||||
#define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
|
||||
|
||||
#define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4)
|
||||
#define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4)
|
||||
|
||||
#define RK3588_GMAC_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
|
||||
#define RK3588_GMAC_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
|
||||
|
||||
#define RK3588_GMAC_CLK_RGMII_DIV1(id) \
|
||||
(GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3))
|
||||
#define RK3588_GMAC_CLK_RGMII_DIV5(id) \
|
||||
(GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
|
||||
#define RK3588_GMAC_CLK_RGMII_DIV50(id) \
|
||||
(GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3))
|
||||
|
||||
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
|
||||
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
|
||||
|
||||
static int rk3588_set_to_rgmii(struct udevice *dev,
|
||||
int tx_delay, int rx_delay)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 offset_con, id = data->id;
|
||||
|
||||
offset_con = data->id == 1 ? RK3588_GRF_GMAC_CON9 :
|
||||
RK3588_GRF_GMAC_CON8;
|
||||
|
||||
regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
|
||||
RK3588_GMAC_PHY_INTF_SEL_RGMII(id));
|
||||
|
||||
regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
|
||||
RK3588_GMAC_CLK_RGMII_MODE(id));
|
||||
|
||||
regmap_write(data->grf, RK3588_GRF_GMAC_CON7,
|
||||
RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
|
||||
RK3588_GMAC_TXCLK_DLY_ENABLE(id));
|
||||
|
||||
regmap_write(data->grf, offset_con,
|
||||
RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
|
||||
RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3588_set_to_rmii(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
regmap_write(data->php_grf, RK3588_GRF_GMAC_CON0,
|
||||
RK3588_GMAC_PHY_INTF_SEL_RMII(data->id));
|
||||
|
||||
regmap_write(data->php_grf, RK3588_GRF_CLK_CON1,
|
||||
RK3588_GMAC_CLK_RMII_MODE(data->id));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3588_set_gmac_speed(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
u32 val = 0, id = data->id;
|
||||
|
||||
switch (eqos->phy->speed) {
|
||||
case SPEED_10:
|
||||
if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
|
||||
val = RK3588_GMAC_CLK_RMII_DIV20(id);
|
||||
else
|
||||
val = RK3588_GMAC_CLK_RGMII_DIV50(id);
|
||||
break;
|
||||
case SPEED_100:
|
||||
if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
|
||||
val = RK3588_GMAC_CLK_RMII_DIV2(id);
|
||||
else
|
||||
val = RK3588_GMAC_CLK_RGMII_DIV5(id);
|
||||
break;
|
||||
case SPEED_1000:
|
||||
if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
|
||||
val = RK3588_GMAC_CLK_RGMII_DIV1(id);
|
||||
else
|
||||
return -EINVAL;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
u32 val = data->clock_input ? RK3588_GMAC_CLK_SELET_IO(data->id) :
|
||||
RK3588_GMAC_CLK_SELET_CRU(data->id);
|
||||
|
||||
val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(data->id) :
|
||||
RK3588_GMAC_CLK_RMII_GATE(data->id);
|
||||
|
||||
regmap_write(data->php_grf, RK3588_GRF_CLK_CON1, val);
|
||||
}
|
||||
|
||||
static const struct rk_gmac_ops rk_gmac_ops[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3568-gmac",
|
||||
.set_to_rgmii = rk3568_set_to_rgmii,
|
||||
.set_to_rmii = rk3568_set_to_rmii,
|
||||
.set_gmac_speed = rk3568_set_gmac_speed,
|
||||
.regs = {
|
||||
0xfe2a0000, /* gmac0 */
|
||||
0xfe010000, /* gmac1 */
|
||||
0x0, /* sentinel */
|
||||
},
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3588-gmac",
|
||||
.set_to_rgmii = rk3588_set_to_rgmii,
|
||||
.set_to_rmii = rk3588_set_to_rmii,
|
||||
.set_gmac_speed = rk3588_set_gmac_speed,
|
||||
.set_clock_selection = rk3588_set_clock_selection,
|
||||
.regs = {
|
||||
0xfe1b0000, /* gmac0 */
|
||||
0xfe1c0000, /* gmac1 */
|
||||
0x0, /* sentinel */
|
||||
},
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct rk_gmac_ops *get_rk_gmac_ops(struct udevice *dev)
|
||||
{
|
||||
const struct rk_gmac_ops *ops = rk_gmac_ops;
|
||||
|
||||
while (ops->compatible) {
|
||||
if (device_is_compatible(dev, ops->compatible))
|
||||
return ops;
|
||||
ops++;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int eqos_probe_resources_rk(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data;
|
||||
const char *clock_in_out;
|
||||
int reset_flags = GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE;
|
||||
int ret;
|
||||
|
||||
data = calloc(1, sizeof(struct rockchip_platform_data));
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->ops = get_rk_gmac_ops(dev);
|
||||
if (!data->ops) {
|
||||
ret = -EINVAL;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
for (int i = 0; data->ops->regs[i]; i++) {
|
||||
if (data->ops->regs[i] == (u32)eqos->regs) {
|
||||
data->id = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pdata->priv_pdata = data;
|
||||
pdata->phy_interface = eqos->config->interface(dev);
|
||||
pdata->max_speed = eqos->max_speed;
|
||||
|
||||
if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
|
||||
pr_err("Invalid PHY interface\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
data->grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,grf");
|
||||
if (IS_ERR(data->grf)) {
|
||||
dev_err(dev, "Missing rockchip,grf property\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
|
||||
data->php_grf =
|
||||
syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
|
||||
if (IS_ERR(data->php_grf)) {
|
||||
dev_err(dev, "Missing rockchip,php-grf property\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free;
|
||||
}
|
||||
}
|
||||
|
||||
ret = reset_get_bulk(dev, &data->resets);
|
||||
if (ret < 0)
|
||||
goto err_free;
|
||||
|
||||
reset_assert_bulk(&data->resets);
|
||||
|
||||
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
|
||||
if (ret) {
|
||||
dev_dbg(dev, "clk_get_by_name(stmmaceth) failed: %d", ret);
|
||||
goto err_release_resets;
|
||||
}
|
||||
|
||||
if (device_is_compatible(dev, "rockchip,rk3568-gmac")) {
|
||||
ret = clk_get_by_name(dev, "clk_mac_speed", &eqos->clk_tx);
|
||||
if (ret) {
|
||||
dev_dbg(dev, "clk_get_by_name(clk_mac_speed) failed: %d", ret);
|
||||
goto err_free_clk_master_bus;
|
||||
}
|
||||
}
|
||||
|
||||
clock_in_out = dev_read_string(dev, "clock_in_out");
|
||||
if (clock_in_out && !strcmp(clock_in_out, "input"))
|
||||
data->clock_input = true;
|
||||
else
|
||||
data->clock_input = false;
|
||||
|
||||
/* snps,reset props are deprecated, do bare minimum to support them */
|
||||
if (dev_read_bool(dev, "snps,reset-active-low"))
|
||||
reset_flags |= GPIOD_ACTIVE_LOW;
|
||||
|
||||
dev_read_u32_array(dev, "snps,reset-delays-us", eqos->reset_delays, 3);
|
||||
|
||||
gpio_request_by_name(dev, "snps,reset-gpio", 0,
|
||||
&eqos->phy_reset_gpio, reset_flags);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_clk_master_bus:
|
||||
clk_free(&eqos->clk_master_bus);
|
||||
err_release_resets:
|
||||
reset_release_bulk(&data->resets);
|
||||
err_free:
|
||||
free(data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int eqos_remove_resources_rk(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
|
||||
dm_gpio_free(dev, &eqos->phy_reset_gpio);
|
||||
|
||||
clk_free(&eqos->clk_tx);
|
||||
clk_free(&eqos->clk_master_bus);
|
||||
reset_release_bulk(&data->resets);
|
||||
free(data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int eqos_stop_resets_rk(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
return reset_assert_bulk(&data->resets);
|
||||
}
|
||||
|
||||
static int eqos_start_resets_rk(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
return reset_deassert_bulk(&data->resets);
|
||||
}
|
||||
|
||||
static int eqos_stop_clks_rk(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
if (data->ops->set_clock_selection)
|
||||
data->ops->set_clock_selection(dev, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int eqos_start_clks_rk(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
int tx_delay, rx_delay, ret;
|
||||
|
||||
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
|
||||
udelay(eqos->reset_delays[1]);
|
||||
|
||||
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
udelay(eqos->reset_delays[2]);
|
||||
}
|
||||
|
||||
if (data->ops->set_clock_selection)
|
||||
data->ops->set_clock_selection(dev, true);
|
||||
|
||||
tx_delay = dev_read_u32_default(dev, "tx_delay", 0x30);
|
||||
rx_delay = dev_read_u32_default(dev, "rx_delay", 0x10);
|
||||
|
||||
switch (pdata->phy_interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
return data->ops->set_to_rgmii(dev, tx_delay, rx_delay);
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
return data->ops->set_to_rgmii(dev, 0, 0);
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
return data->ops->set_to_rgmii(dev, tx_delay, 0);
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
return data->ops->set_to_rgmii(dev, 0, rx_delay);
|
||||
case PHY_INTERFACE_MODE_RMII:
|
||||
return data->ops->set_to_rmii(dev);
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int eqos_set_tx_clk_speed_rk(struct udevice *dev)
|
||||
{
|
||||
struct eth_pdata *pdata = dev_get_plat(dev);
|
||||
struct rockchip_platform_data *data = pdata->priv_pdata;
|
||||
|
||||
return data->ops->set_gmac_speed(dev);
|
||||
}
|
||||
|
||||
static ulong eqos_get_tick_clk_rate_rk(struct udevice *dev)
|
||||
{
|
||||
struct eqos_priv *eqos = dev_get_priv(dev);
|
||||
|
||||
return clk_get_rate(&eqos->clk_master_bus);
|
||||
}
|
||||
|
||||
static struct eqos_ops eqos_rockchip_ops = {
|
||||
.eqos_inval_desc = eqos_inval_desc_generic,
|
||||
.eqos_flush_desc = eqos_flush_desc_generic,
|
||||
.eqos_inval_buffer = eqos_inval_buffer_generic,
|
||||
.eqos_flush_buffer = eqos_flush_buffer_generic,
|
||||
.eqos_probe_resources = eqos_probe_resources_rk,
|
||||
.eqos_remove_resources = eqos_remove_resources_rk,
|
||||
.eqos_stop_resets = eqos_stop_resets_rk,
|
||||
.eqos_start_resets = eqos_start_resets_rk,
|
||||
.eqos_stop_clks = eqos_stop_clks_rk,
|
||||
.eqos_start_clks = eqos_start_clks_rk,
|
||||
.eqos_calibrate_pads = eqos_null_ops,
|
||||
.eqos_disable_calibration = eqos_null_ops,
|
||||
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_rk,
|
||||
.eqos_get_enetaddr = eqos_null_ops,
|
||||
.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_rk,
|
||||
};
|
||||
|
||||
struct eqos_config eqos_rockchip_config = {
|
||||
.reg_access_always_ok = false,
|
||||
.mdio_wait = 10,
|
||||
.swr_wait = 50,
|
||||
.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
|
||||
.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_100_150,
|
||||
.axi_bus_width = EQOS_AXI_WIDTH_64,
|
||||
.interface = dev_read_phy_mode,
|
||||
.ops = &eqos_rockchip_ops,
|
||||
};
|
||||
|
|
@ -18,6 +18,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/regulator.h>
|
||||
|
|
@ -43,6 +44,7 @@ struct rk_pcie {
|
|||
struct reset_ctl_bulk rsts;
|
||||
struct gpio_desc rst_gpio;
|
||||
u32 gen;
|
||||
u32 num_lanes;
|
||||
};
|
||||
|
||||
/* Parameters for the waiting for iATU enabled routine */
|
||||
|
|
@ -152,12 +154,13 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
|
|||
* rk_pcie_configure() - Configure link capabilities and speed
|
||||
*
|
||||
* @rk_pcie: Pointer to the PCI controller state
|
||||
* @cap_speed: The capabilities and speed to configure
|
||||
*
|
||||
* Configure the link capabilities and speed in the PCIe root complex.
|
||||
*/
|
||||
static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
|
||||
static void rk_pcie_configure(struct rk_pcie *pci)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
dw_pcie_dbi_write_enable(&pci->dw, true);
|
||||
|
||||
/* Disable BAR 0 and BAR 1 */
|
||||
|
|
@ -167,11 +170,49 @@ static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
|
|||
PCI_BASE_ADDRESS_1);
|
||||
|
||||
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
|
||||
TARGET_LINK_SPEED_MASK, cap_speed);
|
||||
TARGET_LINK_SPEED_MASK, pci->gen);
|
||||
|
||||
clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
|
||||
TARGET_LINK_SPEED_MASK, cap_speed);
|
||||
TARGET_LINK_SPEED_MASK, pci->gen);
|
||||
|
||||
/* Set the number of lanes */
|
||||
val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
|
||||
val &= ~PORT_LINK_FAST_LINK_MODE;
|
||||
val |= PORT_LINK_DLL_LINK_EN;
|
||||
val &= ~PORT_LINK_MODE_MASK;
|
||||
switch (pci->num_lanes) {
|
||||
case 1:
|
||||
val |= PORT_LINK_MODE_1_LANES;
|
||||
break;
|
||||
case 2:
|
||||
val |= PORT_LINK_MODE_2_LANES;
|
||||
break;
|
||||
case 4:
|
||||
val |= PORT_LINK_MODE_4_LANES;
|
||||
break;
|
||||
default:
|
||||
dev_err(pci->dw.dev, "num-lanes %u: invalid value\n", pci->num_lanes);
|
||||
goto out;
|
||||
}
|
||||
writel(val, pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
|
||||
|
||||
/* Set link width speed control register */
|
||||
val = readl(pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||||
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
||||
switch (pci->num_lanes) {
|
||||
case 1:
|
||||
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
|
||||
break;
|
||||
case 2:
|
||||
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
||||
break;
|
||||
case 4:
|
||||
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
|
||||
break;
|
||||
}
|
||||
writel(val, pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||||
|
||||
out:
|
||||
dw_pcie_dbi_write_enable(&pci->dw, false);
|
||||
}
|
||||
|
||||
|
|
@ -231,11 +272,10 @@ static int is_link_up(struct rk_pcie *priv)
|
|||
* rk_pcie_link_up() - Wait for the link to come up
|
||||
*
|
||||
* @rk_pcie: Pointer to the PCI controller state
|
||||
* @cap_speed: Desired link speed
|
||||
*
|
||||
* Return: 1 (true) for active line and negetive (false) for no link (timeout)
|
||||
*/
|
||||
static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
|
||||
static int rk_pcie_link_up(struct rk_pcie *priv)
|
||||
{
|
||||
int retries;
|
||||
|
||||
|
|
@ -245,7 +285,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
|
|||
}
|
||||
|
||||
/* DW pre link configurations */
|
||||
rk_pcie_configure(priv, cap_speed);
|
||||
rk_pcie_configure(priv);
|
||||
|
||||
rk_pcie_disable_ltssm(priv);
|
||||
rk_pcie_link_status_clear(priv);
|
||||
|
|
@ -341,7 +381,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
|
|||
rk_pcie_writel_apb(priv, 0x0, 0xf00040);
|
||||
pcie_dw_setup_host(&priv->dw);
|
||||
|
||||
ret = rk_pcie_link_up(priv, priv->gen);
|
||||
ret = rk_pcie_link_up(priv);
|
||||
if (ret < 0)
|
||||
goto err_link_up;
|
||||
|
||||
|
|
@ -419,6 +459,8 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
|
|||
priv->gen = dev_read_u32_default(dev, "max-link-speed",
|
||||
LINK_SPEED_GEN_3);
|
||||
|
||||
priv->num_lanes = dev_read_u32_default(dev, "num-lanes", 1);
|
||||
|
||||
return 0;
|
||||
|
||||
rockchip_pcie_parse_dt_err_phy_get_by_index:
|
||||
|
|
|
|||
|
|
@ -61,6 +61,8 @@ struct rockchip_combphy_grfcfg {
|
|||
struct combphy_reg pipe_con1_for_sata;
|
||||
struct combphy_reg pipe_sgmii_mac_sel;
|
||||
struct combphy_reg pipe_xpcs_phy_ready;
|
||||
struct combphy_reg pipe_pcie1l0_sel;
|
||||
struct combphy_reg pipe_pcie1l1_sel;
|
||||
struct combphy_reg u3otg0_port_en;
|
||||
struct combphy_reg u3otg1_port_en;
|
||||
};
|
||||
|
|
@ -435,6 +437,8 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
|||
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
||||
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
||||
param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
|
||||
param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
|
||||
break;
|
||||
case PHY_TYPE_USB3:
|
||||
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
|
|
@ -507,6 +511,8 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
|
|||
/* pipe-grf */
|
||||
.pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
|
||||
.pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
|
||||
.pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
|
||||
.pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
|
||||
};
|
||||
|
||||
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
|
||||
|
|
|
|||
|
|
@ -16,9 +16,27 @@
|
|||
#include <dm/device_compat.h>
|
||||
#include <dm/lists.h>
|
||||
|
||||
#define GRF_PCIE30PHY_CON1 0x4
|
||||
#define GRF_PCIE30PHY_CON6 0x18
|
||||
#define GRF_PCIE30PHY_CON9 0x24
|
||||
/* Register for RK3568 */
|
||||
#define GRF_PCIE30PHY_CON1 0x4
|
||||
#define GRF_PCIE30PHY_CON6 0x18
|
||||
#define GRF_PCIE30PHY_CON9 0x24
|
||||
#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
|
||||
#define GRF_PCIE30PHY_STATUS0 0x80
|
||||
#define GRF_PCIE30PHY_WR_EN (0xf << 16)
|
||||
#define SRAM_INIT_DONE(reg) (reg & BIT(14))
|
||||
|
||||
#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
|
||||
|
||||
/* Register for RK3588 */
|
||||
#define PHP_GRF_PCIESEL_CON 0x100
|
||||
#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
|
||||
#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
|
||||
#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
|
||||
#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
|
||||
|
||||
#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
|
||||
#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
|
||||
#define RK3588_LANE_AGGREGATION BIT(2)
|
||||
|
||||
/**
|
||||
* struct rockchip_p3phy_priv - RK DW PCIe PHY state
|
||||
|
|
@ -26,51 +44,144 @@
|
|||
* @mmio: The base address of PHY internal registers
|
||||
* @phy_grf: The regmap for controlling pipe signal
|
||||
* @p30phy: The reset signal for PHY
|
||||
* @ref_clk_m: The reference clock of M for PHY
|
||||
* @ref_clk_n: The reference clock of N for PHY
|
||||
* @pclk: The clock for accessing PHY blocks
|
||||
* @clks: The clocks for PHY
|
||||
* @num_lanes: The number of lane to controller mappings
|
||||
* @lanes: The lane to controller mapping
|
||||
*/
|
||||
struct rockchip_p3phy_priv {
|
||||
void __iomem *mmio;
|
||||
struct regmap *phy_grf;
|
||||
struct regmap *pipe_grf;
|
||||
struct reset_ctl p30phy;
|
||||
struct clk ref_clk_m;
|
||||
struct clk ref_clk_n;
|
||||
struct clk pclk;
|
||||
struct clk_bulk clks;
|
||||
int num_lanes;
|
||||
u32 lanes[4];
|
||||
};
|
||||
|
||||
static int rochchip_p3phy_init(struct phy *phy)
|
||||
struct rockchip_p3phy_ops {
|
||||
int (*phy_init)(struct phy *phy);
|
||||
};
|
||||
|
||||
static int rockchip_p3phy_rk3568_init(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
|
||||
bool bifurcation = false;
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(&priv->ref_clk_m);
|
||||
if (ret < 0 && ret != -ENOSYS)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&priv->ref_clk_n);
|
||||
if (ret < 0 && ret != -ENOSYS)
|
||||
goto err_ref;
|
||||
|
||||
ret = clk_enable(&priv->pclk);
|
||||
if (ret < 0 && ret != -ENOSYS)
|
||||
goto err_pclk;
|
||||
|
||||
reset_assert(&priv->p30phy);
|
||||
udelay(1);
|
||||
u32 reg;
|
||||
|
||||
/* Deassert PCIe PMA output clamp mode */
|
||||
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
|
||||
(0x1 << 15) | (0x1 << 31));
|
||||
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
|
||||
|
||||
for (int i = 0; i < priv->num_lanes; i++) {
|
||||
if (priv->lanes[i] > 1)
|
||||
bifurcation = true;
|
||||
}
|
||||
|
||||
/* Set bifurcation if needed, and it doesn't care RC/EP */
|
||||
if (bifurcation) {
|
||||
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
|
||||
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
|
||||
GRF_PCIE30PHY_DA_OCM);
|
||||
} else {
|
||||
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
|
||||
}
|
||||
|
||||
reset_deassert(&priv->p30phy);
|
||||
udelay(1);
|
||||
|
||||
return 0;
|
||||
err_pclk:
|
||||
clk_disable(&priv->ref_clk_n);
|
||||
err_ref:
|
||||
clk_disable(&priv->ref_clk_m);
|
||||
ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
GRF_PCIE30PHY_STATUS0,
|
||||
reg, SRAM_INIT_DONE(reg),
|
||||
0, 500);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "lock failed 0x%x\n", reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rockchip_p3phy_ops rk3568_ops = {
|
||||
.phy_init = rockchip_p3phy_rk3568_init,
|
||||
};
|
||||
|
||||
static int rockchip_p3phy_rk3588_init(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
|
||||
u32 reg = 0;
|
||||
u8 mode = 0;
|
||||
int ret;
|
||||
|
||||
/* Deassert PCIe PMA output clamp mode */
|
||||
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
|
||||
BIT(8) | BIT(24));
|
||||
|
||||
/* Set bifurcation if needed */
|
||||
for (int i = 0; i < priv->num_lanes; i++) {
|
||||
if (!priv->lanes[i])
|
||||
mode |= (BIT(i) << 3);
|
||||
|
||||
if (priv->lanes[i] > 1)
|
||||
mode |= (BIT(i) >> 1);
|
||||
}
|
||||
|
||||
if (!mode) {
|
||||
reg = RK3588_LANE_AGGREGATION;
|
||||
} else {
|
||||
if (mode & (BIT(0) | BIT(1)))
|
||||
reg |= RK3588_BIFURCATION_LANE_0_1;
|
||||
|
||||
if (mode & (BIT(2) | BIT(3)))
|
||||
reg |= RK3588_BIFURCATION_LANE_2_3;
|
||||
}
|
||||
|
||||
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
|
||||
(0x7 << 16) | reg);
|
||||
|
||||
/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
|
||||
reg = (mode & (BIT(6) | BIT(7))) >> 6;
|
||||
if (reg)
|
||||
regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
|
||||
(reg << 16) | reg);
|
||||
|
||||
reset_deassert(&priv->p30phy);
|
||||
udelay(1);
|
||||
|
||||
ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
|
||||
reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
0, 500);
|
||||
ret |= regmap_read_poll_timeout(priv->phy_grf,
|
||||
RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
|
||||
reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
0, 500);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "lock failed 0x%x\n", reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rockchip_p3phy_ops rk3588_ops = {
|
||||
.phy_init = rockchip_p3phy_rk3588_init,
|
||||
};
|
||||
|
||||
static int rochchip_p3phy_init(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_ops *ops =
|
||||
(struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev);
|
||||
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_enable_bulk(&priv->clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reset_assert(&priv->p30phy);
|
||||
udelay(1);
|
||||
|
||||
ret = ops->phy_init(phy);
|
||||
if (ret)
|
||||
clk_disable_bulk(&priv->clks);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -79,9 +190,7 @@ static int rochchip_p3phy_exit(struct phy *phy)
|
|||
{
|
||||
struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
|
||||
|
||||
clk_disable(&priv->ref_clk_m);
|
||||
clk_disable(&priv->ref_clk_n);
|
||||
clk_disable(&priv->pclk);
|
||||
clk_disable_bulk(&priv->clks);
|
||||
reset_assert(&priv->p30phy);
|
||||
|
||||
return 0;
|
||||
|
|
@ -90,48 +199,54 @@ static int rochchip_p3phy_exit(struct phy *phy)
|
|||
static int rockchip_p3phy_probe(struct udevice *dev)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
|
||||
struct udevice *syscon;
|
||||
int ret;
|
||||
|
||||
priv->mmio = dev_read_addr_ptr(dev);
|
||||
if (!priv->mmio)
|
||||
return -EINVAL;
|
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
|
||||
"rockchip,phy-grf", &syscon);
|
||||
if (ret) {
|
||||
pr_err("unable to find syscon device for rockchip,phy-grf\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv->phy_grf = syscon_get_regmap(syscon);
|
||||
priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,phy-grf");
|
||||
if (IS_ERR(priv->phy_grf)) {
|
||||
dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
|
||||
return PTR_ERR(priv->phy_grf);
|
||||
}
|
||||
|
||||
if (device_is_compatible(dev, "rockchip,rk3588-pcie3-phy")) {
|
||||
priv->pipe_grf =
|
||||
syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
|
||||
if (IS_ERR(priv->pipe_grf)) {
|
||||
dev_err(dev, "failed to find rockchip,pipe_grf regmap\n");
|
||||
return PTR_ERR(priv->pipe_grf);
|
||||
}
|
||||
}
|
||||
|
||||
ret = dev_read_size(dev, "data-lanes");
|
||||
if (ret > 0) {
|
||||
priv->num_lanes = ret / sizeof(u32);
|
||||
if (priv->num_lanes < 2 ||
|
||||
priv->num_lanes > ARRAY_SIZE(priv->lanes)) {
|
||||
dev_err(dev, "unsupported data-lanes property size\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = dev_read_u32_array(dev, "data-lanes", priv->lanes,
|
||||
priv->num_lanes);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to read data-lanes property\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = reset_get_by_name(dev, "phy", &priv->p30phy);
|
||||
if (ret) {
|
||||
dev_err(dev, "no phy reset control specified\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m);
|
||||
ret = clk_get_bulk(dev, &priv->clks);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find ref clock M\n");
|
||||
return PTR_ERR(&priv->ref_clk_m);
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find ref clock N\n");
|
||||
return PTR_ERR(&priv->ref_clk_n);
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "pclk", &priv->pclk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to find pclk\n");
|
||||
return PTR_ERR(&priv->pclk);
|
||||
dev_err(dev, "failed to get clocks\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -143,7 +258,14 @@ static struct phy_ops rochchip_p3phy_ops = {
|
|||
};
|
||||
|
||||
static const struct udevice_id rockchip_p3phy_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3568-pcie3-phy" },
|
||||
{
|
||||
.compatible = "rockchip,rk3568-pcie3-phy",
|
||||
.data = (ulong)&rk3568_ops,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3588-pcie3-phy",
|
||||
.data = (ulong)&rk3588_ops,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -233,6 +233,7 @@ config PMIC_QCOM
|
|||
|
||||
config PMIC_RK8XX
|
||||
bool "Enable support for Rockchip PMIC RK8XX"
|
||||
select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF
|
||||
---help---
|
||||
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,
|
||||
an RTC and two low Rds (resistance (drain to source)) switches. It is
|
||||
|
|
|
|||
|
|
@ -156,6 +156,10 @@ static int rk8xx_bind(struct udevice *dev)
|
|||
if (!children)
|
||||
debug("%s: %s - no child found\n", __func__, dev->name);
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
|
||||
IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
|
||||
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
|
||||
|
||||
/* Always return success for this device */
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -236,14 +240,16 @@ static int rk8xx_probe(struct udevice *dev)
|
|||
pmic_reg_read(dev, init_data[i].reg));
|
||||
}
|
||||
|
||||
printf("PMIC: RK%x ", show_variant);
|
||||
if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
printf("PMIC: RK%x ", show_variant);
|
||||
if (on_source && off_source)
|
||||
printf("(on=0x%02x, off=0x%02x)",
|
||||
pmic_reg_read(dev, on_source),
|
||||
pmic_reg_read(dev, off_source));
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
if (on_source && off_source)
|
||||
printf("(on=0x%02x, off=0x%02x)",
|
||||
pmic_reg_read(dev, on_source),
|
||||
pmic_reg_read(dev, off_source));
|
||||
printf("\n");
|
||||
if (CONFIG_IS_ENABLED(ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
|
||||
if (IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
|
||||
rk8xx_off_for_plugin(dev);
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -293,6 +293,9 @@ int regulator_autoset(struct udevice *dev)
|
|||
|
||||
uc_pdata = dev_get_uclass_plat(dev);
|
||||
|
||||
if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_DONE)
|
||||
return -EALREADY;
|
||||
|
||||
ret = regulator_set_suspend_enable(dev, uc_pdata->suspend_on);
|
||||
if (ret == -ENOSYS)
|
||||
ret = 0;
|
||||
|
|
@ -306,11 +309,15 @@ int regulator_autoset(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (!uc_pdata->always_on && !uc_pdata->boot_on)
|
||||
return -EMEDIUMTYPE;
|
||||
if (!uc_pdata->always_on && !uc_pdata->boot_on) {
|
||||
ret = -EMEDIUMTYPE;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (uc_pdata->type == REGULATOR_TYPE_FIXED)
|
||||
return regulator_set_enable(dev, true);
|
||||
if (uc_pdata->type == REGULATOR_TYPE_FIXED) {
|
||||
ret = regulator_set_enable(dev, true);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UV)
|
||||
ret = regulator_set_value(dev, uc_pdata->min_uV);
|
||||
|
|
@ -322,6 +329,9 @@ int regulator_autoset(struct udevice *dev)
|
|||
if (!ret)
|
||||
ret = regulator_set_enable(dev, true);
|
||||
|
||||
out:
|
||||
uc_pdata->flags |= REGULATOR_FLAG_AUTOSET_DONE;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -88,62 +88,63 @@ struct rk8xx_reg_info {
|
|||
u8 config_reg;
|
||||
u8 vsel_mask;
|
||||
u8 min_sel;
|
||||
u8 max_sel;
|
||||
};
|
||||
|
||||
static const struct rk8xx_reg_info rk808_buck[] = {
|
||||
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, },
|
||||
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, },
|
||||
{ 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK808_BUCK_VSEL_MASK, },
|
||||
{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, },
|
||||
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f },
|
||||
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK808_BUCK_VSEL_MASK, 0x00, 0x3f },
|
||||
{ NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA },
|
||||
{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK808_BUCK4_VSEL_MASK, 0x00, 0x0f },
|
||||
};
|
||||
|
||||
static const struct rk8xx_reg_info rk816_buck[] = {
|
||||
/* buck 1 */
|
||||
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
|
||||
{ 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
|
||||
{ 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
|
||||
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b },
|
||||
{ 1800000, 200000, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e },
|
||||
{ 2300000, 0, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f },
|
||||
/* buck 2 */
|
||||
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, },
|
||||
{ 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, },
|
||||
{ 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, },
|
||||
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3b },
|
||||
{ 1800000, 200000, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3c, 0x3e },
|
||||
{ 2300000, 0, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x3f, 0x3f },
|
||||
/* buck 3 */
|
||||
{ 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
|
||||
{ NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA },
|
||||
/* buck 4 */
|
||||
{ 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
|
||||
{ 800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, 0x00, 0x1f },
|
||||
};
|
||||
|
||||
static const struct rk8xx_reg_info rk809_buck5[] = {
|
||||
/* buck 5 */
|
||||
{ 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, },
|
||||
{ 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, },
|
||||
{ 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, },
|
||||
{ 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, },
|
||||
{ 1500000, 0, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x00, 0x00 },
|
||||
{ 1800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x01, 0x03 },
|
||||
{ 2800000, 200000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x04, 0x05 },
|
||||
{ 3300000, 300000, RK809_BUCK5_CONFIG(0), RK809_BUCK5_CONFIG(1), NA, RK809_BUCK5_VSEL_MASK, 0x06, 0x07 },
|
||||
};
|
||||
|
||||
static const struct rk8xx_reg_info rk817_buck[] = {
|
||||
/* buck 1 */
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, },
|
||||
{ 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, },
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x50, 0x58 },
|
||||
{ 2400000, 0, RK817_BUCK_ON_VSEL(1), RK817_BUCK_SLP_VSEL(1), RK817_BUCK_CONFIG(1), RK817_BUCK_VSEL_MASK, 0x59, 0x7f },
|
||||
/* buck 2 */
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, },
|
||||
{ 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, },
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x50, 0x58 },
|
||||
{ 2400000, 0, RK817_BUCK_ON_VSEL(2), RK817_BUCK_SLP_VSEL(2), RK817_BUCK_CONFIG(2), RK817_BUCK_VSEL_MASK, 0x59, 0x7f },
|
||||
/* buck 3 */
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, },
|
||||
{ 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, },
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x50, 0x58 },
|
||||
{ 2400000, 0, RK817_BUCK_ON_VSEL(3), RK817_BUCK_SLP_VSEL(3), RK817_BUCK_CONFIG(3), RK817_BUCK_VSEL_MASK, 0x59, 0x7f },
|
||||
/* buck 4 */
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, },
|
||||
{ 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, },
|
||||
{ 500000, 12500, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x00, 0x4f },
|
||||
{ 1500000, 100000, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x50, 0x62 },
|
||||
{ 3400000, 0, RK817_BUCK_ON_VSEL(4), RK817_BUCK_SLP_VSEL(4), RK817_BUCK_CONFIG(4), RK817_BUCK_VSEL_MASK, 0x63, 0x7f },
|
||||
};
|
||||
|
||||
static const struct rk8xx_reg_info rk818_buck[] = {
|
||||
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, },
|
||||
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, },
|
||||
{ 712500, 12500, NA, NA, REG_BUCK3_CONFIG, RK818_BUCK_VSEL_MASK, },
|
||||
{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, },
|
||||
{ 712500, 12500, REG_BUCK1_ON_VSEL, REG_BUCK1_SLP_VSEL, REG_BUCK1_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f },
|
||||
{ 712500, 12500, REG_BUCK2_ON_VSEL, REG_BUCK2_SLP_VSEL, REG_BUCK2_CONFIG, RK818_BUCK_VSEL_MASK, 0x00, 0x3f },
|
||||
{ NA, NA, NA, NA, REG_BUCK3_CONFIG, NA, NA, NA },
|
||||
{ 1800000, 100000, REG_BUCK4_ON_VSEL, REG_BUCK4_SLP_VSEL, REG_BUCK4_CONFIG, RK818_BUCK4_VSEL_MASK, 0x00, 0x1f },
|
||||
};
|
||||
|
||||
#ifdef ENABLE_DRIVER
|
||||
|
|
@ -706,7 +707,6 @@ static int _ldo_get_suspend_enable(struct udevice *pmic, int ldo)
|
|||
static int buck_get_value(struct udevice *dev)
|
||||
{
|
||||
int buck = dev->driver_data - 1;
|
||||
/* We assume level-1 voltage is enough for usage in U-Boot */
|
||||
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
|
||||
int mask = info->vsel_mask;
|
||||
int ret, val;
|
||||
|
|
@ -717,9 +717,12 @@ static int buck_get_value(struct udevice *dev)
|
|||
ret = pmic_reg_read(dev->parent, info->vsel_reg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
val = ret & mask;
|
||||
|
||||
return info->min_uv + val * info->step_uv;
|
||||
val = ret & mask;
|
||||
while (val > info->max_sel)
|
||||
info++;
|
||||
|
||||
return info->min_uv + (val - info->min_sel) * info->step_uv;
|
||||
}
|
||||
|
||||
static int buck_set_value(struct udevice *dev, int uvolt)
|
||||
|
|
@ -732,7 +735,6 @@ static int buck_set_value(struct udevice *dev, int uvolt)
|
|||
static int buck_get_suspend_value(struct udevice *dev)
|
||||
{
|
||||
int buck = dev->driver_data - 1;
|
||||
/* We assume level-1 voltage is enough for usage in U-Boot */
|
||||
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck, 0);
|
||||
int mask = info->vsel_mask;
|
||||
int ret, val;
|
||||
|
|
@ -745,8 +747,10 @@ static int buck_get_suspend_value(struct udevice *dev)
|
|||
return ret;
|
||||
|
||||
val = ret & mask;
|
||||
while (val > info->max_sel)
|
||||
info++;
|
||||
|
||||
return info->min_uv + val * info->step_uv;
|
||||
return info->min_uv + (val - info->min_sel) * info->step_uv;
|
||||
}
|
||||
|
||||
static int buck_set_suspend_value(struct udevice *dev, int uvolt)
|
||||
|
|
@ -1028,6 +1032,25 @@ static int switch_get_suspend_enable(struct udevice *dev)
|
|||
*/
|
||||
static int switch_get_value(struct udevice *dev)
|
||||
{
|
||||
static const char * const supply_name_rk809[] = {
|
||||
"vcc9-supply",
|
||||
"vcc8-supply",
|
||||
};
|
||||
struct rk8xx_priv *priv = dev_get_priv(dev->parent);
|
||||
struct udevice *supply;
|
||||
int id = dev->driver_data - 1;
|
||||
|
||||
if (!switch_get_enable(dev))
|
||||
return 0;
|
||||
|
||||
if (priv->variant == RK809_ID) {
|
||||
if (!uclass_get_device_by_phandle(UCLASS_REGULATOR,
|
||||
dev->parent,
|
||||
supply_name_rk809[id],
|
||||
&supply))
|
||||
return regulator_get_value(supply);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -16,11 +16,13 @@
|
|||
#define ENV_MEM_LAYOUT_SETTINGS \
|
||||
"scriptaddr=0x00500000\0" \
|
||||
"pxefile_addr_r=0x00600000\0" \
|
||||
"fdt_addr_r=0x02800000\0" \
|
||||
"fdt_addr_r=0x03e00000\0" \
|
||||
"fdtoverlay_addr_r=0x03f00000\0" \
|
||||
"kernel_addr_r=0x00680000\0" \
|
||||
"ramdisk_addr_r=0x04000000\0"
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
ENV_MEM_LAYOUT_SETTINGS \
|
||||
"partitions=" PARTS_DEFAULT \
|
||||
ROCKCHIP_DEVICE_SETTINGS \
|
||||
|
|
|
|||
20
include/dt-bindings/ata/ahci.h
Normal file
20
include/dt-bindings/ata/ahci.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* This header provides constants for most AHCI bindings.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_ATA_AHCI_H
|
||||
#define _DT_BINDINGS_ATA_AHCI_H
|
||||
|
||||
/* Host Bus Adapter generic platform capabilities */
|
||||
#define HBA_SSS (1 << 27)
|
||||
#define HBA_SMPS (1 << 28)
|
||||
|
||||
/* Host Bus Adapter port-specific platform capabilities */
|
||||
#define HBA_PORT_HPCP (1 << 18)
|
||||
#define HBA_PORT_MPSP (1 << 19)
|
||||
#define HBA_PORT_CPD (1 << 20)
|
||||
#define HBA_PORT_ESP (1 << 21)
|
||||
#define HBA_PORT_FBSCP (1 << 22)
|
||||
|
||||
#endif
|
||||
|
|
@ -134,6 +134,7 @@ struct dm_regulator_mode {
|
|||
enum regulator_flag {
|
||||
REGULATOR_FLAG_AUTOSET_UV = 1 << 0,
|
||||
REGULATOR_FLAG_AUTOSET_UA = 1 << 1,
|
||||
REGULATOR_FLAG_AUTOSET_DONE = 1 << 2,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -931,4 +931,13 @@ void spl_save_restore_data(void);
|
|||
int spl_load_fit_image(struct spl_image_info *spl_image,
|
||||
const struct legacy_img_hdr *header);
|
||||
|
||||
/*
|
||||
* spl_decompression_enabled() - check decompression support is enabled for SPL build
|
||||
*
|
||||
* Returns true if decompression support is enabled, else False
|
||||
*/
|
||||
static inline bool spl_decompression_enabled(void)
|
||||
{
|
||||
return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user