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ARM: zynq: Add DTSes for mini qspi configurations

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Mini U-Boot is running out of OCM and it's only purpose is to program non
volatile memories. There are different configurations which qspi can be
that's why describe them via DT.
DT binding is already approved that's why there is no reason not to add it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/28b3cdd7e91b2b4c3c36d0bf65aa5bac042f248c.1698329087.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-10-26 16:04:49 +02:00
parent 1cd59c571c
commit da10dd10e0
7 changed files with 126 additions and 0 deletions
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6
arch/arm/dts/Makefile
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@ -376,6 +376,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cse-nand.dtb \
zynq-cse-nor.dtb \
zynq-cse-qspi-single.dtb \
zynq-cse-qspi-parallel.dtb \
zynq-cse-qspi-stacked.dtb \
zynq-cse-qspi-x1-single.dtb \
zynq-cse-qspi-x1-stacked.dtb \
zynq-cse-qspi-x2-single.dtb \
zynq-cse-qspi-x2-stacked.dtb \
zynq-dlc20-rev1.0.dtb \
zynq-microzed.dtb \
zynq-minized.dtb \

22
arch/arm/dts/zynq-cse-qspi-parallel.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI Quad Parallel DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI PARALLEL Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <4>;
};

22
arch/arm/dts/zynq-cse-qspi-stacked.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI Quad Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI STACKED Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <4>;
};

16
arch/arm/dts/zynq-cse-qspi-x1-single.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x1 Single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X1 SINGLE Board";
};
&flash0 {
spi-rx-bus-width = <1>;
};

22
arch/arm/dts/zynq-cse-qspi-x1-stacked.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x1 Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X1 STACKED Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <1>;
};

16
arch/arm/dts/zynq-cse-qspi-x2-single.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x2 Single DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X2 SINGLE Board";
};
&flash0 {
spi-rx-bus-width = <2>;
};

22
arch/arm/dts/zynq-cse-qspi-x2-stacked.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx CSE QSPI x2 Stacked DTS
*
* Copyright (C) 2015 - 2017 Xilinx, Inc.
*/
#include "zynq-cse-qspi.dtsi"
/ {
model = "Zynq CSE QSPI X2 STACKED Board";
};
&qspi {
num-cs = <2>;
};
&flash0 {
reg = <0>, <1>;
stacked-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
spi-rx-bus-width = <2>;
};