board: mediatek: add MT7981 reference boards
This patch adds general board files based on MT7981 SoCs. MT7981 uses one mmc controller for booting from both SD and eMMC, and the pins of mmc controller are also shared with spi controller. So three configs are need for these boot types: 1. mt7981_rfb_defconfig - SPI-NOR and SPI-NAND 2. mt7981_emmc_rfb_defconfig - eMMC only 3. mt7981_sd_rfb_defconfig - SD only Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
parent
389ba6986b
commit
e053ccf6ef
|
|
@ -1235,6 +1235,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
|||
mt7622-bananapi-bpi-r64.dtb \
|
||||
mt7623n-bananapi-bpi-r2.dtb \
|
||||
mt7629-rfb.dtb \
|
||||
mt7981-rfb.dtb \
|
||||
mt7981-emmc-rfb.dtb \
|
||||
mt7981-sd-rfb.dtb \
|
||||
mt7986a-rfb.dtb \
|
||||
mt7986b-rfb.dtb \
|
||||
mt7986a-sd-rfb.dtb \
|
||||
|
|
|
|||
139
arch/arm/dts/mt7981-emmc-rfb.dts
Normal file
139
arch/arm/dts/mt7981-emmc-rfb.dts
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7981.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mt7981-rfb";
|
||||
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
tick-timer = &timer0;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
mediatek,gmac-id = <0>;
|
||||
phy-mode = "sgmii";
|
||||
mediatek,switch = "mt7531";
|
||||
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
spic_pins: spi1-pins-func-1 {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi1_1";
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: spi1-pins-func-3 {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart1_2";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0 */
|
||||
one_pwm_pins: one-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0 and pin14 as pwm1 */
|
||||
two_pwm_pins: two-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1", "pwm1_0";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
|
||||
three_pwm_pins: three-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1", "pwm1_0", "pwm2";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_default: mmc0default {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "emmc_45";
|
||||
};
|
||||
conf-cmd-dat {
|
||||
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
|
||||
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
|
||||
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
conf-clk {
|
||||
pins = "SPI1_CS";
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
conf-rst {
|
||||
pins = "PWM0";
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&two_pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
bus-width = <8>;
|
||||
max-frequency = <52000000>;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
173
arch/arm/dts/mt7981-rfb.dts
Normal file
173
arch/arm/dts/mt7981-rfb.dts
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7981.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mt7981-rfb";
|
||||
compatible = "mediatek,mt7981", "mediatek,mt7981-rfb";
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
tick-timer = &timer0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
mediatek,gmac-id = <0>;
|
||||
phy-mode = "sgmii";
|
||||
mediatek,switch = "mt7531";
|
||||
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
spi_flash_pins: spi0-pins-func-1 {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
|
||||
conf-pu {
|
||||
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
||||
};
|
||||
|
||||
conf-pd {
|
||||
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2_flash_pins: spi2-spi2-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi2", "spi2_wp_hold";
|
||||
};
|
||||
|
||||
conf-pu {
|
||||
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
|
||||
};
|
||||
|
||||
conf-pd {
|
||||
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
|
||||
};
|
||||
};
|
||||
|
||||
spic_pins: spi1-pins-func-1 {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi1_1";
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: spi1-pins-func-3 {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart1_2";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0 */
|
||||
one_pwm_pins: one-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0 and pin14 as pwm1 */
|
||||
two_pwm_pins: two-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1", "pwm1_0";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
|
||||
three_pwm_pins: three-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1", "pwm1_0", "pwm2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
support_quad;
|
||||
tick_dly = <2>;
|
||||
sample_sel = <0>;
|
||||
|
||||
spi_nand@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_flash_pins>;
|
||||
status = "okay";
|
||||
must_tx;
|
||||
enhance_timing;
|
||||
dma_ext;
|
||||
ipm_design;
|
||||
support_quad;
|
||||
tick_dly = <2>;
|
||||
sample_sel = <0>;
|
||||
|
||||
spi_nor@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&two_pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
139
arch/arm/dts/mt7981-sd-rfb.dts
Normal file
139
arch/arm/dts/mt7981-sd-rfb.dts
Normal file
|
|
@ -0,0 +1,139 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7981.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
model = "mt7981-rfb";
|
||||
compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb";
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
tick-timer = &timer0;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
mediatek,gmac-id = <0>;
|
||||
phy-mode = "sgmii";
|
||||
mediatek,switch = "mt7531";
|
||||
reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
spic_pins: spi1-pins-func-1 {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi1_1";
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: spi1-pins-func-3 {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart1_2";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0 */
|
||||
one_pwm_pins: one-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0 and pin14 as pwm1 */
|
||||
two_pwm_pins: two-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1", "pwm1_0";
|
||||
};
|
||||
};
|
||||
|
||||
/* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
|
||||
three_pwm_pins: three-pwm-pins {
|
||||
mux {
|
||||
function = "pwm";
|
||||
groups = "pwm0_1", "pwm1_0", "pwm2";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_default: mmc0default {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "emmc_45";
|
||||
};
|
||||
conf-cmd-dat {
|
||||
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
|
||||
"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
|
||||
"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
conf-clk {
|
||||
pins = "SPI1_CS";
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
||||
};
|
||||
conf-rst {
|
||||
pins = "PWM0";
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&two_pwm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
bus-width = <4>;
|
||||
max-frequency = <52000000>;
|
||||
cap-sd-highspeed;
|
||||
r_smpl = <0>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
10
board/mediatek/mt7981/MAINTAINERS
Normal file
10
board/mediatek/mt7981/MAINTAINERS
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
MT7981
|
||||
M: Sam Shih <sam.shih@mediatek.com>
|
||||
S: Maintained
|
||||
F: board/mediatek/mt7981
|
||||
F: include/configs/mt7981.h
|
||||
F: configs/mt7981_emmc_rfb_defconfig
|
||||
F: configs/mt7981_rfb_defconfig
|
||||
F: configs/mt7981_sd_rfb_defconfig
|
||||
F: configs/mt7981_spim_nand_rfb_defconfig
|
||||
F: configs/mt7981_spim_nor_rfb_defconfig
|
||||
3
board/mediatek/mt7981/Makefile
Normal file
3
board/mediatek/mt7981/Makefile
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
obj-y += mt7981_rfb.o
|
||||
10
board/mediatek/mt7981/mt7981_rfb.c
Normal file
10
board/mediatek/mt7981/mt7981_rfb.c
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
64
configs/mt7981_emmc_rfb_defconfig
Normal file
64
configs/mt7981_emmc_rfb_defconfig
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x80000
|
||||
CONFIG_ENV_OFFSET=0x300000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-emmc-rfb"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_GPT_RENAME=y
|
||||
CONFIG_CMD_LSBLK=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
69
configs/mt7981_rfb_defconfig
Normal file
69
configs/mt7981_rfb_defconfig
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_SF_TEST=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_HAVE_BLOCK_DEVICE=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_XMC=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_SPI_FLASH_MTD=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MTK_SPIM=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
64
configs/mt7981_sd_rfb_defconfig
Normal file
64
configs/mt7981_sd_rfb_defconfig
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x80000
|
||||
CONFIG_ENV_OFFSET=0x300000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7981-sd-rfb"
|
||||
CONFIG_TARGET_MT7981=y
|
||||
CONFIG_DEBUG_UART_BASE=0x11002000
|
||||
CONFIG_DEBUG_UART_CLOCK=40000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x46000000
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_AUTOBOOT is not set
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
CONFIG_LOG=y
|
||||
CONFIG_SYS_PROMPT="MT7981> "
|
||||
CONFIG_SYS_CBSIZE=512
|
||||
CONFIG_SYS_PBSIZE=1049
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_UNLZ4 is not set
|
||||
# CONFIG_CMD_UNZIP is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_GPT_RENAME=y
|
||||
CONFIG_CMD_LSBLK=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_SMC=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_PARTITION_TYPE_GUID=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_MMC_HS200_SUPPORT=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MEDIATEK_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_MTK_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MTK_SERIAL=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_HEXDUMP=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
25
include/configs/mt7981.h
Normal file
25
include/configs/mt7981.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Configuration for MediaTek MT7981 SoC
|
||||
*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef __MT7981_H
|
||||
#define __MT7981_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
|
||||
|
||||
/* Uboot definition */
|
||||
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* SPL -> Uboot */
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
/* DRAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user