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CONFIG_SYS_CLK_FREQ: Consistently be static or get_board_sys_clk()

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This CONFIG option is used in one of two ways.  The first way is that it
is defined to a static value, of an unsigned long size.  The second way
is that it is defined to something, typically a function, to determine
this value at run time.

However, in a few cases that function returns a static value.  Change
that to using the static value directly.

In the case of using something at run time, convert everything to using
a function of the same name and prototype.  This will allow for further
cleanups.

Finally, we have a few cases where the function is just not used, so
drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-12-14 13:36:39 -05:00
parent 0abfcf2fd3
commit e4c3ce7e28
35 changed files with 59 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/mach-davinci/cpu.c
View File

@ -91,3 +91,8 @@ int set_cpu_clk_info(void)
gd->bd->bi_dsp_freq = 0;
return 0;
}
unsigned long get_board_sys_clk(void)
{
return clk_get(DAVINCI_ARM_CLKID);
}

12
board/cadence/xtfpga/xtfpga.c
View File

@ -49,7 +49,7 @@ int checkboard(void)
return 0;
}
int board_postclk_init(void)
unsigned long get_board_sys_clk(void)
{
/*
* Obtain CPU clock frequency from board and cache in global
@ -58,11 +58,17 @@ int board_postclk_init(void)
*/
#ifdef CONFIG_SYS_FPGAREG_FREQ
gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
#else
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
gd->cpu_clk = 50000000UL;
return 50000000;
#endif
}
int board_postclk_init(void)
{
gd->cpu_clk = get_board_sys_clk();
return 0;
}

2
board/freescale/common/cadmus.c
View File

@ -37,7 +37,7 @@ get_board_version(void)
unsigned long
get_clock_freq(void)
get_board_sys_clk(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;

2
board/freescale/common/cadmus.h
View File

@ -19,7 +19,7 @@ extern unsigned int get_board_version(void);
/*
* Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
*/
extern unsigned long get_clock_freq(void);
extern unsigned long get_board_sys_clk(void);
/*

2
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -102,6 +102,7 @@ int checkboard(void)
return 0;
}
#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@ -126,6 +127,7 @@ unsigned long get_board_sys_clk(void)
}
return 66666666;
}
#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)

2
board/freescale/ls1088a/ls1088a.c
View File

@ -374,6 +374,7 @@ bool if_board_diff_clk(void)
#endif
}
#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@ -397,6 +398,7 @@ unsigned long get_board_sys_clk(void)
return 66666666;
}
#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)

2
board/freescale/p2041rdb/p2041rdb.c
View File

@ -148,7 +148,7 @@ int board_early_init_r(void)
return 0;
}
unsigned long get_board_sys_clk(unsigned long dummy)
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = CPLD_READ(sysclk_sw1);

7
board/freescale/t102xrdb/spl.c
View File

@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
@ -74,7 +69,7 @@ void board_init_f(ulong bootflag)
#endif
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;

5
board/freescale/t102xrdb/t102xrdb.c
View File

@ -162,11 +162,6 @@ int board_early_init_r(void)
return 0;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{

7
board/freescale/t104xrdb/spl.c
View File

@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{
@ -73,7 +68,7 @@ void board_init_f(ulong bootflag)
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;

7
board/freescale/t208xrdb/spl.c
View File

@ -24,11 +24,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
@ -43,7 +38,7 @@ void board_init_f(ulong bootflag)
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;

5
board/freescale/t208xrdb/t208xrdb.c
View File

@ -109,11 +109,6 @@ int board_early_init_r(void)
return 0;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
int misc_init_r(void)
{
u8 reg;

7
board/freescale/t4rdb/spl.c
View File

@ -30,11 +30,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
@ -52,7 +47,7 @@ void board_init_f(ulong bootflag)
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;

5
board/keymile/kmcent2/kmcent2.c
View File

@ -181,11 +181,6 @@ unsigned long get_serial_clock(unsigned long dummy)
return (gd->bus_clk / 2);
}
unsigned long get_board_sys_clk(unsigned long dummy)
{
return 66666666;
}
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */

6
board/xes/common/fsl_8xxx_clk.c
View File

@ -9,7 +9,7 @@
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
unsigned long get_board_sys_clk(ulong dummy)
unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -33,13 +33,13 @@ unsigned long get_board_sys_clk(ulong dummy)
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
* Note: 86xx doesn't support asynchronous DDR clk
*/
unsigned long get_board_ddr_clk(ulong dummy)
unsigned long get_board_ddr_clk(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
return get_board_sys_clk();
#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)

4
include/configs/MPC8548CDS.h
View File

@ -24,9 +24,9 @@
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
extern unsigned long get_clock_freq(void);
extern unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.

4
include/configs/P2041RDB.h
View File

@ -49,10 +49,10 @@
#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(unsigned long dummy);
unsigned long get_board_sys_clk(void);
#include <linux/stringify.h>
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
/*
* These can be toggled for performance analysis, otherwise use default.

4
include/configs/T102xRDB.h
View File

@ -115,10 +115,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
/*

4
include/configs/T208xRDB.h
View File

@ -88,10 +88,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ 66660000
/*

4
include/configs/T4240RDB.h
View File

@ -226,10 +226,6 @@
#define CONFIG_SYS_CLK_FREQ 66666666
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
/*
* DDR Setup
*/

3
include/configs/alt.h
View File

@ -34,8 +34,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \

3
include/configs/blanche.h
View File

@ -45,8 +45,7 @@
#endif
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
/* ENV setting */

2
include/configs/condor.h
View File

@ -27,7 +27,7 @@
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
#define CONFIG_SYS_CLK_FREQ 33333333
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */

5
include/configs/da850evm.h
View File

@ -17,8 +17,11 @@
/*
* SoC Configuration
*/
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)

2
include/configs/eagle.h
View File

@ -18,7 +18,7 @@
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
#define CONFIG_SYS_CLK_FREQ 33333333
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */

2
include/configs/falcon.h
View File

@ -26,7 +26,7 @@
/* Board Clock */
/* XTAL_CLK : 16.66MHz */
#define CONFIG_SYS_CLK_FREQ 16666666u
#define CONFIG_SYS_CLK_FREQ 16666666
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */

3
include/configs/gose.h
View File

@ -30,8 +30,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"

3
include/configs/koelsch.h
View File

@ -30,8 +30,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"

3
include/configs/lager.h
View File

@ -31,8 +31,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"

5
include/configs/legoev3.h
View File

@ -17,8 +17,11 @@
/*
* SoC Configuration
*/
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)

5
include/configs/omapl138_lcdk.h
View File

@ -17,7 +17,10 @@
/*
* SoC Configuration
*/
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)

3
include/configs/porter.h
View File

@ -35,8 +35,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"

3
include/configs/silk.h
View File

@ -35,8 +35,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"

3
include/configs/stout.h
View File

@ -39,8 +39,7 @@
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
#define RMOBILE_XTAL_CLK 20000000u
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"

5
include/configs/xtfpga.h
View File

@ -23,7 +23,10 @@
#define CONFIG_XTFPGA
/* FPGA CPU freq after init */
#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk)
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
/*===================*/
/* RAM Layout */