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Merge branch '2022-07-07-Kconfig-migrations-dead-code-removal' into next

Browse Source 
- Migrate more CONFIG options to Kconfig and remove some unused code
  while we're at it.
This commit is contained in:
Tom Rini 2022-07-07 14:12:07 -04:00
commit ea92f95d63
768 changed files with 948 additions and 7942 deletions
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7
MAINTAINERS
View File

@ -348,13 +348,6 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/serial/serial_mvebu_a3700.c
ARM MARVELL PXA
M: Marek Vasut <marex@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>

26
README
View File

@ -371,10 +371,6 @@ The following options need to be configured:
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
CONFIG_SYS_CPC_REINIT_F
This CONFIG is defined when the CPC is configured as SRAM at the
time of U-Boot entry and is required to be re-initialized.
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@ -850,13 +846,6 @@ The following options need to be configured:
the appropriate value in Hz.
- MMC Support:
The MMC controller on the Intel PXA is supported. To
enable this define CONFIG_MMC. The MMC can be
accessed from the boot prompt by mapping the device
to physical memory similar to flash. Command line is
enabled with CONFIG_CMD_MMC. The MMC driver also works with
the FAT fs. This is enabled with CONFIG_CMD_FAT.
CONFIG_SH_MMCIF
Support for Renesas on-chip MMCIF controller
@ -1747,12 +1736,6 @@ Configuration Settings:
Non-cached memory is only supported on 32-bit ARM at present.
- CONFIG_SYS_BOOTM_LEN:
Normally compressed uImages are limited to an
uncompressed size of 8 MBytes. If this is not enough,
you can define CONFIG_SYS_BOOTM_LEN in your board config file
to adjust this setting to your needs.
- CONFIG_SYS_BOOTMAPSZ:
Maximum size of memory mapped by the startup code of
the Linux kernel; all data that must be processed by
@ -1765,11 +1748,6 @@ Configuration Settings:
CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
- CONFIG_SYS_BOOT_RAMDISK_HIGH:
Enable initrd_high functionality. If defined then the
initrd_high feature is enabled and the bootm ramdisk subcommand
is enabled.
- CONFIG_SYS_BOOT_GET_CMDLINE:
Enables allocating and saving kernel cmdline in space between
"bootm_low" and "bootm_low" + BOOTMAPSZ.
@ -2074,10 +2052,6 @@ Low Level (hardware related) configuration options:
- CONFIG_FSL_DDR_BIST
Enable built-in memory test for Freescale DDR controllers.
- CONFIG_SYS_83XX_DDR_USES_CS0
Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't

1
arch/Kconfig.nxp
View File

@ -16,6 +16,7 @@ config CHAIN_OF_TRUST
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
imply CMD_BLOB

2
arch/arc/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef __ASM_ARC_CONFIG_H_
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif /*__ASM_ARC_CONFIG_H_ */

15
arch/arm/Kconfig
View File

@ -330,15 +330,6 @@ config CPU_V7R
select SYS_ARM_MPU
select SYS_CACHE_SHIFT_6
config CPU_PXA
bool
select SYS_CACHE_SHIFT_5
imply SYS_ARM_MMU
config CPU_PXA27X
bool
select CPU_PXA
config CPU_SA1100
bool
select SYS_CACHE_SHIFT_5
@ -354,7 +345,6 @@ config SYS_CPU
default "armv7" if CPU_V7A
default "armv7" if CPU_V7R
default "armv7m" if CPU_V7M
default "pxa" if CPU_PXA
default "sa1100" if CPU_SA1100
default "armv8" if ARM64
@ -369,14 +359,12 @@ config SYS_ARM_ARCH
default 7 if CPU_V7A
default 7 if CPU_V7M
default 7 if CPU_V7R
default 5 if CPU_PXA
default 4 if CPU_SA1100
default 8 if ARM64
choice
prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
CPU_PXA || RZA1
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK
@ -1119,7 +1107,6 @@ config ARCH_SOCFPGA
select SPL_DM_SERIAL
select SPL_LIBCOMMON_SUPPORT
select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_SERIAL

2
arch/arm/Makefile
View File

@ -11,7 +11,6 @@ arch-$(CONFIG_CPU_ARM920T) =-march=armv4t
arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
arch-$(CONFIG_CPU_ARM946ES) =-march=armv5te
arch-$(CONFIG_CPU_SA1100) =-march=armv4
arch-$(CONFIG_CPU_PXA) =
arch-$(CONFIG_CPU_ARM1136) =-march=armv5t
arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \
@ -41,7 +40,6 @@ tune-$(CONFIG_CPU_ARM920T) =
tune-$(CONFIG_CPU_ARM926EJS) =
tune-$(CONFIG_CPU_ARM946ES) =
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
tune-$(CONFIG_CPU_ARM1136) =
tune-$(CONFIG_CPU_ARM1176) =
tune-$(CONFIG_CPU_V7A) =-mtune=generic-armv7-a

2
arch/arm/cpu/armv8/Kconfig
View File

@ -76,6 +76,7 @@ config ARMV8_SEC_FIRMWARE_SUPPORT
config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
bool "Enable ARMv8 secure monitor firmware framework support for SPL"
depends on SPL
select SPL_FIT
select SPL_OF_LIBFDT
help
@ -83,6 +84,7 @@ config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
config SPL_RECOVER_DATA_SECTION
bool "save/restore SPL data section"
depends on SPL
help
Say Y here to save SPL data section for cold boot, and restore
at warm boot in SPL phase.

14
arch/arm/cpu/pxa/Makefile
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@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
extra-y = start.o
obj-$(CONFIG_CPU_PXA27X) += pxa2xx.o
obj-y += cpuinfo.o
obj-y += timer.o
obj-y += usb.o
obj-y += relocate.o
obj-y += cache.o

58
arch/arm/cpu/pxa/cache.c
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@ -1,58 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2016 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/types.h>
#include <common.h>
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
asm volatile("mcr p15, 0, %0, c7, c5, 0\n" : : "r"(0));
/* Flush/Invalidate D cache */
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
{
return invalidate_dcache_all();
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
while (start <= stop) {
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
return invalidate_dcache_range(start, stop);
}
#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
*/
__weak void l2_cache_disable(void) {}
#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
__weak void invalidate_l2_cache(void) {}
#endif

18
arch/arm/cpu/pxa/config.mk
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@ -1,18 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# !WARNING!
# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
# really small OneNAND memories where the mmap'd window is only 1KiB big. The
# .text.0 contains only the bare minimum needed to load the real SPL into SRAM.
# Add .text.0 and .text.1 into OBJFLAGS, so when the SPL is being objcopy'd,
# they are not discarded.
#
#ifdef CONFIG_SPL_BUILD
OBJCOPYFLAGS += -j .text.0 -j .text.1
#endif

139
arch/arm/cpu/pxa/cpuinfo.c
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@ -1,139 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PXA CPU information display
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <errno.h>
#include <linux/compiler.h>
#define CPU_MASK_PXA_PRODID 0x000003f0
#define CPU_MASK_PXA_REVID 0x0000000f
#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
#define CPU_VALUE_PXA25X 0x100
#define CPU_VALUE_PXA27X 0x110
static uint32_t pxa_get_cpuid(void)
{
uint32_t cpuid;
asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r"(cpuid));
return cpuid;
}
int cpu_is_pxa25x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA25X;
}
int cpu_is_pxa27x(void)
{
uint32_t id = pxa_get_cpuid();
id &= CPU_MASK_PXA_PRODID;
return id == CPU_VALUE_PXA27X;
}
int cpu_is_pxa27xm(void)
{
uint32_t id = pxa_get_cpuid();
return ((id & CPU_MASK_PXA_PRODID) == CPU_VALUE_PXA27X) &&
((id & CPU_MASK_PXA_REVID) == 8);
}
uint32_t pxa_get_cpu_revision(void)
{
return pxa_get_cpuid() & CPU_MASK_PRODREV;
}
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
static __maybe_unused const char * const revs_25x[] = { "A0" };
static __maybe_unused const char * const revs_26x[] = {
"A0", "B0", "B1"
};
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa25x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
/* PXA26x is a sick special case as it can't be told apart from PXA25x :-( */
#ifdef CONFIG_CPU_PXA26X
switch (id) {
case 3: return revs_26x[0];
case 5: return revs_26x[1];
case 6: return revs_26x[2];
}
#else
if (id == 6)
return revs_25x[0];
#endif
return unknown;
}
static const char *pxa27x_get_revision(void)
{
static const char *const rev[] = { "A0", "A1", "B0", "B1", "C0", "C5" };
static const char *unknown = "Unknown";
uint32_t id;
if (!cpu_is_pxa27x())
return unknown;
id = pxa_get_cpuid() & CPU_MASK_PXA_REVID;
if ((id == 5) || (id == 6) || (id > 8))
return unknown;
/* Cap the special PXA270 C5 case. */
if (id == 7)
id = 5;
/* Cap the special PXA270M A1 case. */
if (id == 8)
id = 1;
return rev[id];
}
static int print_cpuinfo_pxa2xx(void)
{
if (cpu_is_pxa25x()) {
puts("Marvell PXA25x rev. ");
puts(pxa25x_get_revision());
} else if (cpu_is_pxa27x()) {
puts("Marvell PXA27x");
if (cpu_is_pxa27xm()) puts("M");
puts(" rev. ");
puts(pxa27x_get_revision());
} else
return -EINVAL;
puts("\n");
return 0;
}
int print_cpuinfo(void)
{
int ret;
puts("CPU: ");
ret = print_cpuinfo_pxa2xx();
if (!ret)
return ret;
return ret;
}
#endif

295
arch/arm/cpu/pxa/pxa2xx.c
View File

@ -1,295 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <irq_func.h>
#include <asm/arch/pxa-regs.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
/* Flush I/D-cache */
static void cache_flush(void)
{
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
}
int cleanup_before_linux(void)
{
/*
* This function is called just before we call Linux. It prepares
* the processor for Linux by just disabling everything that can
* disturb booting Linux.
*/
disable_interrupts();
icache_disable();
dcache_disable();
cache_flush();
return 0;
}
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
asm volatile("" : : : "memory");
readl(addr);
asm volatile("" : : : "memory");
}
void pxa2xx_dram_init(void)
{
uint32_t tmp;
int i;
/*
* 1) Initialize Asynchronous static memory controller
*/
writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
/*
* 2) Initialize Card Interface
*/
/* MECR: Memory Expansion Card Register */
writelrb(CONFIG_SYS_MECR_VAL, MECR);
/* MCMEM0: Card Interface slot 0 timing */
writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
/* MCMEM1: Card Interface slot 1 timing */
writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
/*
* 3) Configure Fly-By DMA register
*/
writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
/*
* 4) Initialize Timing for Sync Memory (SDCLK0)
*/
/*
* Before accessing MDREFR we need a valid DRI field, so we set
* this to power on defaults + DRI field.
*/
/* Read current MDREFR config and zero out DRI */
tmp = readl(MDREFR) & ~0xfff;
/* Add user-specified DRI */
tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
/* Configure important bits */
tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
/* Write MDREFR back */
writelrb(tmp, MDREFR);
/*
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
*/
/* Initialize SXCNFG register. Assert the enable bits.
*
* Write SXMRS to cause an MRS command to all enabled banks of
* synchronous static memory. Note that SXLCR need not be written
* at this time.
*/
writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
/*
* 6) Initialize SDRAM
*/
writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
/*
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
* but not enable each SDRAM partition pair.
*/
writelrb(CONFIG_SYS_MDCNFG_VAL &
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
writel(0, OSCR);
while (readl(OSCR) < 0x300)
asm volatile("" : : : "memory");
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
* non-burst read or write accesses to disabled SDRAM, as commonly
* specified in the power up sequence documented in SDRAM data
* sheets. The address(es) used for this purpose must not be
* cacheable.
*/
for (i = 9; i >= 0; i--) {
writel(i, 0xa0000000);
asm volatile("" : : : "memory");
}
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
*/
tmp = CONFIG_SYS_MDCNFG_VAL &
(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
tmp |= readl(MDCNFG);
writelrb(tmp, MDCNFG);
/*
* 10) Write MDMRS.
*/
writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
/*
* 11) Enable APD
*/
if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
tmp = readl(MDREFR);
tmp |= MDREFR_APD;
writelrb(tmp, MDREFR);
}
}
void pxa_gpio_setup(void)
{
writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
#endif
writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
#endif
writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
#endif
writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
#if defined(CONFIG_CPU_PXA27X)
writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
#endif
writel(CONFIG_SYS_PSSR_VAL, PSSR);
}
void pxa_interrupt_setup(void)
{
writel(0, ICLR);
writel(0, ICMR);
#if defined(CONFIG_CPU_PXA27X)
writel(0, ICLR2);
writel(0, ICMR2);
#endif
}
void pxa_clock_setup(void)
{
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
while (!(readl(OSCC) & OSCC_OOK))
asm volatile("" : : : "memory");
}
void pxa_wakeup(void)
{
uint32_t rcsr;
rcsr = readl(RCSR);
writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
/* Wakeup */
if (rcsr & RCSR_SMR) {
writel(PSSR_PH, PSSR);
pxa2xx_dram_init();
icache_disable();
dcache_disable();
asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
}
}
int arch_cpu_init(void)
{
pxa_gpio_setup();
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();
return 0;
}
void i2c_clk_enable(void)
{
/* Set the global I2C clock on */
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
void reset_cpu(void)
{
uint32_t tmp;
setbits_le32(OWER, OWER_WME);
tmp = readl(OSCR);
tmp += 0x1000;
writel(tmp, OSMR3);
writel(MDREFR_SLFRSH, MDREFR);
for (;;)
;
}
void enable_caches(void)
{
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}

22
arch/arm/cpu/pxa/relocate.S
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@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - PXA270 vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The PXA SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

98
arch/arm/cpu/pxa/start.S
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@ -1,98 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* armboot - Startup Code for XScale CPU-core
*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
* Copyright (C) 2001 Marius Groger <mag@sysgo.de>
* Copyright (C) 2002 Alex Zupke <azu@sysgo.de>
* Copyright (C) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (C) 2003 Kshitij <kshitij@ti.com>
* Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com>
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*/
#include <asm-offsets.h>
#include <config.h>
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
#ifdef CONFIG_CPU_PXA27X
/*
* enable clock for SRAM
*/
ldr r0,=CKEN
ldr r1,[r0]
orr r1,r1,#(1 << 20)
str r1,[r0]
#endif
bl _main
/*------------------------------------------------------------------------------*/
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
bx lr
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

16
arch/arm/cpu/pxa/timer.c
View File

@ -1,16 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Marvell PXA2xx/3xx timer driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
int timer_init(void)
{
writel(0, CONFIG_SYS_TIMER_COUNTER);
return 0;
}

89
arch/arm/cpu/pxa/usb.c
View File

@ -1,89 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
*/
#include <common.h>
#include <linux/delay.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <usb.h>
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
udelay(100);
#endif
#if defined(CONFIG_CPU_PXA27X)
/* Enable USB host clock. */
writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
writel(0x3000c, UP2OCR);
#endif
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
mdelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (readl(UHCHR) & UHCHR_FSBIR)
udelay(1);
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
return 0;
}
int usb_cpu_stop(void)
{
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
udelay(10);
#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
#endif
#if defined(CONFIG_CPU_PXA27X)
writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
#endif
writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
#if defined(CONFIG_CPU_MONAHANS)
/* Disable USB host clock. */
writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
udelay(100);
#endif
#if defined(CONFIG_CPU_PXA27X)
/* Disable USB host clock. */
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
#endif
return 0;
}
int usb_cpu_init_fail(void)
{
return usb_cpu_stop();
}
# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

2
arch/arm/dts/Makefile
View File

@ -414,7 +414,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
am437x-cm-t43.dtb
dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \

4
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -13,10 +13,8 @@
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
@ -26,9 +24,7 @@
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -52,7 +52,6 @@
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)

4
arch/arm/include/asm/arch-lpc32xx/config.h
View File

@ -52,11 +52,7 @@
/* USB OHCI */
#if defined(CONFIG_USB_OHCI_LPC32XX)
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
#endif
#endif /* _LPC32XX_CONFIG_H */

6
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -32,14 +32,11 @@
#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
@ -79,8 +76,7 @@
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#ifdef CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif
#define CONFIG_SYS_FSL_IFC_BE

112
arch/arm/include/asm/arch-pxa/bitfield.h
View File

@ -1,112 +0,0 @@
/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */

22
arch/arm/include/asm/arch-pxa/config.h
View File

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Andrew Ruder <andrew.ruder@elecsyscorp.com>
*/
#ifndef _ASM_ARM_PXA_CONFIG_
#define _ASM_ARM_PXA_CONFIG_
#include <asm/arch/pxa-regs.h>
/*
* Generic timer support
*/
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define CONFIG_SYS_TIMER_RATE 3250000
#else
#error "Timer frequency unknown - please config PXA CPU type"
#endif
#define CONFIG_SYS_TIMER_COUNTER OSCR
#endif /* _ASM_ARM_PXA_CONFIG_ */

82
arch/arm/include/asm/arch-pxa/hardware.h
View File

@ -1,82 +0,0 @@
/*
* linux/include/asm-arm/arch-pxa/hardware.h
*
* Author: Nicolas Pitre
* Created: Jun 15, 2001
* Copyright: MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Note: This file was taken from linux-2.4.19-rmk4-pxa1
*
* - 2003/01/20 implementation specifics activated
* Robert Schwebel <r.schwebel@pengutronix.de>
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/mach-types.h>
/*
* Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
* PXA300/310/320 all have distinct register mappings in some cases, that's why
* the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
* drivers and compatibility glue with old source then.
*/
#ifndef CONFIG_CPU_MONAHANS
#if defined(CONFIG_CPU_PXA300) || \
defined(CONFIG_CPU_PXA310) || \
defined(CONFIG_CPU_PXA320)
#define CONFIG_CPU_MONAHANS
#endif
#endif
/*
* These are statically mapped PCMCIA IO space for designs using it as a
* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
* The actual PCMCIA code is mapping required IO region at run time.
*/
#define PCMCIA_IO_0_BASE 0xf6000000
#define PCMCIA_IO_1_BASE 0xf7000000
/*
* We requires absolute addresses.
*/
#define PCIO_BASE 0
/*
* Workarounds for at least 2 errata so far require this.
* The mapping is set in mach-pxa/generic.c.
*/
#define UNCACHED_PHYS_0 0xff000000
#define UNCACHED_ADDR UNCACHED_PHYS_0
/*
* Intel PXA internal I/O mappings:
*
* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
#include "pxa-regs.h"
#ifndef __ASSEMBLY__
/*
* GPIO edge detection for IRQs:
* IRQs are generated on Falling-Edge, Rising-Edge, or both.
* This must be called *before* the corresponding IRQ is registered.
* Use this instead of directly setting GRER/GFER.
*/
#define GPIO_FALLING_EDGE 1
#define GPIO_RISING_EDGE 2
#define GPIO_BOTH_EDGES 3
#endif
#endif /* _ASM_ARCH_HARDWARE_H */

2635
arch/arm/include/asm/arch-pxa/pxa-regs.h
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File diff suppressed because it is too large Load Diff

28
arch/arm/include/asm/arch-pxa/pxa.h
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* PXA common functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __PXA_H__
#define __PXA_H__
#define PXA255_A0 0x00000106
#define PXA250_C0 0x00000105
#define PXA250_B2 0x00000104
#define PXA250_B1 0x00000103
#define PXA250_B0 0x00000102
#define PXA250_A1 0x00000101
#define PXA250_A0 0x00000100
#define PXA210_C0 0x00000125
#define PXA210_B2 0x00000124
#define PXA210_B1 0x00000123
#define PXA210_B0 0x00000122
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
uint32_t pxa_get_cpu_revision(void);
void pxa2xx_dram_init(void);
#endif /* __PXA_H__ */

140
arch/arm/include/asm/arch-pxa/regs-mmc.h
View File

@ -1,140 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __REGS_MMC_H__
#define __REGS_MMC_H__
#define MMC0_BASE 0x41100000
#define MMC1_BASE 0x42000000
int pxa_mmc_register(int card_index);
struct pxa_mmc_regs {
uint32_t strpcl;
uint32_t stat;
uint32_t clkrt;
uint32_t spi;
uint32_t cmdat;
uint32_t resto;
uint32_t rdto;
uint32_t blklen;
uint32_t nob;
uint32_t prtbuf;
uint32_t i_mask;
uint32_t i_reg;
uint32_t cmd;
uint32_t argh;
uint32_t argl;
uint32_t res;
uint32_t rxfifo;
uint32_t txfifo;
};
/* MMC_STRPCL */
#define MMC_STRPCL_STOP_CLK (1 << 0)
#define MMC_STRPCL_START_CLK (1 << 1)
/* MMC_STAT */
#define MMC_STAT_END_CMD_RES (1 << 13)
#define MMC_STAT_PRG_DONE (1 << 12)
#define MMC_STAT_DATA_TRAN_DONE (1 << 11)
#define MMC_STAT_CLK_EN (1 << 8)
#define MMC_STAT_RECV_FIFO_FULL (1 << 7)
#define MMC_STAT_XMIT_FIFO_EMPTY (1 << 6)
#define MMC_STAT_RES_CRC_ERROR (1 << 5)
#define MMC_STAT_SPI_READ_ERROR_TOKEN (1 << 4)
#define MMC_STAT_CRC_READ_ERROR (1 << 3)
#define MMC_STAT_CRC_WRITE_ERROR (1 << 2)
#define MMC_STAT_TIME_OUT_RESPONSE (1 << 1)
#define MMC_STAT_READ_TIME_OUT (1 << 0)
/* MMC_CLKRT */
#define MMC_CLKRT_20MHZ 0
#define MMC_CLKRT_10MHZ 1
#define MMC_CLKRT_5MHZ 2
#define MMC_CLKRT_2_5MHZ 3
#define MMC_CLKRT_1_25MHZ 4
#define MMC_CLKRT_0_625MHZ 5
#define MMC_CLKRT_0_3125MHZ 6
/* MMC_SPI */
#define MMC_SPI_EN (1 << 0)
#define MMC_SPI_CS_EN (1 << 2)
#define MMC_SPI_CS_ADDRESS (1 << 3)
#define MMC_SPI_CRC_ON (1 << 1)
/* MMC_CMDAT */
#define MMC_CMDAT_SD_4DAT (1 << 8)
#define MMC_CMDAT_MMC_DMA_EN (1 << 7)
#define MMC_CMDAT_INIT (1 << 6)
#define MMC_CMDAT_BUSY (1 << 5)
#define MMC_CMDAT_BCR (MMC_CMDAT_BUSY | MMC_CMDAT_INIT)
#define MMC_CMDAT_STREAM (1 << 4)
#define MMC_CMDAT_WRITE (1 << 3)
#define MMC_CMDAT_DATA_EN (1 << 2)
#define MMC_CMDAT_R0 0
#define MMC_CMDAT_R1 1
#define MMC_CMDAT_R2 2
#define MMC_CMDAT_R3 3
/* MMC_RESTO */
#define MMC_RES_TO_MAX_MASK 0x7f
/* MMC_RDTO */
#define MMC_READ_TO_MAX_MASK 0xffff
/* MMC_BLKLEN */
#define MMC_BLK_LEN_MAX_MASK 0x3ff
/* MMC_PRTBUF */
#define MMC_PRTBUF_BUF_PART_FULL (1 << 0)
/* MMC_I_MASK */
#define MMC_I_MASK_TXFIFO_WR_REQ (1 << 6)
#define MMC_I_MASK_RXFIFO_RD_REQ (1 << 5)
#define MMC_I_MASK_CLK_IS_OFF (1 << 4)
#define MMC_I_MASK_STOP_CMD (1 << 3)
#define MMC_I_MASK_END_CMD_RES (1 << 2)
#define MMC_I_MASK_PRG_DONE (1 << 1)
#define MMC_I_MASK_DATA_TRAN_DONE (1 << 0)
#define MMC_I_MASK_ALL 0x7f
/* MMC_I_REG */
#define MMC_I_REG_TXFIFO_WR_REQ (1 << 6)
#define MMC_I_REG_RXFIFO_RD_REQ (1 << 5)
#define MMC_I_REG_CLK_IS_OFF (1 << 4)
#define MMC_I_REG_STOP_CMD (1 << 3)
#define MMC_I_REG_END_CMD_RES (1 << 2)
#define MMC_I_REG_PRG_DONE (1 << 1)
#define MMC_I_REG_DATA_TRAN_DONE (1 << 0)
/* MMC_CMD */
#define MMC_CMD_INDEX_MAX 0x6f
#define MMC_R1_IDLE_STATE 0x01
#define MMC_R1_ERASE_STATE 0x02
#define MMC_R1_ILLEGAL_CMD 0x04
#define MMC_R1_COM_CRC_ERR 0x08
#define MMC_R1_ERASE_SEQ_ERR 0x01
#define MMC_R1_ADDR_ERR 0x02
#define MMC_R1_PARAM_ERR 0x04
#define MMC_R1B_WP_ERASE_SKIP 0x0002
#define MMC_R1B_ERR 0x0004
#define MMC_R1B_CC_ERR 0x0008
#define MMC_R1B_CARD_ECC_ERR 0x0010
#define MMC_R1B_WP_VIOLATION 0x0020
#define MMC_R1B_ERASE_PARAM 0x0040
#define MMC_R1B_OOR 0x0080
#define MMC_R1B_IDLE_STATE 0x0100
#define MMC_R1B_ERASE_RESET 0x0200
#define MMC_R1B_ILLEGAL_CMD 0x0400
#define MMC_R1B_COM_CRC_ERR 0x0800
#define MMC_R1B_ERASE_SEQ_ERR 0x1000
#define MMC_R1B_ADDR_ERR 0x2000
#define MMC_R1B_PARAM_ERR 0x4000
#endif /* __REGS_MMC_H__ */

95
arch/arm/include/asm/arch-pxa/regs-uart.h
View File

@ -1,95 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*/
#ifndef __REGS_UART_H__
#define __REGS_UART_H__
#define FFUART_BASE 0x40100000
#define BTUART_BASE 0x40200000
#define STUART_BASE 0x40700000
#define HWUART_BASE 0x41600000
struct pxa_uart_regs {
union {
uint32_t thr;
uint32_t rbr;
uint32_t dll;
};
union {
uint32_t ier;
uint32_t dlh;
};
union {
uint32_t fcr;
uint32_t iir;
};
uint32_t lcr;
uint32_t mcr;
uint32_t lsr;
uint32_t msr;
uint32_t spr;
uint32_t isr;
};
#define IER_DMAE (1 << 7)
#define IER_UUE (1 << 6)
#define IER_NRZE (1 << 5)
#define IER_RTIOE (1 << 4)
#define IER_MIE (1 << 3)
#define IER_RLSE (1 << 2)
#define IER_TIE (1 << 1)
#define IER_RAVIE (1 << 0)
#define IIR_FIFOES1 (1 << 7)
#define IIR_FIFOES0 (1 << 6)
#define IIR_TOD (1 << 3)
#define IIR_IID2 (1 << 2)
#define IIR_IID1 (1 << 1)
#define IIR_IP (1 << 0)
#define FCR_ITL2 (1 << 7)
#define FCR_ITL1 (1 << 6)
#define FCR_RESETTF (1 << 2)
#define FCR_RESETRF (1 << 1)
#define FCR_TRFIFOE (1 << 0)
#define FCR_ITL_1 0
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7)
#define LCR_SB (1 << 6)
#define LCR_STKYP (1 << 5)
#define LCR_EPS (1 << 4)
#define LCR_PEN (1 << 3)
#define LCR_STB (1 << 2)
#define LCR_WLS1 (1 << 1)
#define LCR_WLS0 (1 << 0)
#define LSR_FIFOE (1 << 7)
#define LSR_TEMT (1 << 6)
#define LSR_TDRQ (1 << 5)
#define LSR_BI (1 << 4)
#define LSR_FE (1 << 3)
#define LSR_PE (1 << 2)
#define LSR_OE (1 << 1)
#define LSR_DR (1 << 0)
#define MCR_LOOP (1 << 4)
#define MCR_OUT2 (1 << 3)
#define MCR_OUT1 (1 << 2)
#define MCR_RTS (1 << 1)
#define MCR_DTR (1 << 0)
#define MSR_DCD (1 << 7)
#define MSR_RI (1 << 6)
#define MSR_DSR (1 << 5)
#define MSR_CTS (1 << 4)
#define MSR_DDCD (1 << 3)
#define MSR_TERI (1 << 2)
#define MSR_DDSR (1 << 1)
#define MSR_DCTS (1 << 0)
#endif /* __REGS_UART_H__ */

146
arch/arm/include/asm/arch-pxa/regs-usb.h
View File

@ -1,146 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* PXA25x UDC definitions
*
* Copyright (C) 2012 Łukasz Dałek <luk0104@gmail.com>
*/
#ifndef __REGS_USB_H__
#define __REGS_USB_H__
struct pxa25x_udc_regs {
/* UDC Control Register */
uint32_t udccr; /* 0x000 */
uint32_t reserved1;
/* UDC Control Function Register */
uint32_t udccfr; /* 0x008 */
uint32_t reserved2;
/* UDC Endpoint Control/Status Registers */
uint32_t udccs[16]; /* 0x010 - 0x04c */
/* UDC Interrupt Control/Status Registers */
uint32_t uicr0; /* 0x050 */
uint32_t uicr1; /* 0x054 */
uint32_t usir0; /* 0x058 */
uint32_t usir1; /* 0x05c */
/* UDC Frame Number/Byte Count Registers */
uint32_t ufnrh; /* 0x060 */
uint32_t ufnrl; /* 0x064 */
uint32_t ubcr2; /* 0x068 */
uint32_t ubcr4; /* 0x06c */
uint32_t ubcr7; /* 0x070 */
uint32_t ubcr9; /* 0x074 */
uint32_t ubcr12; /* 0x078 */
uint32_t ubcr14; /* 0x07c */
/* UDC Endpoint Data Registers */
uint32_t uddr0; /* 0x080 */
uint32_t reserved3[7];
uint32_t uddr5; /* 0x0a0 */
uint32_t reserved4[7];
uint32_t uddr10; /* 0x0c0 */
uint32_t reserved5[7];
uint32_t uddr15; /* 0x0e0 */
uint32_t reserved6[7];
uint32_t uddr1; /* 0x100 */
uint32_t reserved7[31];
uint32_t uddr2; /* 0x180 */
uint32_t reserved8[31];
uint32_t uddr3; /* 0x200 */
uint32_t reserved9[127];
uint32_t uddr4; /* 0x400 */
uint32_t reserved10[127];
uint32_t uddr6; /* 0x600 */
uint32_t reserved11[31];
uint32_t uddr7; /* 0x680 */
uint32_t reserved12[31];
uint32_t uddr8; /* 0x700 */
uint32_t reserved13[127];
uint32_t uddr9; /* 0x900 */
uint32_t reserved14[127];
uint32_t uddr11; /* 0xb00 */
uint32_t reserved15[31];
uint32_t uddr12; /* 0xb80 */
uint32_t reserved16[31];
uint32_t uddr13; /* 0xc00 */
uint32_t reserved17[127];
uint32_t uddr14; /* 0xe00 */
};
#define PXA25X_UDC_BASE 0x40600000
#define UDCCR_UDE (1 << 0)
#define UDCCR_UDA (1 << 1)
#define UDCCR_RSM (1 << 2)
#define UDCCR_RESIR (1 << 3)
#define UDCCR_SUSIR (1 << 4)
#define UDCCR_SRM (1 << 5)
#define UDCCR_RSTIR (1 << 6)
#define UDCCR_REM (1 << 7)
/* Bulk IN endpoint 1/6/11 */
#define UDCCS_BI_TSP (1 << 7)
#define UDCCS_BI_FST (1 << 5)
#define UDCCS_BI_SST (1 << 4)
#define UDCCS_BI_TUR (1 << 3)
#define UDCCS_BI_FTF (1 << 2)
#define UDCCS_BI_TPC (1 << 1)
#define UDCCS_BI_TFS (1 << 0)
/* Bulk OUT endpoint 2/7/12 */
#define UDCCS_BO_RSP (1 << 7)
#define UDCCS_BO_RNE (1 << 6)
#define UDCCS_BO_FST (1 << 5)
#define UDCCS_BO_SST (1 << 4)
#define UDCCS_BO_DME (1 << 3)
#define UDCCS_BO_RPC (1 << 1)
#define UDCCS_BO_RFS (1 << 0)
/* Isochronous OUT endpoint 4/9/14 */
#define UDCCS_IO_RSP (1 << 7)
#define UDCCS_IO_RNE (1 << 6)
#define UDCCS_IO_DME (1 << 3)
#define UDCCS_IO_ROF (1 << 2)
#define UDCCS_IO_RPC (1 << 1)
#define UDCCS_IO_RFS (1 << 0)
/* Control endpoint 0 */
#define UDCCS0_OPR (1 << 0)
#define UDCCS0_IPR (1 << 1)
#define UDCCS0_FTF (1 << 2)
#define UDCCS0_DRWF (1 << 3)
#define UDCCS0_SST (1 << 4)
#define UDCCS0_FST (1 << 5)
#define UDCCS0_RNE (1 << 6)
#define UDCCS0_SA (1 << 7)
#define UICR0_IM0 (1 << 0)
#define USIR0_IR0 (1 << 0)
#define USIR0_IR1 (1 << 1)
#define USIR0_IR2 (1 << 2)
#define USIR0_IR3 (1 << 3)
#define USIR0_IR4 (1 << 4)
#define USIR0_IR5 (1 << 5)
#define USIR0_IR6 (1 << 6)
#define USIR0_IR7 (1 << 7)
#define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */
#define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */
/*
* Intel(R) PXA255 Processor Specification, September 2003 (page 31)
* define new "must be one" bits in UDCCFR (see Table 12-13.)
*/
#define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN | UDCCFR_ACM))
#define UFNRH_SIR (1 << 7) /* SOF interrupt request */
#define UFNRH_SIM (1 << 6) /* SOF interrupt mask */
#define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */
#define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */
#define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */
#endif /* __REGS_USB_H__ */

4
arch/arm/include/asm/config.h
View File

@ -6,11 +6,7 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#if defined(CONFIG_ARCH_LS1021A) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif

4
arch/arm/mach-imx/imx8/Kconfig
View File

@ -20,13 +20,13 @@ config MU_BASE_SPL
config IMX8QM
select IMX8
select SUPPORT_SPL
select SPL_RECOVER_DATA_SECTION
select SPL_RECOVER_DATA_SECTION if SPL
bool
config IMX8QXP
select IMX8
select SUPPORT_SPL
select SPL_RECOVER_DATA_SECTION
select SPL_RECOVER_DATA_SECTION if SPL
bool
config SYS_SOC

21
arch/arm/mach-omap2/Kconfig
View File

@ -169,6 +169,27 @@ config TI_SECURE_EMIF_PROTECTED_REGION_SIZE
using hardware memory firewalls. This value must be smaller than the
TI_SECURE_EMIF_TOTAL_REGION_SIZE value.
config SYS_AUTOMATIC_SDRAM_DETECTION
bool
choice
depends on OMAP44XX || OMAP54XX
prompt "Static or dynamic DDR timing calculations"
default SYS_EMIF_PRECALCULATED_TIMING_REGS
help
For the DDR timing information we can either dynamically determine
the timings to use or use pre-determined timings (based on using the
dynamic method). Default to the static timing information.
config SYS_EMIF_PRECALCULATED_TIMING_REGS
bool "Use precalcualted timing values"
config SYS_DEFAULT_LPDDR2_TIMINGS
bool "Use default LPDDR2 timing values"
select SYS_AUTOMATIC_SDRAM_DETECTION
endchoice
source "arch/arm/mach-omap2/omap3/Kconfig"
source "arch/arm/mach-omap2/omap4/Kconfig"

2
arch/m68k/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

2
arch/microblaze/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

2
arch/mips/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

6
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -11,6 +11,11 @@ config E300
config SYS_CPU
default "mpc83xx"
config SYS_83XX_DDR_USES_CS0
bool
help
DDR should be configured using CS0 and CS1 instead of CS2 and CS3.
choice
prompt "Target select"
optional
@ -19,6 +24,7 @@ config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
select ARCH_MPC837X
select BOARD_EARLY_INIT_F
select SYS_83XX_DDR_USES_CS0
config TARGET_IDS8313
bool "Support ids8313"

14
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -109,6 +109,7 @@ config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
select ARCH_QEMU_E500
select PHYS_64BIT
select SYS_RAMBOOT
imply OF_HAS_PRIOR_STAGE
config TARGET_T1024RDB
@ -1216,6 +1217,19 @@ config SYS_FSL_LBC_CLK_DIV
config ENABLE_36BIT_PHYS
bool "Enable 36bit physical address space support"
config SYS_BOOK3E_HV
bool "Category E.HV is supported"
depends on BOOKE
config SYS_CPC_REINIT_F
bool
help
The CPC is configured as SRAM at the time of U-Boot entry and is
required to be re-initialized.
config SYS_FSL_CPC
bool "Corenet Platform Cache support"
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx

2
arch/powerpc/include/asm/config.h
View File

@ -14,8 +14,6 @@
#define HWCONFIG_BUFFER_SIZE 256
#endif
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#ifndef CONFIG_MAX_MEM_MAPPED
#if defined(CONFIG_E500) || \
defined(CONFIG_MPC86xx) || \

3
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -21,9 +21,6 @@
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_ARCH_T1024)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F
#endif
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif

2
arch/riscv/include/asm/config.h
View File

@ -7,6 +7,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

1
arch/x86/Kconfig
View File

@ -945,6 +945,7 @@ config ACPI_GPE
config SPL_ACPI_GPE
bool "Support ACPI general-purpose events in SPL"
depends on SPL
help
Enable a driver for ACPI GPEs to allow peripherals to send interrupts
via ACPI to the OS. In U-Boot this is only used when U-Boot itself

2
arch/x86/include/asm/config.h
View File

@ -6,6 +6,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

6
board/keymile/km83xx/km83xx.c
View File

@ -102,8 +102,10 @@ int misc_init_r(void)
int last_stage_init(void)
{
#if defined(CONFIG_TARGET_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
/*
* BFTIC3 on the local bus CS4
*/
struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
if (dip_switch != 0) {

14
boot/Kconfig
View File

@ -555,8 +555,12 @@ config CHROMEOS_VBOOT
distinguishing between booting Chrome OS in a basic way (developer
mode) and a full boot.
config SYS_RAMBOOT
bool
config RAMBOOT_PBL
bool "Freescale PBL(pre-boot loader) image format support"
select SYS_RAMBOOT if PPC
help
Some SoCs use PBL to load RCW and/or pre-initialization instructions.
For more details refer to doc/README.pblimage
@ -602,6 +606,14 @@ config SYS_FSL_PBL_RCW
Enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details.
config SYS_BOOT_RAMDISK_HIGH
depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ
depends on !(NIOS2 || SANDBOX || SH || XTENSA)
def_bool y
help
Enable initrd_high functionality. If defined then the initrd_high
feature is enabled and the boot* ramdisk subcommand is enabled.
endmenu # Boot images
menu "Boot timing"
@ -626,7 +638,7 @@ config BOOTSTAGE
config SPL_BOOTSTAGE
bool "Boot timing and reported in SPL"
depends on BOOTSTAGE
depends on BOOTSTAGE && SPL
help
Enable recording of boot time in SPL. To make this visible to U-Boot
proper, enable BOOTSTAGE_STASH as well. This will stash the timing

24
boot/bootm.c
View File

@ -33,11 +33,6 @@
#include <bootm.h>
#include <image.h>
#ifndef CONFIG_SYS_BOOTM_LEN
/* use 8MByte as default max gunzip size */
#define CONFIG_SYS_BOOTM_LEN 0x800000
#endif
#define MAX_CMDLINE_SIZE SZ_4K
#define IH_INITRD_ARCH IH_ARCH_DEFAULT
@ -369,10 +364,12 @@ static int bootm_find_other(struct cmd_tbl *cmdtp, int flag, int argc,
*
* @comp_type: Compression type being used (IH_COMP_...)
* @uncomp_size: Number of bytes uncompressed
* @buf_size: Number of bytes the decompresion buffer was
* @ret: errno error code received from compression library
* Return: Appropriate BOOTM_ERR_ error code
*/
static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret)
static int handle_decomp_error(int comp_type, size_t uncomp_size,
size_t buf_size, int ret)
{
const char *name = genimg_get_comp_name(comp_type);
@ -380,7 +377,7 @@ static int handle_decomp_error(int comp_type, size_t uncomp_size, int ret)
if (ret == -ENOSYS)
return BOOTM_ERR_UNIMPLEMENTED;
if (uncomp_size >= CONFIG_SYS_BOOTM_LEN)
if (uncomp_size >= buf_size)
printf("Image too large: increase CONFIG_SYS_BOOTM_LEN\n");
else
printf("%s: uncompress error %d\n", name, ret);
@ -420,7 +417,8 @@ static int bootm_load_os(bootm_headers_t *images, int boot_progress)
load_buf, image_buf, image_len,
CONFIG_SYS_BOOTM_LEN, &load_end);
if (err) {
err = handle_decomp_error(os.comp, load_end - load, err);
err = handle_decomp_error(os.comp, load_end - load,
CONFIG_SYS_BOOTM_LEN, err);
bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
return err;
}
@ -1006,7 +1004,7 @@ static int bootm_host_load_image(const void *fit, int req_image_type,
ulong data, len;
bootm_headers_t images;
int noffset;
ulong load_end;
ulong load_end, buf_size;
uint8_t image_type;
uint8_t imape_comp;
void *load_buf;
@ -1032,14 +1030,14 @@ static int bootm_host_load_image(const void *fit, int req_image_type,
}
/* Allow the image to expand by a factor of 4, should be safe */
load_buf = malloc((1 << 20) + len * 4);
buf_size = (1 << 20) + len * 4;
load_buf = malloc(buf_size);
ret = image_decomp(imape_comp, 0, data, image_type, load_buf,
(void *)data, len, CONFIG_SYS_BOOTM_LEN,
&load_end);
(void *)data, len, buf_size, &load_end);
free(load_buf);
if (ret) {
ret = handle_decomp_error(imape_comp, load_end - 0, ret);
ret = handle_decomp_error(imape_comp, load_end - 0, buf_size, ret);
if (ret != BOOTM_ERR_UNIMPLEMENTED)
return ret;
}

10
cmd/Kconfig
View File

@ -335,6 +335,16 @@ config BOOTM_VXWORKS
help
Support booting VxWorks images via the bootm command.
config SYS_BOOTM_LEN
hex "Maximum size of a decompresed OS image"
depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ
default 0x4000000 if PPC || ARM64
default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7
default 0x800000
help
This is the maximum size of the buffer that is used to decompress the OS
image in to, if passing a compressed image to bootm/booti/bootz.
config CMD_BOOTEFI
bool "bootefi"
depends on EFI_LOADER

3
common/Kconfig
View File

@ -83,6 +83,7 @@ config LOGLEVEL
config SPL_LOGLEVEL
int
depends on SPL
default LOGLEVEL
config TPL_LOGLEVEL
@ -358,7 +359,7 @@ config LOG_SYSLOG
config SPL_LOG
bool "Enable logging support in SPL"
depends on LOG
depends on LOG && SPL
help
This enables support for logging of status and debug messages. These
can be displayed on the console, recorded in a memory buffer, or

1
configs/M5208EVBE_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y

1
configs/M5235EVB_Flash32_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set

1
configs/M5235EVB_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set

1
configs/M5253DEMO_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_IDE=y
# CONFIG_CMD_SETEXPR is not set

1
configs/M5275EVB_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x1000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADB is not set

2
configs/M53017EVB_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
@ -42,6 +43,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000

2
configs/M5329AFEE_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
@ -41,6 +42,7 @@ CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000

2
configs/M5329BFEE_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
@ -43,6 +44,7 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000

2
configs/M5373EVB_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_SYS_MALLOC_BOOTPARAMS=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="-> "
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
@ -43,6 +44,7 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y
CONFIG_SYS_UNIFY_CACHE=y
CONFIG_MII=y
CONFIG_MCFRTC=y
CONFIG_SYS_MCFRTC_BASE=0xFC0A8000

1
configs/MCR3000_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SYS_PROMPT="S3K> "
CONFIG_SYS_PBSIZE=278
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_SYS_BOOTM_LEN=0x800000
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_LOADB is not set

2
configs/P2041RDB_NAND_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P2041RDB_SDCARD_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P2041RDB_SPIFLASH_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P2041RDB_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P3041DS_NAND_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P3041DS_SDCARD_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P3041DS_SPIFLASH_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P3041DS_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P4080DS_SDCARD_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P4080DS_SPIFLASH_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P4080DS_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P5040DS_NAND_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P5040DS_SDCARD_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P5040DS_SPIFLASH_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/P5040DS_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/T1024RDB_NAND_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

2
configs/T1024RDB_SDCARD_defconfig
View File

@ -14,6 +14,8 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

2
configs/T1024RDB_SPIFLASH_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

2
configs/T1024RDB_defconfig
View File

@ -9,6 +9,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

2
configs/T1042D4RDB_NAND_defconfig
View File

@ -12,6 +12,8 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y

2
configs/T1042D4RDB_SDCARD_defconfig
View File

@ -13,6 +13,8 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

2
configs/T1042D4RDB_SPIFLASH_defconfig
View File

@ -15,6 +15,8 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

2
configs/T1042D4RDB_defconfig
View File

@ -8,6 +8,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y

12
configs/T2080QDS_NAND_defconfig
View File

@ -6,23 +6,16 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x140000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -34,7 +27,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

12
configs/T2080QDS_SDCARD_defconfig
View File

@ -6,13 +6,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
@ -20,9 +13,9 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -34,7 +27,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

3
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -6,6 +6,8 @@ CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_NXP_ESBC=y
CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000
CONFIG_PCIE1=y
@ -106,5 +108,4 @@ CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y

12
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -7,13 +7,6 @@ CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
@ -22,9 +15,9 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -36,7 +29,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

11
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View File

@ -2,19 +2,18 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
<<<<<<< HEAD
=======
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
@ -22,12 +21,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SRIO_PCIE_BOOT_SLAVE=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

10
configs/T2080QDS_defconfig
View File

@ -3,18 +3,17 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
<<<<<<< HEAD
=======
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
CONFIG_PCIE4=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
@ -22,11 +21,6 @@ CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

9
configs/T2080RDB_NAND_defconfig
View File

@ -6,20 +6,16 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -28,7 +24,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_SDCARD_defconfig
View File

@ -6,10 +6,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
@ -17,9 +13,9 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -28,7 +24,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_SPIFLASH_defconfig
View File

@ -7,10 +7,6 @@ CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
@ -19,9 +15,9 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -30,7 +26,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_defconfig
View File

@ -3,17 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
<<<<<<< HEAD
=======
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -22,7 +18,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_revD_NAND_defconfig
View File

@ -6,21 +6,17 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -29,7 +25,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_revD_SDCARD_defconfig
View File

@ -6,10 +6,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
@ -17,10 +13,10 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -29,7 +25,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_revD_SPIFLASH_defconfig
View File

@ -7,10 +7,6 @@ CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
@ -19,10 +15,10 @@ CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -31,7 +27,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T2080RDB_revD_defconfig
View File

@ -3,18 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_T2080RDB_REV_D=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -23,7 +19,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_MP=y

9
configs/T4240RDB_SDCARD_defconfig
View File

@ -6,10 +6,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
@ -17,9 +13,9 @@ CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
<<<<<<< HEAD
=======
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -28,7 +24,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

9
configs/T4240RDB_defconfig
View File

@ -3,17 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
<<<<<<< HEAD
=======
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SYS_FSL_CPC=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y
CONFIG_PCIE3=y
@ -22,7 +18,6 @@ CONFIG_VID=y
CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
>>>>>>> Convert CONFIG_PCIE1 et al to Kconfig
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y

1
configs/a3y17lte_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y

1
configs/a5y17lte_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C_GPIO=y

1
configs/a64-olinuxino-emmc_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x54000
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y

1
configs/a64-olinuxino_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_STACK=0x54000
CONFIG_SYS_PBSIZE=1024
CONFIG_SYS_BOOTM_LEN=0x2000000
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

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