arm: mediatek: add support for MediaTek MT7981 SoC
This patch adds basic support for MediaTek MT7981 SoC. This include the file that will initialize the SoC after boot and its device tree. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
Tom Rini
parent
10c6233696
commit
ed86e4fba1
295
arch/arm/dts/mt7981.dtsi
Normal file
295
arch/arm/dts/mt7981.dtsi
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@ -0,0 +1,295 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7981-clk.h>
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#include <dt-bindings/reset/mt7629-reset.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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/ {
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compatible = "mediatek,mt7981";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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mediatek,hwver = <&hwver>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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mediatek,hwver = <&hwver>;
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};
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};
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gpt_clk: gpt_dummy20m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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hwver: hwver {
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compatible = "mediatek,hwver", "syscon";
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reg = <0x8000000 0x1000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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clock-frequency = <13000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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arm,cpu-registers-not-fw-configured;
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};
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timer0: timer@10008000 {
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compatible = "mediatek,mt7986-timer";
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reg = <0x10008000 0x1000>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gpt_clk>;
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clock-names = "gpt-clk";
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u-boot,dm-pre-reloc;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt";
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reg = <0x1001c000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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status = "disabled";
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0x0c000000 0x40000>, /* GICD */
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<0x0c080000 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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fixed_plls: apmixedsys@1001e000 {
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compatible = "mediatek,mt7981-fixed-plls";
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reg = <0x1001e000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7981-topckgen";
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reg = <0x1001b000 0x1000>;
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clock-parent = <&fixed_plls>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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infracfg_ao: infracfg_ao@10001000 {
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compatible = "mediatek,mt7981-infracfg_ao";
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reg = <0x10001000 0x80>;
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clock-parent = <&infracfg>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7981-infracfg";
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reg = <0x10001000 0x30>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: pinctrl@11d00000 {
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compatible = "mediatek,mt7981-pinctrl";
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reg = <0x11d00000 0x1000>,
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<0x11c00000 0x1000>,
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<0x11c10000 0x1000>,
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<0x11d20000 0x1000>,
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<0x11e00000 0x1000>,
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<0x11e20000 0x1000>,
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<0x11f00000 0x1000>,
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<0x11f10000 0x1000>,
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<0x1000b000 0x1000>;
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reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rm_base",
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"iocfg_rb_base", "iocfg_lb_base", "iocfg_bl_base",
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"iocfg_tm_base", "iocfg_tl_base", "eint";
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0x10048000 0x1000>;
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#clock-cells = <1>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CK_INFRA_PWM>,
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<&infracfg_ao CK_INFRA_PWM_BSEL>,
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<&infracfg_ao CK_INFRA_PWM1_CK>,
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<&infracfg_ao CK_INFRA_PWM2_CK>,
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/* FIXME */
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<&infracfg_ao CK_INFRA_PWM2_CK>;
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assigned-clocks = <&topckgen CK_TOP_PWM_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x400>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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mediatek,force-highspeed;
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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uart1: serial@11003000 {
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compatible = "mediatek,hsuart";
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reg = <0x11003000 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART1_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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mediatek,force-highspeed;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,hsuart";
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reg = <0x11004000 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
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assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
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<&infracfg_ao CK_INFRA_UART2_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
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<&infracfg CK_INFRA_UART>;
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mediatek,force-highspeed;
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status = "disabled";
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};
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snand: snand@11005000 {
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compatible = "mediatek,mt7986-snand";
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reg = <0x11005000 0x1000>,
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<0x11006000 0x1000>;
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reg-names = "nfi", "ecc";
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clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
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<&infracfg_ao CK_INFRA_NFI1_CK>,
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<&infracfg_ao CK_INFRA_NFI_HCK_CK>;
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clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
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assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
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<&topckgen CK_TOP_NFI1X_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
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<&topckgen CK_TOP_CB_M_D8>;
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status = "disabled";
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};
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ethsys: syscon@15000000 {
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compatible = "mediatek,mt7981-ethsys", "syscon";
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reg = <0x15000000 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7981-eth", "syscon";
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reg = <0x15100000 0x20000>;
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resets = <ðsys ETHSYS_FE_RST>;
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reset-names = "fe";
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7986-sgmiisys", "syscon";
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reg = <0x10060000 0x1000>;
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pn_swap;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7986-sgmiisys", "syscon";
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reg = <0x10070000 0x1000>;
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#clock-cells = <1>;
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,ipm-spi";
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reg = <0x1100a000 0x100>;
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clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
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<&topckgen CK_TOP_SPI_SEL>;
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assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
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<&infracfg CK_INFRA_SPI0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
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<&topckgen CK_INFRA_ISPI0>;
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clock-names = "sel-clk", "spi-clk";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi1: spi@1100b000 {
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compatible = "mediatek,ipm-spi";
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reg = <0x1100b000 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi2: spi@11009000 {
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compatible = "mediatek,ipm-spi";
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reg = <0x11009000 0x100>;
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clocks = <&infracfg_ao CK_INFRA_SPI0_CK>,
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<&topckgen CK_TOP_SPI_SEL>;
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assigned-clocks = <&topckgen CK_TOP_SPI_SEL>,
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<&infracfg CK_INFRA_SPI0_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>,
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<&topckgen CK_INFRA_ISPI0>;
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clock-names = "sel-clk", "spi-clk";
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7981-mmc";
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reg = <0x11230000 0x1000>,
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<0x11C20000 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CK_TOP_EMMC_400M>,
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<&topckgen CK_TOP_EMMC_208M>,
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<&infracfg_ao CK_INFRA_MSDC_CK>;
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assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>,
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<&topckgen CK_TOP_EMMC_208M_SEL>;
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assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>,
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<&topckgen CK_TOP_CB_M_D2>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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};
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@ -40,6 +40,15 @@ config TARGET_MT7629
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including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
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switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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config TARGET_MT7981
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bool "MediaTek MT7981 SoC"
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select ARM64
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select CPU
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help
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The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53.
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including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C,
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built-in Wi-Fi, and PCIe.
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config TARGET_MT7986
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bool "MediaTek MT7986 SoC"
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select ARM64
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@ -93,6 +102,7 @@ config SYS_BOARD
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default "mt7622" if TARGET_MT7622
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default "mt7623" if TARGET_MT7623
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default "mt7629" if TARGET_MT7629
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default "mt7981" if TARGET_MT7981
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default "mt7986" if TARGET_MT7986
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default "mt8183" if TARGET_MT8183
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default "mt8512" if TARGET_MT8512
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@ -109,6 +119,7 @@ config SYS_CONFIG_NAME
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default "mt7622" if TARGET_MT7622
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default "mt7623" if TARGET_MT7623
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default "mt7629" if TARGET_MT7629
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default "mt7981" if TARGET_MT7981
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default "mt7986" if TARGET_MT7986
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default "mt8183" if TARGET_MT8183
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default "mt8512" if TARGET_MT8512
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@ -124,7 +135,7 @@ config MTK_BROM_HEADER_INFO
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string
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default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
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default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
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default "media=snand;nandinfo=2k+64" if TARGET_MT7986
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default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
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default "lk=1" if TARGET_MT7623
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endif
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@ -7,6 +7,7 @@ obj-$(CONFIG_MT8512) += mt8512/
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obj-$(CONFIG_TARGET_MT7622) += mt7622/
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obj-$(CONFIG_TARGET_MT7623) += mt7623/
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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obj-$(CONFIG_TARGET_MT7981) += mt7981/
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obj-$(CONFIG_TARGET_MT7986) += mt7986/
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obj-$(CONFIG_TARGET_MT8183) += mt8183/
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obj-$(CONFIG_TARGET_MT8516) += mt8516/
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4
arch/arm/mach-mediatek/mt7981/Makefile
Normal file
4
arch/arm/mach-mediatek/mt7981/Makefile
Normal file
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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obj-y += lowlevel_init.o
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45
arch/arm/mach-mediatek/mt7981/init.c
Normal file
45
arch/arm/mach-mediatek/mt7981/init.c
Normal file
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@ -0,0 +1,45 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <init.h>
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#include <asm/armv8/mmu.h>
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#include <asm/system.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G);
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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static struct mm_region mt7981_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt7981_mem_map;
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32
arch/arm/mach-mediatek/mt7981/lowlevel_init.S
Normal file
32
arch/arm/mach-mediatek/mt7981/lowlevel_init.S
Normal file
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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/*
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* Switch from AArch64 EL2 to AArch32 EL2
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* @param inputs:
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* x0: argument, zero
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||||
* x1: machine nr
|
||||
* x2: fdt address
|
||||
* x3: input argument
|
||||
* x4: kernel entry point
|
||||
* @param outputs for secure firmware:
|
||||
* x0: function id
|
||||
* x1: kernel entry point
|
||||
* x2: machine nr
|
||||
* x3: fdt address
|
||||
*
|
||||
* [1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/mediatek/common/mtk_sip_svc.c
|
||||
*/
|
||||
|
||||
.global armv8_el2_to_aarch32
|
||||
armv8_el2_to_aarch32:
|
||||
mov x3, x2
|
||||
mov x2, x1
|
||||
mov x1, x4
|
||||
mov x4, #0
|
||||
ldr x0, =0x82000200 /* MTK_SIP_KERNEL_BOOT_AARCH32 */
|
||||
SMC #0
|
||||
ret
|
||||
Loading…
Reference in New Issue
Block a user