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clk/qcom: sdm845: add gdscs

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Define the GDSC power domains for SDM845.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Caleb Connolly 2024-04-03 14:07:41 +02:00
parent d33d4e0a45
commit f2c3708b9c
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GPG Key ID: 0583312B195F64B6
1 changed files with 18 additions and 0 deletions
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18
drivers/clk/qcom/clock-sdm845.c
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@ -146,11 +146,29 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = {
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
static const struct qcom_power_map sdm845_gdscs[] = {
[PCIE_0_GDSC] = { 0x6b004 },
[PCIE_1_GDSC] = { 0x8d004 },
[UFS_CARD_GDSC] = { 0x75004 },
[UFS_PHY_GDSC] = { 0x77004 },
[USB30_PRIM_GDSC] = { 0xf004 },
[USB30_SEC_GDSC] = { 0x10004 },
[HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 },
[HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c },
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 },
[HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 },
[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 },
[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
[HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
};
static struct msm_clk_data sdm845_clk_data = {
.resets = sdm845_gcc_resets,
.num_resets = ARRAY_SIZE(sdm845_gcc_resets),
.clks = sdm845_clks,
.num_clks = ARRAY_SIZE(sdm845_clks),
.power_domains = sdm845_gdscs,
.num_power_domains = ARRAY_SIZE(sdm845_gdscs),
.enable = sdm845_clk_enable,
.set_rate = sdm845_clk_set_rate,