clk: exynos: Add Samsung clock framework
Heavily based on Linux kernel Samsung clock framework, with some changes to accommodate the differences in U-Boot CCF implementation. It's also quite minimal as compared to the Linux version. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Sam Protsenko
Minkyu Kang
parent
0caae9fdc2
commit
ff3e8b8c6c
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@ -1,6 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2016 Samsung Electronics
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# Thomas Abraham <thomas.ab@samsung.com>
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# Copyright (C) 2023 Linaro Ltd.
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#
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# Authors:
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# Thomas Abraham <thomas.ab@samsung.com>
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# Sam Protsenko <semen.protsenko@linaro.org>
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obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
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obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
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obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
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167
drivers/clk/exynos/clk-pll.c
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167
drivers/clk/exynos/clk-pll.c
Normal file
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@ -0,0 +1,167 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Samsung Electronics
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* Copyright (C) 2023 Linaro Ltd.
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*
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* Authors:
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* Thomas Abraham <thomas.ab@samsung.com>
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* Sam Protsenko <semen.protsenko@linaro.org>
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*
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* This file contains the utility functions to register the pll clocks.
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*/
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#include <asm/io.h>
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#include <div64.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <clk.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_SAMSUNG_PLL0822X "samsung_clk_pll0822x"
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#define UBOOT_DM_CLK_SAMSUNG_PLL0831X "samsung_clk_pll0831x"
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struct samsung_clk_pll {
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struct clk clk;
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void __iomem *con_reg;
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enum samsung_pll_type type;
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};
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#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk)
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/*
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* PLL0822x Clock Type
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*/
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#define PLL0822X_MDIV_MASK 0x3ff
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#define PLL0822X_PDIV_MASK 0x3f
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#define PLL0822X_SDIV_MASK 0x7
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#define PLL0822X_MDIV_SHIFT 16
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#define PLL0822X_PDIV_SHIFT 8
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#define PLL0822X_SDIV_SHIFT 0
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static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk)
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{
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struct samsung_clk_pll *pll = to_clk_pll(clk);
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u32 mdiv, pdiv, sdiv, pll_con3;
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u64 fvco = clk_get_parent_rate(clk);
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pll_con3 = readl_relaxed(pll->con_reg);
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mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
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pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
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sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll0822x_clk_min_ops = {
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.get_rate = samsung_pll0822x_recalc_rate,
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};
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/*
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* PLL0831x Clock Type
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*/
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#define PLL0831X_KDIV_MASK 0xffff
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#define PLL0831X_MDIV_MASK 0x1ff
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#define PLL0831X_PDIV_MASK 0x3f
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#define PLL0831X_SDIV_MASK 0x7
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#define PLL0831X_MDIV_SHIFT 16
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#define PLL0831X_PDIV_SHIFT 8
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#define PLL0831X_SDIV_SHIFT 0
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#define PLL0831X_KDIV_SHIFT 0
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static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk)
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{
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struct samsung_clk_pll *pll = to_clk_pll(clk);
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u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
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s16 kdiv;
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u64 fvco = clk_get_parent_rate(clk);
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pll_con3 = readl_relaxed(pll->con_reg);
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pll_con5 = readl_relaxed(pll->con_reg + 8);
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mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
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pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
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sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
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kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
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fvco *= (mdiv << 16) + kdiv;
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do_div(fvco, (pdiv << sdiv));
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fvco >>= 16;
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll0831x_clk_min_ops = {
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.get_rate = samsung_pll0831x_recalc_rate,
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};
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static struct clk *_samsung_clk_register_pll(void __iomem *base,
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const struct samsung_pll_clock *pll_clk)
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{
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struct samsung_clk_pll *pll;
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struct clk *clk;
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const char *drv_name;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->con_reg = base + pll_clk->con_offset;
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pll->type = pll_clk->type;
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clk = &pll->clk;
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clk->flags = pll_clk->flags;
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switch (pll_clk->type) {
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case pll_0822x:
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drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0822X;
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break;
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case pll_0831x:
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drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0831X;
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break;
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default:
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kfree(pll);
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return ERR_PTR(-ENODEV);
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}
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ret = clk_register(clk, drv_name, pll_clk->name, pll_clk->parent_name);
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if (ret) {
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kfree(pll);
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return ERR_PTR(ret);
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}
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return clk;
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}
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void samsung_clk_register_pll(void __iomem *base,
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const struct samsung_pll_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_pll_clock *pll_clk;
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pll_clk = &clk_list[cnt];
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clk = _samsung_clk_register_pll(base, pll_clk);
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clk_dm(pll_clk->id, clk);
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}
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}
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U_BOOT_DRIVER(samsung_pll0822x_clk) = {
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.name = UBOOT_DM_CLK_SAMSUNG_PLL0822X,
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.id = UCLASS_CLK,
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.ops = &samsung_pll0822x_clk_min_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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U_BOOT_DRIVER(samsung_pll0831x_clk) = {
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.name = UBOOT_DM_CLK_SAMSUNG_PLL0831X,
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.id = UCLASS_CLK,
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.ops = &samsung_pll0831x_clk_min_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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23
drivers/clk/exynos/clk-pll.h
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23
drivers/clk/exynos/clk-pll.h
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Samsung Electronics
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* Copyright (C) 2023 Linaro Ltd.
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*
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* Authors:
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* Thomas Abraham <thomas.ab@samsung.com>
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* Sam Protsenko <semen.protsenko@linaro.org>
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*
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* Common Clock Framework support for all PLL's in Samsung platforms.
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*/
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#ifndef __EXYNOS_CLK_PLL_H
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#define __EXYNOS_CLK_PLL_H
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#include <linux/clk-provider.h>
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enum samsung_pll_type {
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pll_0822x,
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pll_0831x,
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};
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#endif /* __EXYNOS_CLK_PLL_H */
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121
drivers/clk/exynos/clk.c
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121
drivers/clk/exynos/clk.c
Normal file
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@ -0,0 +1,121 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2023 Linaro Ltd.
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* Sam Protsenko <semen.protsenko@linaro.org>
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*
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* This file includes utility functions to register clocks to common
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* clock framework for Samsung platforms.
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*/
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#include <dm.h>
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#include "clk.h"
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void samsung_clk_register_mux(void __iomem *base,
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const struct samsung_mux_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_mux_clock *m;
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m = &clk_list[cnt];
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clk = clk_register_mux(NULL, m->name, m->parent_names,
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m->num_parents, m->flags, base + m->offset, m->shift,
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m->width, m->mux_flags);
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clk_dm(m->id, clk);
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}
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}
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void samsung_clk_register_div(void __iomem *base,
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const struct samsung_div_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_div_clock *d;
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d = &clk_list[cnt];
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clk = clk_register_divider(NULL, d->name, d->parent_name,
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d->flags, base + d->offset, d->shift,
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d->width, d->div_flags);
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clk_dm(d->id, clk);
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}
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}
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void samsung_clk_register_gate(void __iomem *base,
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const struct samsung_gate_clock *clk_list,
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unsigned int nr_clk)
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{
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unsigned int cnt;
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for (cnt = 0; cnt < nr_clk; cnt++) {
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struct clk *clk;
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const struct samsung_gate_clock *g;
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g = &clk_list[cnt];
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clk = clk_register_gate(NULL, g->name, g->parent_name,
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g->flags, base + g->offset, g->bit_idx,
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g->gate_flags, NULL);
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clk_dm(g->id, clk);
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}
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}
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typedef void (*samsung_clk_register_fn)(void __iomem *base,
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const void *clk_list,
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unsigned int nr_clk);
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static const samsung_clk_register_fn samsung_clk_register_fns[] = {
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[S_CLK_MUX] = (samsung_clk_register_fn)samsung_clk_register_mux,
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[S_CLK_DIV] = (samsung_clk_register_fn)samsung_clk_register_div,
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[S_CLK_GATE] = (samsung_clk_register_fn)samsung_clk_register_gate,
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[S_CLK_PLL] = (samsung_clk_register_fn)samsung_clk_register_pll,
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};
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/**
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* samsung_cmu_register_clocks() - Register provided clock groups
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* @base: Base address of CMU registers
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* @clk_groups: list of clock groups
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* @nr_groups: count of clock groups in @clk_groups
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*
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* Having the array of clock groups @clk_groups makes it possible to keep a
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* correct clocks registration order.
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*/
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void samsung_cmu_register_clocks(void __iomem *base,
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const struct samsung_clk_group *clk_groups,
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unsigned int nr_groups)
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{
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unsigned int i;
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for (i = 0; i < nr_groups; i++) {
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const struct samsung_clk_group *g = &clk_groups[i];
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samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk);
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}
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}
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/**
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* samsung_cmu_register_one - Register all CMU clocks
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* @dev: CMU device
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* @clk_groups: list of CMU clock groups
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* @nr_groups: count of CMU clock groups in @clk_groups
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*
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* Return: 0 on success or negative value on error.
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*/
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int samsung_cmu_register_one(struct udevice *dev,
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const struct samsung_clk_group *clk_groups,
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unsigned int nr_groups)
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{
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void __iomem *base;
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base = dev_read_addr_ptr(dev);
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if (!base)
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return -EINVAL;
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samsung_cmu_register_clocks(base, clk_groups, nr_groups);
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return 0;
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}
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228
drivers/clk/exynos/clk.h
Normal file
228
drivers/clk/exynos/clk.h
Normal file
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@ -0,0 +1,228 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023 Linaro Ltd.
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* Sam Protsenko <semen.protsenko@linaro.org>
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*
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* Common Clock Framework support for all Samsung platforms.
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*/
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#ifndef __EXYNOS_CLK_H
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#define __EXYNOS_CLK_H
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#include <errno.h>
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#include <linux/clk-provider.h>
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#include "clk-pll.h"
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/**
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* struct samsung_mux_clock - information about mux clock
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* @id: platform specific id of the clock
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* @name: name of this mux clock
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* @parent_names: array of pointer to parent clock names
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* @num_parents: number of parents listed in @parent_names
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* @flags: optional flags for basic clock
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* @offset: offset of the register for configuring the mux
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* @shift: starting bit location of the mux control bit-field in @reg
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* @width: width of the mux control bit-field in @reg
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* @mux_flags: flags for mux-type clock
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*/
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struct samsung_mux_clock {
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unsigned int id;
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const char *name;
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const char * const *parent_names;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 mux_flags;
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};
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#define PNAME(x) static const char * const x[]
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#define __MUX(_id, cname, pnames, o, s, w, f, mf) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = (f) | CLK_SET_RATE_NO_REPARENT, \
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.offset = o, \
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.shift = s, \
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.width = w, \
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.mux_flags = mf, \
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}
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#define MUX(_id, cname, pnames, o, s, w) \
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__MUX(_id, cname, pnames, o, s, w, 0, 0)
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#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
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__MUX(_id, cname, pnames, o, s, w, f, mf)
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/**
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* struct samsung_div_clock - information about div clock
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* @id: platform specific id of the clock
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* @name: name of this div clock
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* @parent_name: name of the parent clock
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* @flags: optional flags for basic clock
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* @offset: offset of the register for configuring the div
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* @shift: starting bit location of the div control bit-field in @reg
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* @width: width of the bitfield
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* @div_flags: flags for div-type clock
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*/
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struct samsung_div_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 div_flags;
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};
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#define __DIV(_id, cname, pname, o, s, w, f, df) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.flags = f, \
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.offset = o, \
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.shift = s, \
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.width = w, \
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.div_flags = df, \
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}
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#define DIV(_id, cname, pname, o, s, w) \
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__DIV(_id, cname, pname, o, s, w, 0, 0)
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#define DIV_F(_id, cname, pname, o, s, w, f, df) \
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__DIV(_id, cname, pname, o, s, w, f, df)
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/**
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* struct samsung_gate_clock - information about gate clock
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* @id: platform specific id of the clock
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* @name: name of this gate clock
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* @parent_name: name of the parent clock
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* @flags: optional flags for basic clock
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* @offset: offset of the register for configuring the gate
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* @bit_idx: bit index of the gate control bit-field in @reg
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* @gate_flags: flags for gate-type clock
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*/
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struct samsung_gate_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
unsigned long offset;
|
||||
u8 bit_idx;
|
||||
u8 gate_flags;
|
||||
};
|
||||
|
||||
#define __GATE(_id, cname, pname, o, b, f, gf) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = cname, \
|
||||
.parent_name = pname, \
|
||||
.flags = f, \
|
||||
.offset = o, \
|
||||
.bit_idx = b, \
|
||||
.gate_flags = gf, \
|
||||
}
|
||||
|
||||
#define GATE(_id, cname, pname, o, b, f, gf) \
|
||||
__GATE(_id, cname, pname, o, b, f, gf)
|
||||
|
||||
/**
|
||||
* struct samsung_pll_clock - information about pll clock
|
||||
* @id: platform specific id of the clock
|
||||
* @name: name of this pll clock
|
||||
* @parent_name: name of the parent clock
|
||||
* @flags: optional flags for basic clock
|
||||
* @con_offset: offset of the register for configuring the PLL
|
||||
* @type: type of PLL to be registered
|
||||
*/
|
||||
struct samsung_pll_clock {
|
||||
unsigned int id;
|
||||
const char *name;
|
||||
const char *parent_name;
|
||||
unsigned long flags;
|
||||
int con_offset;
|
||||
enum samsung_pll_type type;
|
||||
};
|
||||
|
||||
#define PLL(_typ, _id, _name, _pname, _con) \
|
||||
{ \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _pname, \
|
||||
.flags = CLK_GET_RATE_NOCACHE, \
|
||||
.con_offset = _con, \
|
||||
.type = _typ, \
|
||||
}
|
||||
|
||||
enum samsung_clock_type {
|
||||
S_CLK_MUX,
|
||||
S_CLK_DIV,
|
||||
S_CLK_GATE,
|
||||
S_CLK_PLL,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct samsung_clock_group - contains a list of clocks of one type
|
||||
* @type: type of clocks this structure contains
|
||||
* @clk_list: list of clocks
|
||||
* @nr_clk: count of clocks in @clk_list
|
||||
*/
|
||||
struct samsung_clk_group {
|
||||
enum samsung_clock_type type;
|
||||
const void *clk_list;
|
||||
unsigned int nr_clk;
|
||||
};
|
||||
|
||||
void samsung_clk_register_mux(void __iomem *base,
|
||||
const struct samsung_mux_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
void samsung_clk_register_div(void __iomem *base,
|
||||
const struct samsung_div_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
void samsung_clk_register_gate(void __iomem *base,
|
||||
const struct samsung_gate_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
void samsung_clk_register_pll(void __iomem *base,
|
||||
const struct samsung_pll_clock *clk_list,
|
||||
unsigned int nr_clk);
|
||||
|
||||
void samsung_cmu_register_clocks(void __iomem *base,
|
||||
const struct samsung_clk_group *clk_groups,
|
||||
unsigned int nr_groups);
|
||||
int samsung_cmu_register_one(struct udevice *dev,
|
||||
const struct samsung_clk_group *clk_groups,
|
||||
unsigned int nr_groups);
|
||||
|
||||
/**
|
||||
* samsung_register_cmu - Register CMU clocks ensuring parent CMU is present
|
||||
* @dev: CMU device
|
||||
* @clk_groups: list of CMU clock groups
|
||||
* @parent_drv: name of parent CMU driver
|
||||
*
|
||||
* Register provided CMU clocks, but make sure CMU_TOP driver is instantiated
|
||||
* first.
|
||||
*
|
||||
* Return: 0 on success or negative value on error.
|
||||
*/
|
||||
#define samsung_register_cmu(dev, clk_groups, parent_drv) \
|
||||
({ \
|
||||
struct udevice *__parent; \
|
||||
int __ret; \
|
||||
\
|
||||
__ret = uclass_get_device_by_driver(UCLASS_CLK, \
|
||||
DM_DRIVER_GET(parent_drv), &__parent); \
|
||||
if (__ret || !__parent) \
|
||||
__ret = -ENOENT; \
|
||||
else \
|
||||
__ret = samsung_cmu_register_one(dev, clk_groups, \
|
||||
ARRAY_SIZE(clk_groups)); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#endif /* __EXYNOS_CLK_H */
|
||||
Loading…
Reference in New Issue
Block a user