8c19506bc5
Enable Kconfig options for the two USB 2.0 ports and bottom USB 3.0 port on ROCK 5 Model A. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
87 lines
2.3 KiB
Plaintext
87 lines
2.3 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00a00000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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CONFIG_DEFAULT_DEVICE_TREE="rk3588s-rock-5a"
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CONFIG_ROCKCHIP_RK3588=y
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CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK_R_ADDR=0x1000000
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CONFIG_TARGET_ROCK5A_RK3588=y
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CONFIG_SPL_STACK=0x1000000
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CONFIG_DEBUG_UART_BASE=0xFEB50000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SYS_LOAD_ADDR=0xc00800
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x4000000
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CONFIG_SPL_BSS_MAX_SIZE=0x4000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_ATF=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_REGULATOR=y
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# CONFIG_SPL_DOS_PARTITION is not set
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_SUPPORT_EMMC_RPMB=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DWC_ETH_QOS=y
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CONFIG_DWC_ETH_QOS_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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CONFIG_PHY_ROCKCHIP_USBDP=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_SPL_RAM=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_DM_USB_GADGET=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_ERRNO_STR=y
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