b29dbf98ba
When coreboot does not pass a UART in its sysinfo struct, there is no easy way to find it out. Since coreboot does not actually init the serial device when serial is disabled, it is not possible to make it add this information to the sysinfo table. Add a way to obtain this information from the DBG2 ACPI table, which is normally set up by coreboot. For now this only supports a memory-mapped 16550-style UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* UART support for U-Boot when launched from Coreboot
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*
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* Copyright 2019 Google LLC
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*/
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#define LOG_CATGEGORY UCLASS_SERIAL
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <ns16550.h>
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#include <serial.h>
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#include <acpi/acpi_table.h>
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#include <asm/cb_sysinfo.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int read_dbg2(struct ns16550_plat *plat)
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{
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struct acpi_table_header *tab;
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struct acpi_dbg2_header *hdr;
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struct acpi_dbg2_device *dbg;
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struct acpi_gen_regaddr *addr;
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u32 *addr_size;
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log_debug("Looking for DBG2 in ACPI tables\n");
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if (!gd->acpi_start) {
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log_debug("No ACPI tables\n");
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return -ENOENT;
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}
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tab = acpi_find_table("DBG2");
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if (!tab) {
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log_debug("No DBG2 table\n");
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return -ENOENT;
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}
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hdr = container_of(tab, struct acpi_dbg2_header, header);
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/* We only use the first device, but check that there is at least one */
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if (!hdr->devices_count) {
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log_debug("No devices\n");
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return -ENOENT;
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}
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if (hdr->devices_offset >= tab->length) {
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log_debug("Invalid offset\n");
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return -EINVAL;
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}
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dbg = (void *)hdr + hdr->devices_offset;
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if (dbg->revision) {
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log_debug("Invalid revision %d\n", dbg->revision);
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return -EINVAL;
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}
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if (!dbg->address_count) {
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log_debug("No addresses\n");
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return -EINVAL;
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}
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if (dbg->port_type != ACPI_DBG2_SERIAL_PORT) {
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log_debug("Not a serial port\n");
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return -EPROTOTYPE;
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}
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if (dbg->port_subtype != ACPI_DBG2_16550_COMPATIBLE) {
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log_debug("Incompatible serial port\n");
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return -EPROTOTYPE;
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}
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if (dbg->base_address_offset >= dbg->length ||
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dbg->address_size_offset >= dbg->length) {
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log_debug("Invalid base address/size offsets %d, %d\n",
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dbg->base_address_offset, dbg->address_size_offset);
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return -EINVAL;
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}
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addr_size = (void *)dbg + dbg->address_size_offset;
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if (!*addr_size) {
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log_debug("Zero address size\n");
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return -EINVAL;
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}
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addr = (void *)dbg + dbg->base_address_offset;
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if (addr->space_id != ACPI_ADDRESS_SPACE_MEMORY) {
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log_debug("Incompatible space %d\n", addr->space_id);
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return -EPROTOTYPE;
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}
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plat->base = addr->addrl;
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/* ACPI_ACCESS_SIZE_DWORD_ACCESS is 3; we want 2 */
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plat->reg_shift = addr->access_size - 1;
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plat->reg_width = 4; /* coreboot sets bit_width to 0 */
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plat->clock = 1843200;
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plat->fcr = UART_FCR_DEFVAL;
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plat->flags = 0;
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log_debug("Collected UART from ACPI DBG2 table\n");
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return 0;
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}
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static int coreboot_of_to_plat(struct udevice *dev)
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{
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struct ns16550_plat *plat = dev_get_plat(dev);
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struct cb_serial *cb_info = lib_sysinfo.serial;
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int ret = -ENOENT;
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if (cb_info) {
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plat->base = cb_info->baseaddr;
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plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
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plat->reg_width = cb_info->regwidth;
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plat->clock = cb_info->input_hertz;
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plat->fcr = UART_FCR_DEFVAL;
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plat->flags = 0;
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if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
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plat->flags |= NS16550_FLAG_IO;
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ret = 0;
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} else if (IS_ENABLED(CONFIG_COREBOOT_SERIAL_FROM_DBG2)) {
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ret = read_dbg2(plat);
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}
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if (ret) {
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/*
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* Returning an error will cause U-Boot to complain that
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* there is no UART, which may panic. So stay silent and
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* pray that the video console will work.
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*/
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log_debug("Cannot detect UART\n");
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}
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return 0;
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}
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static const struct udevice_id coreboot_serial_ids[] = {
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{ .compatible = "coreboot-serial" },
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{ },
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};
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U_BOOT_DRIVER(coreboot_uart) = {
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.name = "coreboot_uart",
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.id = UCLASS_SERIAL,
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.of_match = coreboot_serial_ids,
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.priv_auto = sizeof(struct ns16550),
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.plat_auto = sizeof(struct ns16550_plat),
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.of_to_plat = coreboot_of_to_plat,
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.probe = ns16550_serial_probe,
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.ops = &ns16550_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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