5e7cd8a119
With the stack and text base used by U-Boot SPL and proper on RK3399 there is a high likelihood of overlapping when U-Boot proper + FDT nears or exceeded 1 MiB in size. Currently the following memory layout is typically used on RK3399: [ 0, 256K) - SPL binary [ 256K, 2M) - TF-A / reserved [ 2M, +X) - U-Boot proper binary (TEXT_BASE) [ -X, 3M) - U-Boot proper pre-reloc stack (CUSTOM_SYS_INIT_SP_ADDR) [ -16K, 3M) - pre-reloc malloc heap (SYS_MALLOC_F_LEN) [ -X, 4M) - SPL pre-reloc stack (SPL_STACK) [ -16K, 4M) - pre-reloc malloc heap (SPL_SYS_MALLOC_F_LEN) [ 4M, +8K) - SPL bss (SPL_BSS_START_ADDR, SPL_BSS_MAX_SIZE) [ -X, 64M) - SPL reloc stack (SPL_STACK_R_ADDR) [ 63M, 64M) - reloc malloc heap (SPL_STACK_R_MALLOC_SIMPLE_LEN) SPL can safely load U-Boot proper + FDT to [2M, 4M-16K) with this layout. However, the stack at [-X, 3M) used during U-Boot proper pre-reloc is restricting the safe size of U-Boot proper + FDT to be less than 1 MiB. Migrate to use common bss, stack and malloc heap size and addresses to fix this restriction and allow for a larger U-Boot proper image size. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
61 lines
1.6 KiB
Plaintext
61 lines
1.6 KiB
Plaintext
CONFIG_ARM=y
|
|
CONFIG_SKIP_LOWLEVEL_INIT=y
|
|
CONFIG_COUNTER_FREQUENCY=24000000
|
|
CONFIG_ARCH_ROCKCHIP=y
|
|
CONFIG_NR_DRAM_BANKS=1
|
|
CONFIG_ENV_OFFSET=0x3F8000
|
|
CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi"
|
|
CONFIG_ROCKCHIP_RK3399=y
|
|
CONFIG_TARGET_EVB_RK3399=y
|
|
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
|
CONFIG_SYS_LOAD_ADDR=0x800800
|
|
CONFIG_DEBUG_UART=y
|
|
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
|
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
CONFIG_SPL_MAX_SIZE=0x2e000
|
|
CONFIG_SPL_PAD_TO=0x7f8000
|
|
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
|
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
|
CONFIG_TPL=y
|
|
CONFIG_CMD_BOOTZ=y
|
|
CONFIG_CMD_GPT=y
|
|
CONFIG_CMD_MMC=y
|
|
CONFIG_CMD_USB=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
CONFIG_CMD_TIME=y
|
|
CONFIG_SPL_OF_CONTROL=y
|
|
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
|
CONFIG_ENV_IS_IN_MMC=y
|
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
CONFIG_ROCKCHIP_GPIO=y
|
|
CONFIG_SYS_I2C_ROCKCHIP=y
|
|
CONFIG_MMC_DW=y
|
|
CONFIG_MMC_DW_ROCKCHIP=y
|
|
CONFIG_MMC_SDHCI=y
|
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
|
CONFIG_ETH_DESIGNWARE=y
|
|
CONFIG_GMAC_ROCKCHIP=y
|
|
CONFIG_PMIC_RK8XX=y
|
|
CONFIG_REGULATOR_PWM=y
|
|
CONFIG_REGULATOR_RK8XX=y
|
|
CONFIG_PWM_ROCKCHIP=y
|
|
CONFIG_BAUDRATE=1500000
|
|
CONFIG_DEBUG_UART_SHIFT=2
|
|
CONFIG_SYS_NS16550_MEM32=y
|
|
CONFIG_SYSRESET=y
|
|
CONFIG_USB=y
|
|
CONFIG_USB_XHCI_HCD=y
|
|
CONFIG_USB_EHCI_HCD=y
|
|
CONFIG_USB_EHCI_GENERIC=y
|
|
CONFIG_USB_DWC3=y
|
|
CONFIG_USB_DWC3_GENERIC=y
|
|
CONFIG_USB_HOST_ETHER=y
|
|
CONFIG_USB_ETHER_ASIX=y
|
|
CONFIG_USB_ETHER_ASIX88179=y
|
|
CONFIG_USB_ETHER_MCS7830=y
|
|
CONFIG_USB_ETHER_RTL8152=y
|
|
CONFIG_USB_ETHER_SMSC95XX=y
|
|
CONFIG_SPL_TINY_MEMSET=y
|
|
CONFIG_ERRNO_STR=y
|