ef5ba2cef4
All the source code of clk-mem-n5x.c and clk-n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
490 lines
13 KiB
C
490 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2020-2022 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dm/util.h>
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#include <dt-bindings/clock/n5x-clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct socfpga_clk_plat {
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void __iomem *regs;
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};
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
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cm_wait_for_fsm();
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}
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static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
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{
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CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
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cm_wait_for_fsm();
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}
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/*
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* Setup clocks while making no assumptions about previous state of the clocks.
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*/
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static void clk_basic_init(struct udevice *dev,
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const struct cm_config * const cfg)
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{
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struct socfpga_clk_plat *plat = dev_get_plat(dev);
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if (!cfg)
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return;
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#if IS_ENABLED(CONFIG_SPL_BUILD)
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/* Always force clock manager into boot mode before any configuration */
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clk_write_ctrl(plat,
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CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
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#else
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/* Skip clock configuration in SSBL if it's not in boot mode */
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if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
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return;
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#endif
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/* Put both PLLs in bypass */
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clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
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clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
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/* Put both PLLs in Reset */
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CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
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CLKMGR_PLLCTRL_BYPASS_MASK);
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CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
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CLKMGR_PLLCTRL_BYPASS_MASK);
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/* setup main PLL */
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CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
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CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
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CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
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CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
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CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
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CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
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/* setup peripheral */
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CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
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CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
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CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
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CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
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CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
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/* Take both PLL out of reset and power up */
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CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
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CLKMGR_PLLCTRL_BYPASS_MASK);
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CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
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CLKMGR_PLLCTRL_BYPASS_MASK);
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cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
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CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
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CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
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CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
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CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
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CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
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CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
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CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
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CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
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/* Configure ping pong counters in altera group */
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CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
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CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
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CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
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CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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CLKMGR_MAINPLL_PLLGLOB);
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CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
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CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
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CLKMGR_PERPLL_PLLGLOB);
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/* Take all PLLs out of bypass */
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clk_write_bypass_mainpll(plat, 0);
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clk_write_bypass_perpll(plat, 0);
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/* Clear the loss of lock bits */
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CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
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CLKMGR_INTER_PERPLLLOST_MASK |
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CLKMGR_INTER_MAINPLLLOST_MASK);
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/* Take all ping pong counters out of reset */
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CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
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CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK);
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/* Out of boot mode */
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clk_write_ctrl(plat,
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CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
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}
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static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32 reg)
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{
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u32 clksrc = CM_REG_READL(plat, reg);
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return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
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}
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static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat,
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u32 pllglob_reg, u32 plldiv_reg)
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{
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u64 clock = 0;
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u32 clklsrc, divf, divr, divq, power = 1;
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/* Get input clock frequency */
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clklsrc = (CM_REG_READL(plat, pllglob_reg) &
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CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
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CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
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switch (clklsrc) {
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case CLKMGR_VCO_PSRC_EOSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_VCO_PSRC_F2S:
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clock = cm_get_fpga_clk_hz();
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break;
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}
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/* Calculate pll out clock frequency */
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divf = (CM_REG_READL(plat, plldiv_reg) &
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CLKMGR_PLLDIV_FDIV_MASK) >>
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CLKMGR_PLLDIV_FDIV_OFFSET;
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divr = (CM_REG_READL(plat, plldiv_reg) &
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CLKMGR_PLLDIV_REFCLKDIV_MASK) >>
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CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
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divq = (CM_REG_READL(plat, plldiv_reg) &
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CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >>
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CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
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while (divq) {
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power *= 2;
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divq--;
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}
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return (clock * 2 * (divf + 1)) / ((divr + 1) * power);
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}
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static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
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u32 main_div, u32 per_div)
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{
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u64 clock = 0;
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u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
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switch (clklsrc) {
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case CLKMGR_CLKSRC_MAIN:
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clock = clk_get_pll_output_hz(plat,
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CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLDIV);
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clock /= 1 + main_div;
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break;
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case CLKMGR_CLKSRC_PER:
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clock = clk_get_pll_output_hz(plat,
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CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLDIV);
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clock /= 1 + per_div;
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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default:
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return 0;
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}
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return clock;
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}
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static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
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{
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u32 mainpll_c0cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
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u32 perpll_c0cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
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u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
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mainpll_c0cnt, perpll_c0cnt);
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clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
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CLKMGR_CLKCNT_MSK);
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return clock;
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}
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static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
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{
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u32 mainpll_c1cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
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u32 perpll_c1cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
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return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
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mainpll_c1cnt, perpll_c1cnt);
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}
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static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
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{
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u64 clock = clk_get_l3_main_clk_hz(plat);
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clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
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CLKMGR_NOCDIV_L4MAIN_OFFSET) &
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CLKMGR_NOCDIV_DIVIDER_MASK);
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return clock;
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}
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static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
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{
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u32 mainpll_c3cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
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u32 perpll_c3cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
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u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
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mainpll_c3cnt, perpll_c3cnt);
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clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
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CLKMGR_CLKCNT_MSK);
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return clock / 4;
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}
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static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
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{
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u64 clock = clk_get_l3_main_clk_hz(plat);
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clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
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CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
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CLKMGR_NOCDIV_DIVIDER_MASK);
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return clock;
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}
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static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
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{
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u64 clock = clk_get_l3_main_clk_hz(plat);
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clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
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CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
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CLKMGR_NOCDIV_DIVIDER_MASK);
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return clock;
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}
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static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
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{
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if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
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return clk_get_l3_main_clk_hz(plat) / 2;
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return clk_get_l3_main_clk_hz(plat) / 4;
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}
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static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
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{
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bool emacsel_a;
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u32 ctl;
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u32 ctr_reg;
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u32 clock;
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u32 div;
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u32 reg;
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/* Get EMAC clock source */
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ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
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if (emac_id == N5X_EMAC0_CLK)
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ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
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CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
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else if (emac_id == N5X_EMAC1_CLK)
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ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
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CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
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else if (emac_id == N5X_EMAC2_CLK)
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ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
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CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
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else
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return 0;
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if (ctl) {
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/* EMAC B source */
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emacsel_a = false;
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ctr_reg = CLKMGR_ALTR_EMACBCTR;
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} else {
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/* EMAC A source */
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emacsel_a = true;
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ctr_reg = CLKMGR_ALTR_EMACACTR;
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}
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reg = CM_REG_READL(plat, ctr_reg);
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clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
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>> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
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div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
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>> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
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switch (clock) {
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case CLKMGR_CLKSRC_MAIN:
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clock = clk_get_pll_output_hz(plat,
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CLKMGR_MAINPLL_PLLGLOB,
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CLKMGR_MAINPLL_PLLDIV);
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if (emacsel_a) {
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clock /= 1 + ((CM_REG_READL(plat,
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CLKMGR_MAINPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
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} else {
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clock /= 1 + ((CM_REG_READL(plat,
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CLKMGR_MAINPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C3CNT_OFFSET);
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}
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break;
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case CLKMGR_CLKSRC_PER:
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clock = clk_get_pll_output_hz(plat,
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CLKMGR_PERPLL_PLLGLOB,
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CLKMGR_PERPLL_PLLDIV);
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if (emacsel_a) {
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clock /= 1 + ((CM_REG_READL(plat,
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CLKMGR_PERPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
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CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
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} else {
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clock /= 1 + ((CM_REG_READL(plat,
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CLKMGR_PERPLL_PLLOUTDIV) &
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CLKMGR_PLLOUTDIV_C3CNT_MASK >>
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CLKMGR_PLLOUTDIV_C3CNT_OFFSET));
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}
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break;
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case CLKMGR_CLKSRC_OSC1:
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clock = cm_get_osc_clk_hz();
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break;
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case CLKMGR_CLKSRC_INTOSC:
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clock = cm_get_intosc_clk_hz();
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break;
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case CLKMGR_CLKSRC_FPGA:
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clock = cm_get_fpga_clk_hz();
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break;
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}
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clock /= 1 + div;
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return clock;
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}
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static ulong socfpga_clk_get_rate(struct clk *clk)
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{
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struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
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switch (clk->id) {
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case N5X_MPU_CLK:
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return clk_get_mpu_clk_hz(plat);
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case N5X_L4_MAIN_CLK:
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return clk_get_l4_main_clk_hz(plat);
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case N5X_L4_SYS_FREE_CLK:
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return clk_get_l4_sys_free_clk_hz(plat);
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case N5X_L4_MP_CLK:
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return clk_get_l4_mp_clk_hz(plat);
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case N5X_L4_SP_CLK:
|
|
return clk_get_l4_sp_clk_hz(plat);
|
|
case N5X_SDMMC_CLK:
|
|
return clk_get_sdmmc_clk_hz(plat);
|
|
case N5X_EMAC0_CLK:
|
|
case N5X_EMAC1_CLK:
|
|
case N5X_EMAC2_CLK:
|
|
return clk_get_emac_clk_hz(plat, clk->id);
|
|
case N5X_USB_CLK:
|
|
case N5X_NAND_X_CLK:
|
|
return clk_get_l4_mp_clk_hz(plat);
|
|
case N5X_NAND_CLK:
|
|
return clk_get_l4_mp_clk_hz(plat) / 4;
|
|
default:
|
|
return -ENXIO;
|
|
}
|
|
}
|
|
|
|
static int socfpga_clk_enable(struct clk *clk)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int socfpga_clk_probe(struct udevice *dev)
|
|
{
|
|
const struct cm_config *cm_default_cfg = cm_get_default_config();
|
|
|
|
clk_basic_init(dev, cm_default_cfg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int socfpga_clk_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct socfpga_clk_plat *plat = dev_get_plat(dev);
|
|
fdt_addr_t addr;
|
|
|
|
addr = devfdt_get_addr(dev);
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
plat->regs = (void __iomem *)addr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops socfpga_clk_ops = {
|
|
.enable = socfpga_clk_enable,
|
|
.get_rate = socfpga_clk_get_rate,
|
|
};
|
|
|
|
static const struct udevice_id socfpga_clk_match[] = {
|
|
{ .compatible = "intel,n5x-clkmgr" },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(socfpga_n5x_clk) = {
|
|
.name = "clk-n5x",
|
|
.id = UCLASS_CLK,
|
|
.of_match = socfpga_clk_match,
|
|
.ops = &socfpga_clk_ops,
|
|
.probe = socfpga_clk_probe,
|
|
.of_to_plat = socfpga_clk_of_to_plat,
|
|
.plat_auto = sizeof(struct socfpga_clk_plat),
|
|
};
|