2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
381 lines
11 KiB
C
381 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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/**
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* enum ratio - Description of a core clock ratio
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* @RAT_UNK: Unknown ratio
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* @RAT_BYP: Bypass
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* @RAT_1_TO_8: Ratio 1:8
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* @RAT_1_TO_4: Ratio 1:4
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* @RAT_1_TO_2: Ratio 1:2
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* @RAT_1_TO_1: Ratio 1:1
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* @RAT_1_5_TO_1: Ratio 1.5:1
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* @RAT_2_TO_1: Ratio 2:1
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* @RAT_2_5_TO_1: Ratio 2.5:1
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* @RAT_3_TO_1: Ratio 3:1
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*/
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#include <linux/bitops.h>
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enum ratio {
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RAT_UNK,
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RAT_BYP,
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RAT_1_TO_8,
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RAT_1_TO_4,
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RAT_1_TO_2,
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RAT_1_TO_1,
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RAT_1_5_TO_1,
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RAT_2_TO_1,
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RAT_2_5_TO_1,
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RAT_3_TO_1
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};
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/**
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* struct corecnf - Description for a core clock configuration
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* @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
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* @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider)
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*/
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struct corecnf {
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int core_csb_ratio;
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int vco_divider;
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};
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/*
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* Table with all valid Core CSB frequency ratio / VCO divider combinations as
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* indexed by the COREPLL field of the SPMR
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*/
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static const struct corecnf corecnf_tab[] = {
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{RAT_BYP, RAT_BYP}, /* 0x00 */
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{RAT_BYP, RAT_BYP}, /* 0x01 */
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{RAT_BYP, RAT_BYP}, /* 0x02 */
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{RAT_BYP, RAT_BYP}, /* 0x03 */
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{RAT_BYP, RAT_BYP}, /* 0x04 */
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{RAT_BYP, RAT_BYP}, /* 0x05 */
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{RAT_BYP, RAT_BYP}, /* 0x06 */
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{RAT_BYP, RAT_BYP}, /* 0x07 */
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{RAT_1_TO_1, RAT_1_TO_2}, /* 0x08 */
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{RAT_1_TO_1, RAT_1_TO_4}, /* 0x09 */
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{RAT_1_TO_1, RAT_1_TO_8}, /* 0x0A */
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{RAT_1_TO_1, RAT_1_TO_8}, /* 0x0B */
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{RAT_1_5_TO_1, RAT_1_TO_2}, /* 0x0C */
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{RAT_1_5_TO_1, RAT_1_TO_4}, /* 0x0D */
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{RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0E */
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{RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0F */
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{RAT_2_TO_1, RAT_1_TO_2}, /* 0x10 */
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{RAT_2_TO_1, RAT_1_TO_4}, /* 0x11 */
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{RAT_2_TO_1, RAT_1_TO_8}, /* 0x12 */
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{RAT_2_TO_1, RAT_1_TO_8}, /* 0x13 */
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{RAT_2_5_TO_1, RAT_1_TO_2}, /* 0x14 */
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{RAT_2_5_TO_1, RAT_1_TO_4}, /* 0x15 */
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{RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x16 */
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{RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x17 */
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{RAT_3_TO_1, RAT_1_TO_2}, /* 0x18 */
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{RAT_3_TO_1, RAT_1_TO_4}, /* 0x19 */
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{RAT_3_TO_1, RAT_1_TO_8}, /* 0x1A */
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{RAT_3_TO_1, RAT_1_TO_8}, /* 0x1B */
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};
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/**
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* enum reg_type - Register to read a field from
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* @REG_SCCR: Use the SCCR register
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* @REG_SPMR: Use the SPMR register
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*/
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enum reg_type {
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REG_SCCR,
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REG_SPMR,
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};
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/**
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* enum mode_type - Description of how to read a specific frequency value
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* @TYPE_INVALID: Unknown type, will provoke error
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* @TYPE_SCCR_STANDARD: Read a field from the SCCR register, and use it
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* as a divider for the CSB clock to compute the
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* frequency
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* @TYPE_SCCR_ONOFF: The field describes a bit flag that can turn the
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* clock on or off
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* @TYPE_SPMR_DIRECT_MULTIPLY: Read a field from the SPMR register, and use it
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* as a multiplier for the CSB clock to compute the
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* frequency
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* @TYPE_SPECIAL: The frequency is calculated in a non-standard way
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*/
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enum mode_type {
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TYPE_INVALID = 0,
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TYPE_SCCR_STANDARD,
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TYPE_SCCR_ONOFF,
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TYPE_SPMR_DIRECT_MULTIPLY,
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TYPE_SPECIAL,
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};
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/* Map of each clock index to its human-readable name */
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static const char * const names[] = {
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[MPC83XX_CLK_CORE] = "Core",
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[MPC83XX_CLK_CSB] = "Coherent System Bus",
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[MPC83XX_CLK_QE] = "QE",
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[MPC83XX_CLK_BRG] = "BRG",
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[MPC83XX_CLK_LBIU] = "Local Bus Controller",
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[MPC83XX_CLK_LCLK] = "Local Bus",
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[MPC83XX_CLK_MEM] = "DDR",
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[MPC83XX_CLK_MEM_SEC] = "DDR Secondary",
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[MPC83XX_CLK_ENC] = "SEC",
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[MPC83XX_CLK_I2C1] = "I2C1",
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[MPC83XX_CLK_I2C2] = "I2C2",
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[MPC83XX_CLK_TDM] = "TDM",
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[MPC83XX_CLK_SDHC] = "SDHC",
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[MPC83XX_CLK_TSEC1] = "TSEC1",
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[MPC83XX_CLK_TSEC2] = "TSEC2",
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[MPC83XX_CLK_USBDR] = "USB DR",
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[MPC83XX_CLK_USBMPH] = "USB MPH",
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[MPC83XX_CLK_PCIEXP1] = "PCIEXP1",
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[MPC83XX_CLK_PCIEXP2] = "PCIEXP2",
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[MPC83XX_CLK_SATA] = "SATA",
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[MPC83XX_CLK_DMAC] = "DMAC",
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[MPC83XX_CLK_PCI] = "PCI",
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};
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/**
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* struct clk_mode - Structure for clock mode descriiptions
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* @low: The low bit of the data field to read for this mode (may not apply to
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* some modes)
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* @high: The high bit of the data field to read for this mode (may not apply to
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* some modes)
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* @type: The type of the mode description (one of enum mode_type)
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*/
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struct clk_mode {
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u8 low;
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u8 high;
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int type;
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};
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/**
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* set_mode() - Build a clock mode description from data
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* @mode: The clock mode description to be filled out
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* @low: The low bit of the data field to read for this mode (may not apply to
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* some modes)
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* @high: The high bit of the data field to read for this mode (may not apply to
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* some modes)
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* @type: The type of the mode description (one of enum mode_type)
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*
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* Clock mode descriptions are a succinct description of how to read a specific
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* clock's rate from the hardware; usually by reading a specific field of a
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* register, such a s the SCCR register, but some types use different methods
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* for obtaining the clock rate.
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*/
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static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type)
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{
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mode->low = low;
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mode->high = high;
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mode->type = type;
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}
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/**
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* retrieve_mode() - Get the clock mode description for a specific clock
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* @clk: The identifier of the clock for which the clock description should
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* be retrieved
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* @soc_type: The type of MPC83xx SoC for which the clock description should be
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* retrieved
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* @mode: Pointer to a clk_mode structure to be filled with data for the
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* clock
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*
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* Since some clock rate are stored in different places on different MPC83xx
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* SoCs, the SoC type has to be supplied along with the clock's identifier.
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*
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* Return: 0 if OK, -ve on error
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*/
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static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
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{
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switch (clk) {
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case MPC83XX_CLK_CORE:
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case MPC83XX_CLK_CSB:
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case MPC83XX_CLK_QE:
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case MPC83XX_CLK_BRG:
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case MPC83XX_CLK_LCLK:
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case MPC83XX_CLK_I2C2:
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set_mode(mode, 0, 0, TYPE_SPECIAL);
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break;
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case MPC83XX_CLK_MEM:
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set_mode(mode, 1, 1, TYPE_SPMR_DIRECT_MULTIPLY);
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break;
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case MPC83XX_CLK_LBIU:
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case MPC83XX_CLK_MEM_SEC:
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set_mode(mode, 0, 0, TYPE_SPMR_DIRECT_MULTIPLY);
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break;
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case MPC83XX_CLK_TSEC1:
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set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_TSEC2:
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if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */
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set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
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else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
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set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_SDHC:
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set_mode(mode, 4, 5, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_ENC:
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set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_I2C1:
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if (soc_type == SOC_MPC8349)
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set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
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else /* I2C and ENC are the same register */
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set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_PCIEXP1:
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set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_PCIEXP2:
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set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_USBDR:
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if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349)
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set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
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else
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set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_USBMPH:
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set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_PCI:
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set_mode(mode, 15, 15, TYPE_SCCR_ONOFF);
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break;
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case MPC83XX_CLK_DMAC:
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set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
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break;
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case MPC83XX_CLK_SATA:
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/* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */
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if (soc_type == SOC_MPC8379) {
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set_mode(mode, 24, 25, TYPE_SCCR_STANDARD);
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set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
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set_mode(mode, 28, 29, TYPE_SCCR_STANDARD);
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set_mode(mode, 30, 31, TYPE_SCCR_STANDARD);
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} else {
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set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
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set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
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}
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break;
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case MPC83XX_CLK_TDM:
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set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
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break;
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default:
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debug("%s: Unknown clock type %d on soc type %d\n",
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__func__, clk, soc_type);
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set_mode(mode, 0, 0, TYPE_INVALID);
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return -EINVAL;
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}
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return 0;
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}
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/**
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* get_spmr() - Read the SPMR (System PLL Mode Register)
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* @im: Pointer to the MPC83xx main register map in question
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*
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* Return: The SPMR value as a 32-bit number.
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*/
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static inline u32 get_spmr(immap_t *im)
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{
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u32 res = in_be32(&im->clk.spmr);
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return res;
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}
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/**
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* get_sccr() - Read the SCCR (System Clock Control Register)
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* @im: Pointer to the MPC83xx main register map in question
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*
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* Return: The SCCR value as a 32-bit number.
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*/
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static inline u32 get_sccr(immap_t *im)
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{
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u32 res = in_be32(&im->clk.sccr);
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return res;
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}
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/**
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* get_lcrr() - Read the LCRR (Clock Ratio Register)
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* @im: Pointer to the MPC83xx main register map in question
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*
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* Return: The LCRR value as a 32-bit number.
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*/
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static inline u32 get_lcrr(immap_t *im)
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{
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u32 res = in_be32(&im->im_lbc.lcrr);
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return res;
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}
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/**
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* get_pci_sync_in() - Read the PCI synchronization clock speed
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* @im: Pointer to the MPC83xx main register map in question
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*
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* Return: The PCI synchronization clock speed value as a 32-bit number.
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*/
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static inline u32 get_pci_sync_in(immap_t *im)
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{
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u8 clkin_div;
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clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
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return get_board_sys_clk() / (1 + clkin_div);
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}
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/**
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* get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
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* @im: Pointer to the MPC83xx main register map in question
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*
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* Return: The CSB clock speed value as a 32-bit number.
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*/
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static inline u32 get_csb_clk(immap_t *im)
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{
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u8 spmf;
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spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
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return get_board_sys_clk() * spmf;
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}
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/**
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* spmr_field() - Read a specific SPMR field
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* @im: Pointer to the MPC83xx main register map in question
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* @mask: A bitmask that describes the bitfield to be read
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*
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* Return: The value of the bit field as a 32-bit number.
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*/
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static inline uint spmr_field(immap_t *im, u32 mask)
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{
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/* Extract shift from bitmask */
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uint shift = mask ? ffs(mask) - 1 : 0;
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return (get_spmr(im) & mask) >> shift;
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}
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/**
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* sccr_field() - Read a specific SCCR field
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* @im: Pointer to the MPC83xx main register map in question
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* @mask: A bitmask that describes the bitfield to be read
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*
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* Return: The value of the bit field as a 32-bit number.
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*/
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static inline uint sccr_field(immap_t *im, u32 mask)
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{
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/* Extract shift from bitmask */
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uint shift = mask ? ffs(mask) - 1 : 0;
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return (get_sccr(im) & mask) >> shift;
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}
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/**
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* lcrr_field() - Read a specific LCRR field
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* @im: Pointer to the MPC83xx main register map in question
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* @mask: A bitmask that describes the bitfield to be read
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*
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* Return: The value of the bit field as a 32-bit number.
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*/
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static inline uint lcrr_field(immap_t *im, u32 mask)
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{
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/* Extract shift from bitmask */
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uint shift = mask ? ffs(mask) - 1 : 0;
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return (get_lcrr(im) & mask) >> shift;
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}
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