652d8d4561
Add a flag to set ahb/apb/fiu/spi clock divider as read-only The spi clock setting is related to booting flash, it is setup by early bootloader. It just protects the clock source and can't modify it in uboot. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231114090004.3746024-1-JJLIU0@nuvoton.com
99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*/
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#include <dm.h>
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#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
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#include "clk_npcm.h"
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/* Parent clock map */
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static const struct parent_data pll_parents[] = {
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{NPCM8XX_CLK_PLL0, 0},
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{NPCM8XX_CLK_PLL1, 1},
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{NPCM8XX_CLK_REFCLK, 2},
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{NPCM8XX_CLK_PLL2DIV2, 3}
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};
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static const struct parent_data cpuck_parents[] = {
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{NPCM8XX_CLK_PLL0, 0},
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{NPCM8XX_CLK_PLL1, 1},
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{NPCM8XX_CLK_REFCLK, 2},
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{NPCM8XX_CLK_PLL2, 7}
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};
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static const struct parent_data apb_parent[] = {{NPCM8XX_CLK_AHB, 0}};
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static struct npcm_clk_pll npcm8xx_clk_plls[] = {
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{NPCM8XX_CLK_PLL0, NPCM8XX_CLK_REFCLK, PLLCON0, 0},
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{NPCM8XX_CLK_PLL1, NPCM8XX_CLK_REFCLK, PLLCON1, 0},
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{NPCM8XX_CLK_PLL2, NPCM8XX_CLK_REFCLK, PLLCON2, 0},
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{NPCM8XX_CLK_PLL2DIV2, NPCM8XX_CLK_REFCLK, PLLCON2, POST_DIV2}
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};
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static struct npcm_clk_select npcm8xx_clk_selectors[] = {
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{NPCM8XX_CLK_AHB, cpuck_parents, CLKSEL, NPCM8XX_CPUCKSEL, 4, 0},
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{NPCM8XX_CLK_APB2, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM8XX_CLK_APB5, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM8XX_CLK_SPI0, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM8XX_CLK_SPI1, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM8XX_CLK_SPI3, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM8XX_CLK_SPIX, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM8XX_CLK_UART, pll_parents, CLKSEL, UARTCKSEL, 4, 0},
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{NPCM8XX_CLK_UART2, pll_parents, CLKSEL, UARTCKSEL, 4, 0},
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{NPCM8XX_CLK_SDHC, pll_parents, CLKSEL, SDCKSEL, 4, 0}
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};
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static struct npcm_clk_div npcm8xx_clk_dividers[] = {
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{NPCM8XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2 | DIV_RO},
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{NPCM8XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2 | DIV_RO},
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{NPCM8XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2 | DIV_RO},
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{NPCM8XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1 | DIV_RO},
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{NPCM8XX_CLK_SPI1, CLKDIV3, SPI1CKDIV, DIV_TYPE1 | DIV_RO},
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{NPCM8XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1 | DIV_RO},
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{NPCM8XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
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{NPCM8XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
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{NPCM8XX_CLK_UART2, CLKDIV3, UARTDIV2, DIV_TYPE1},
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{NPCM8XX_CLK_SDHC, CLKDIV1, MMCCKDIV, DIV_TYPE1}
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};
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static struct npcm_clk_data npcm8xx_clk_data = {
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.clk_plls = npcm8xx_clk_plls,
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.num_plls = ARRAY_SIZE(npcm8xx_clk_plls),
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.clk_selectors = npcm8xx_clk_selectors,
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.num_selectors = ARRAY_SIZE(npcm8xx_clk_selectors),
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.clk_dividers = npcm8xx_clk_dividers,
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.num_dividers = ARRAY_SIZE(npcm8xx_clk_dividers),
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.refclk_id = NPCM8XX_CLK_REFCLK,
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.pll0_id = NPCM8XX_CLK_PLL0,
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};
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static int npcm8xx_clk_probe(struct udevice *dev)
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{
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struct npcm_clk_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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priv->clk_data = &npcm8xx_clk_data;
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priv->num_clks = NPCM8XX_NUM_CLOCKS;
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return 0;
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}
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static const struct udevice_id npcm8xx_clk_ids[] = {
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{ .compatible = "nuvoton,npcm845-clk" },
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{ }
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};
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U_BOOT_DRIVER(clk_npcm) = {
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.name = "clk_npcm",
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.id = UCLASS_CLK,
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.of_match = npcm8xx_clk_ids,
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.ops = &npcm_clk_ops,
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.priv_auto = sizeof(struct npcm_clk_priv),
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.probe = npcm8xx_clk_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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