1918ff5c95
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family.
* static data describing the clocks and resets which are specific to the
R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
is used to indicate that both SoCs are supported.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
320 lines
8.4 KiB
C
320 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* RZ/G2L Clock Pulse Generator
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*
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* Copyright (C) 2021-2023 Renesas Electronics Corp.
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*
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*/
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#ifndef __RENESAS_RZG2L_CPG_H__
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#define __RENESAS_RZG2L_CPG_H__
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#define CPG_SIPLL5_STBY 0x140
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#define CPG_SIPLL5_CLK1 0x144
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#define CPG_SIPLL5_CLK3 0x14C
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#define CPG_SIPLL5_CLK4 0x150
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#define CPG_SIPLL5_CLK5 0x154
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#define CPG_SIPLL5_MON 0x15C
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#define CPG_PL1_DDIV 0x200
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#define CPG_PL2_DDIV 0x204
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#define CPG_PL3A_DDIV 0x208
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#define CPG_PL6_DDIV 0x210
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#define CPG_PL2SDHI_DSEL 0x218
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#define CPG_CLKSTATUS 0x280
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#define CPG_PL3_SSEL 0x408
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#define CPG_PL6_SSEL 0x414
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#define CPG_PL6_ETH_SSEL 0x418
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#define CPG_PL5_SDIV 0x420
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#define CPG_RST_MON 0x680
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#define CPG_OTHERFUNC1_REG 0xBE8
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#define CPG_SIPLL5_STBY_RESETB BIT(0)
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#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16)
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#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18)
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#define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20)
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#define CPG_SIPLL5_CLK4_RESV_LSB 0xFF
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#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4)
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#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16)
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#define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16)
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#define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24)
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#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
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#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
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#define CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US 20000
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/* n = 0/1/2 for PLL1/4/6 */
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#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * (n)))
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#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * (n)))
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#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
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#define DDIV_PACK(offset, bitpos, size) \
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(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
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#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
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#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
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#define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2)
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#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
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#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
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#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
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#define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2)
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#define SEL_PLL_PACK(offset, bitpos, size) \
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(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
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#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
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#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)
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#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
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#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
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#define SEL_SDHI0 DDIV_PACK(CPG_PL2SDHI_DSEL, 0, 2)
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#define SEL_SDHI1 DDIV_PACK(CPG_PL2SDHI_DSEL, 4, 2)
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#define SEL_SDHI_533MHz 1
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#define SEL_SDHI_400MHz 2
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#define SEL_SDHI_266MHz 3
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#define SEL_SDHI_WRITE_ENABLE 0x10000
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/* Unpack CPG conf value create by DDIV_PACK() or SEL_PLL_PACK(). */
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#define CPG_CONF_OFFSET(x) ((x) >> 20)
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#define CPG_CONF_BITPOS(x) (((x) >> 12) & 0xff)
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#define CPG_CONF_SIZE(x) (((x) >> 8) & 0xf)
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#define CPG_CONF_BITMASK(x) GENMASK(CPG_CONF_SIZE(x) - 1, 0)
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#define EXTAL_FREQ_IN_MEGA_HZ 24
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/**
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* Definitions of CPG Core Clocks
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*
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* These include:
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* - Clock outputs exported to DT
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* - External input clocks
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* - Internal CPG clocks
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*/
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struct cpg_core_clk {
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const char *name;
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unsigned int id;
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unsigned int parent;
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unsigned int div;
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unsigned int mult;
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unsigned int type;
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unsigned int conf;
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const struct clk_div_table *dtable;
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const char * const *parent_names;
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int flag;
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int mux_flags;
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int num_parents;
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};
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enum clk_types {
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/* Generic */
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CLK_TYPE_IN, /* External Clock Input */
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CLK_TYPE_FF, /* Fixed Factor Clock */
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CLK_TYPE_SAM_PLL,
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/* Clock with divider */
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CLK_TYPE_DIV,
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/* Clock with clock source selector */
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CLK_TYPE_MUX,
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/* Clock with SD clock source selector */
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CLK_TYPE_SD_MUX,
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/* Clock for SIPLL5 */
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CLK_TYPE_SIPLL5,
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/* Clock for PLL5_4 clock source selector */
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CLK_TYPE_PLL5_4_MUX,
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/* Clock for DSI divider */
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CLK_TYPE_DSI_DIV,
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};
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#define DEF_TYPE(_name, _id, _type...) \
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{ .name = _name, .id = _id, .type = _type }
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#define DEF_BASE(_name, _id, _type, _parent...) \
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DEF_TYPE(_name, _id, _type, .parent = _parent)
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#define DEF_SAMPLL(_name, _id, _parent, _conf) \
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DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
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#define DEF_INPUT(_name, _id) \
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DEF_TYPE(_name, _id, CLK_TYPE_IN)
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#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
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DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
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.parent = _parent, .dtable = _dtable, \
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.flag = CLK_DIVIDER_HIWORD_MASK)
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#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
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DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
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.parent = _parent, .dtable = _dtable, \
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.flag = CLK_DIVIDER_READ_ONLY)
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#define DEF_MUX(_name, _id, _conf, _parent_names) \
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DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names), \
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.mux_flags = CLK_MUX_HIWORD_MASK)
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#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
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DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names), \
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.mux_flags = CLK_MUX_READ_ONLY)
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#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \
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DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names))
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#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
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DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
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#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \
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DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
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.parent_names = _parent_names, \
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.num_parents = ARRAY_SIZE(_parent_names))
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#define DEF_DSI_DIV(_name, _id, _parent, _flag) \
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DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
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/**
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* struct rzg2l_mod_clk - Module Clocks definitions
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*
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* @name: handle between common and hardware-specific interfaces
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* @id: clock index in array containing all Core and Module Clocks
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* @parent: id of parent clock
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* @off: register offset
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* @bit: ON/MON bit
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* @is_coupled: flag to indicate coupled clock
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*/
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struct rzg2l_mod_clk {
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const char *name;
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unsigned int id;
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unsigned int parent;
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u16 off;
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u8 bit;
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bool is_coupled;
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};
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#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \
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{ \
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.name = (_name), \
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.id = (_id), \
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.parent = (_parent), \
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.off = (_off), \
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.bit = (_bit), \
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.is_coupled = (_is_coupled), \
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}
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#define DEF_MOD(_name, _id, _parent, _off, _bit) \
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DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
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#define DEF_COUPLED(_name, _id, _parent, _off, _bit) \
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DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
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/**
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* struct rzg2l_reset - Reset definitions
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*
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* @off: register offset
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* @bit: reset bit
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* @monbit: monitor bit in CPG_RST_MON register, -1 if none
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*/
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struct rzg2l_reset {
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u16 off;
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u8 bit;
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s8 monbit;
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};
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#define DEF_RST_MON(_id, _off, _bit, _monbit) \
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[_id] = { \
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.off = (_off), \
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.bit = (_bit), \
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.monbit = (_monbit) \
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}
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#define DEF_RST(_id, _off, _bit) \
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DEF_RST_MON(_id, _off, _bit, -1)
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/**
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* struct rzg2l_cpg_info - SoC-specific CPG Description
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*
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* @core_clks: Array of Core Clock definitions
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* @num_core_clks: Number of entries in core_clks[]
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*
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* @mod_clks: Array of Module Clock definitions
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* @num_mod_clks: Number of entries in mod_clks[]
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* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
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*
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* @resets: Array of Module Reset definitions
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* @num_resets: Number of entries in resets[]
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*
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* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
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*/
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struct rzg2l_cpg_info {
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/* Core Clocks */
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const struct cpg_core_clk *core_clks;
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unsigned int num_core_clks;
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/* Module Clocks */
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const struct rzg2l_mod_clk *mod_clks;
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unsigned int num_mod_clks;
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unsigned int num_hw_mod_clks;
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/* Resets */
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const struct rzg2l_reset *resets;
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unsigned int num_resets;
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bool has_clk_mon_regs;
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};
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extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
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int rzg2l_cpg_bind(struct udevice *parent);
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/*
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* Clock IDs start at an offset to avoid overlapping with core & module clock
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* IDs defined in the dt-bindings headers.
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*/
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enum clk_ids {
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/* External Input Clocks */
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CLK_EXTAL = 0x100,
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/* Internal Core Clocks */
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CLK_OSC_DIV1000 = 0x200,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV2_8,
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CLK_PLL2_DIV2_10,
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CLK_PLL3,
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CLK_PLL3_400,
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CLK_PLL3_533,
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CLK_M2_DIV2,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_4_2,
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CLK_SEL_PLL3_3,
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CLK_DIV_PLL3_C,
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CLK_PLL4,
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CLK_PLL5,
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CLK_PLL5_FOUTPOSTDIV,
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CLK_PLL5_FOUT1PH0,
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CLK_PLL5_FOUT3,
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CLK_PLL5_250,
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CLK_PLL6,
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CLK_PLL6_250,
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CLK_P1_DIV2,
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CLK_PLL2_800,
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CLK_PLL2_SDHI_533,
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CLK_PLL2_SDHI_400,
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CLK_PLL2_SDHI_266,
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CLK_SD0_DIV4,
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CLK_SD1_DIV4,
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CLK_SEL_GPU2,
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CLK_SEL_PLL5_4,
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CLK_DSI_DIV,
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CLK_PLL2_533,
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CLK_PLL2_533_DIV2,
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CLK_DIV_DSI_LPCLK,
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};
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#endif
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