46fa23f9ee
Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
37 lines
1.0 KiB
C
37 lines
1.0 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) Samuel Holland <samuel@sholland.org>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/reset/sun8i-r-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate a31_r_gates[] = {
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[CLK_APB0_PIO] = GATE(0x028, BIT(0)),
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[CLK_APB0_IR] = GATE(0x028, BIT(1)),
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[CLK_APB0_TIMER] = GATE(0x028, BIT(2)),
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[CLK_APB0_RSB] = GATE(0x028, BIT(3)),
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[CLK_APB0_UART] = GATE(0x028, BIT(4)),
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[CLK_APB0_I2C] = GATE(0x028, BIT(6)),
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[CLK_APB0_TWD] = GATE(0x028, BIT(7)),
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};
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static struct ccu_reset a31_r_resets[] = {
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[RST_APB0_IR] = RESET(0x0b0, BIT(1)),
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[RST_APB0_TIMER] = RESET(0x0b0, BIT(2)),
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[RST_APB0_RSB] = RESET(0x0b0, BIT(3)),
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[RST_APB0_UART] = RESET(0x0b0, BIT(4)),
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[RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
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};
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const struct ccu_desc a31_r_ccu_desc = {
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.gates = a31_r_gates,
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.resets = a31_r_resets,
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.num_gates = ARRAY_SIZE(a31_r_gates),
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.num_resets = ARRAY_SIZE(a31_r_resets),
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};
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