46fa23f9ee
Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) Samuel Holland <samuel@sholland.org>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate h6_r_gates[] = {
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[CLK_R_APB1] = GATE_DUMMY,
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[CLK_R_APB1_TIMER] = GATE(0x11c, BIT(0)),
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[CLK_R_APB1_TWD] = GATE(0x12c, BIT(0)),
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[CLK_R_APB1_PWM] = GATE(0x13c, BIT(0)),
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[CLK_R_APB2_UART] = GATE(0x18c, BIT(0)),
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[CLK_R_APB2_I2C] = GATE(0x19c, BIT(0)),
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[CLK_R_APB2_RSB] = GATE(0x1bc, BIT(0)),
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[CLK_R_APB1_IR] = GATE(0x1cc, BIT(0)),
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[CLK_R_APB1_W1] = GATE(0x1ec, BIT(0)),
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};
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static struct ccu_reset h6_r_resets[] = {
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[RST_R_APB1_TIMER] = RESET(0x11c, BIT(16)),
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[RST_R_APB1_TWD] = RESET(0x12c, BIT(16)),
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[RST_R_APB1_PWM] = RESET(0x13c, BIT(16)),
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[RST_R_APB2_UART] = RESET(0x18c, BIT(16)),
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[RST_R_APB2_I2C] = RESET(0x19c, BIT(16)),
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[RST_R_APB2_RSB] = RESET(0x1bc, BIT(16)),
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[RST_R_APB1_IR] = RESET(0x1cc, BIT(16)),
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[RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
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};
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const struct ccu_desc h6_r_ccu_desc = {
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.gates = h6_r_gates,
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.resets = h6_r_resets,
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.num_gates = ARRAY_SIZE(h6_r_gates),
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.num_resets = ARRAY_SIZE(h6_r_resets),
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};
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