756d64e43e
The digital phase-locked loop (DPLL) provides all interface clocks and functional clocks to the processor of the AM33xx device. The AM33xx device integrates five different DPLLs: * Core DPLL * Per DPLL * LCD DPLL * DDR DPLL * MPU DPLL The patch adds support for the compatible strings: * "ti,am3-dpll-core-clock" * "ti,am3-dpll-no-gate-clock" * "ti,am3-dpll-no-gate-j-type-clock" * "ti,am3-dpll-x2-clock" The code is loosely based on the drivers/clk/ti/dpll.c drivers of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/dpll.txt Signed-off-by: Dario Binacchi <dariobin@libero.it>
80 lines
1.7 KiB
C
80 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI DPLL x2 clock support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* Loosely based on Linux kernel drivers/clk/ti/dpll.c
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/clk-provider.h>
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struct clk_ti_am3_dpll_x2_priv {
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struct clk parent;
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};
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static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)
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{
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struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev);
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unsigned long rate;
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rate = clk_get_rate(&priv->parent);
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if (IS_ERR_VALUE(rate))
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return rate;
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rate *= 2;
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dev_dbg(clk->dev, "rate=%ld\n", rate);
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return rate;
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}
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const struct clk_ops clk_ti_am3_dpll_x2_ops = {
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.get_rate = clk_ti_am3_dpll_x2_get_rate,
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};
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static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_release_all(&priv->parent, 1);
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if (err) {
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dev_err(dev, "failed to release parent clock\n");
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return err;
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}
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return 0;
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}
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static int clk_ti_am3_dpll_x2_probe(struct udevice *dev)
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{
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struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
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int err;
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err = clk_get_by_index(dev, 0, &priv->parent);
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if (err) {
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dev_err(dev, "%s: failed to get parent clock\n", __func__);
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return err;
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}
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return 0;
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}
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static const struct udevice_id clk_ti_am3_dpll_x2_of_match[] = {
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{.compatible = "ti,am3-dpll-x2-clock"},
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{}
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};
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U_BOOT_DRIVER(clk_ti_am3_dpll_x2) = {
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.name = "ti_am3_dpll_x2_clock",
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.id = UCLASS_CLK,
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.of_match = clk_ti_am3_dpll_x2_of_match,
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.probe = clk_ti_am3_dpll_x2_probe,
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.remove = clk_ti_am3_dpll_x2_remove,
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.priv_auto = sizeof(struct clk_ti_am3_dpll_x2_priv),
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.ops = &clk_ti_am3_dpll_x2_ops,
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};
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