2c0bdcacf3
The fttmr010 timer driver was deleted by
commit 29fc6f2492 ("ARM: remove a320evb board support")
The original source file was: arch/arm/cpu/arm920t/a320/timer.c
Return the driver to the codebase in a DM compatible form.
A platform using fttmr010 will be submitted later.
This hardware is described in the datasheet [1], starting from page 348.
According to the datasheet, there is a Revision Register at offset 0x3C,
which is not present in 'struct fttmr010'. Add it and debug() print
revision in probe function.
[1]
https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf
Signed-off-by: Sergei Antonov <saproj@gmail.com>
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* 23/08/2022 Port to DM
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <dm/ofnode.h>
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#include <faraday/fttmr010.h>
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#include <asm/global_data.h>
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#define TIMER_LOAD_VAL 0xffffffff
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struct fttmr010_timer_priv {
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struct fttmr010 __iomem *regs;
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};
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static u64 fttmr010_timer_get_count(struct udevice *dev)
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{
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struct fttmr010_timer_priv *priv = dev_get_priv(dev);
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struct fttmr010 *tmr = priv->regs;
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u32 now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
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/* increment tbu if tbl has rolled over */
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if (now < gd->arch.tbl)
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gd->arch.tbu++;
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gd->arch.tbl = now;
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return ((u64)gd->arch.tbu << 32) | gd->arch.tbl;
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}
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static int fttmr010_timer_probe(struct udevice *dev)
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{
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struct fttmr010_timer_priv *priv = dev_get_priv(dev);
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struct fttmr010 *tmr;
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unsigned int cr;
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priv->regs = dev_read_addr_ptr(dev);
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if (!priv->regs)
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return -EINVAL;
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tmr = priv->regs;
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debug("Faraday FTTMR010 timer revision 0x%08X\n", readl(&tmr->revision));
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/* disable timers */
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writel(0, &tmr->cr);
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/* setup timer */
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writel(TIMER_LOAD_VAL, &tmr->timer3_load);
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writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
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writel(0, &tmr->timer3_match1);
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writel(0, &tmr->timer3_match2);
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/* we don't want timer to issue interrupts */
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writel(FTTMR010_TM3_MATCH1 |
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FTTMR010_TM3_MATCH2 |
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FTTMR010_TM3_OVERFLOW,
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&tmr->interrupt_mask);
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cr = readl(&tmr->cr);
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cr |= FTTMR010_TM3_CLOCK; /* use external clock */
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cr |= FTTMR010_TM3_ENABLE;
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writel(cr, &tmr->cr);
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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return 0;
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}
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static const struct timer_ops fttmr010_timer_ops = {
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.get_count = fttmr010_timer_get_count,
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};
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static const struct udevice_id fttmr010_timer_ids[] = {
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{ .compatible = "faraday,fttmr010-timer" },
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{}
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};
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U_BOOT_DRIVER(fttmr010_timer) = {
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.name = "fttmr010_timer",
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.id = UCLASS_TIMER,
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.of_match = fttmr010_timer_ids,
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.priv_auto = sizeof(struct fttmr010_timer_priv),
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.probe = fttmr010_timer_probe,
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.ops = &fttmr010_timer_ops,
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};
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