adf869045d
Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
131 lines
3.1 KiB
C
131 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/tegra.h>
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#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320)
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#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5)
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#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0)
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#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
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#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */
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/*
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* On pre-DM stage timer should be left configured by
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* previous bootloader for correct 1MHz clock.
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* In the case of reset default value is set to 1/13 of
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* CLK_M which should be decent enough to safely
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* get to DM stage.
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*/
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u64 notrace timer_early_get_count(void)
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{
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/* At this stage raw timer is used */
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return readl(TEGRA_TIMER_USEC_CNTR);
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}
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unsigned long notrace timer_early_get_rate(void)
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{
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return TEGRA_TIMER_RATE;
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}
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ulong timer_get_boot_us(void)
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{
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return timer_early_get_count();
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}
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/*
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* At moment of calling get_count, timer driver is already
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* probed and is configured to have precise 1MHz clock.
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* Tegra timer has a step of 1 microsecond which removes
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* need of using adjusments involving uc_priv->clock_rate.
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*/
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static notrace u64 tegra_timer_get_count(struct udevice *dev)
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{
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u32 val = timer_early_get_count();
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return timer_conv_64(val);
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}
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static int tegra_timer_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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u32 usec_config, value;
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/* Timer rate has to be set unconditionally */
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uc_priv->clock_rate = TEGRA_TIMER_RATE;
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/*
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* Configure microsecond timers to have 1MHz clock
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* Config register is 0xqqww, where qq is "dividend", ww is "divisor"
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* Uses n+1 scheme
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*/
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switch (clock_get_rate(CLOCK_ID_CLK_M)) {
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case 12000000:
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usec_config = 0x000b; /* (11+1)/(0+1) */
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break;
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case 12800000:
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usec_config = 0x043f; /* (63+1)/(4+1) */
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break;
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case 13000000:
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usec_config = 0x000c; /* (12+1)/(0+1) */
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break;
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case 16800000:
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usec_config = 0x0453; /* (83+1)/(4+1) */
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break;
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case 19200000:
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usec_config = 0x045f; /* (95+1)/(4+1) */
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break;
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case 26000000:
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usec_config = 0x0019; /* (25+1)/(0+1) */
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break;
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case 38400000:
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usec_config = 0x04bf; /* (191+1)/(4+1) */
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break;
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case 48000000:
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usec_config = 0x002f; /* (47+1)/(0+1) */
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break;
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default:
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return -EINVAL;
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}
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/* Enable clock to timer hardware */
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value = readl_relaxed(TEGRA_OSC_CLK_ENB_L_SET);
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writel_relaxed(value | TEGRA_OSC_SET_CLK_ENB_TMR,
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TEGRA_OSC_CLK_ENB_L_SET);
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writel_relaxed(usec_config, TEGRA_TIMER_USEC_CFG);
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return 0;
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}
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static const struct timer_ops tegra_timer_ops = {
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.get_count = tegra_timer_get_count,
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};
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static const struct udevice_id tegra_timer_ids[] = {
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{ .compatible = "nvidia,tegra20-timer" },
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{ .compatible = "nvidia,tegra30-timer" },
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{ .compatible = "nvidia,tegra114-timer" },
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{ .compatible = "nvidia,tegra124-timer" },
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{ .compatible = "nvidia,tegra210-timer" },
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{ }
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};
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U_BOOT_DRIVER(tegra_timer) = {
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.name = "tegra_timer",
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.id = UCLASS_TIMER,
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.of_match = tegra_timer_ids,
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.probe = tegra_timer_probe,
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.ops = &tegra_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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