b34bc22bd9
Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.
Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().
Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20221012053656.1492457-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
83 lines
2.1 KiB
C
83 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022 Advanced Micro Devices, Inc
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* Michal Simek <michal.simek@amd.com>
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*
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* (C) Copyright 2007 Michal Simek
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* Michal SIMEK <monstr@monstr.eu>
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*/
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#include <common.h>
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#include <dm.h>
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#include <timer.h>
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#include <regmap.h>
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#include <dm/device_compat.h>
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#define TIMER_ENABLE_ALL 0x400 /* ENALL */
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#define TIMER_PWM 0x200 /* PWMA0 */
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#define TIMER_INTERRUPT 0x100 /* T0INT */
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#define TIMER_ENABLE 0x080 /* ENT0 */
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#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */
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#define TIMER_RESET 0x020 /* LOAD0 */
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#define TIMER_RELOAD 0x010 /* ARHT0 */
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#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */
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#define TIMER_EXT_COMPARE 0x004 /* GENT0 */
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#define TIMER_DOWN_COUNT 0x002 /* UDT0 */
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#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */
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#define TIMER_CONTROL_OFFSET 0
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#define TIMER_LOADREG_OFFSET 4
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#define TIMER_COUNTER_OFFSET 8
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struct xilinx_timer_priv {
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struct regmap *regs;
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};
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static u64 xilinx_timer_get_count(struct udevice *dev)
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{
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struct xilinx_timer_priv *priv = dev_get_priv(dev);
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u32 value;
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regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
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return timer_conv_64(value);
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}
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static int xilinx_timer_probe(struct udevice *dev)
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{
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struct xilinx_timer_priv *priv = dev_get_priv(dev);
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int ret;
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/* uc_priv->clock_rate has already clock rate */
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regs);
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if (ret) {
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dev_dbg(dev, "failed to get regbase of timer\n");
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return ret;
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}
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regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0);
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regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET);
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regmap_write(priv->regs, TIMER_CONTROL_OFFSET,
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TIMER_ENABLE | TIMER_RELOAD);
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return 0;
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}
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static const struct timer_ops xilinx_timer_ops = {
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.get_count = xilinx_timer_get_count,
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};
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static const struct udevice_id xilinx_timer_ids[] = {
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{ .compatible = "xlnx,xps-timer-1.00.a" },
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{}
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};
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U_BOOT_DRIVER(xilinx_timer) = {
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.name = "xilinx_timer",
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.id = UCLASS_TIMER,
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.of_match = xilinx_timer_ids,
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.priv_auto = sizeof(struct xilinx_timer_priv),
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.probe = xilinx_timer_probe,
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.ops = &xilinx_timer_ops,
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};
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