18370f1497
Similar change was done by commit b4c2c151b1 ("Kconfig: Remove all
default n/no options") and again sync is required.
default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
526 lines
14 KiB
Plaintext
526 lines
14 KiB
Plaintext
menu "RISC-V architecture"
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depends on RISCV
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config SYS_ARCH
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default "riscv"
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choice
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prompt "Target select"
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optional
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config TARGET_ANDES_AE350
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bool "Support Andes ae350"
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config TARGET_MICROCHIP_ICICLE
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bool "Support Microchip PolarFire-SoC Icicle Board"
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config TARGET_QEMU_VIRT
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bool "Support QEMU Virt Board"
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config TARGET_SIFIVE_UNLEASHED
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bool "Support SiFive Unleashed Board"
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config TARGET_SIFIVE_UNMATCHED
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bool "Support SiFive Unmatched Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_STARFIVE_VISIONFIVE2
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bool "Support StarFive VisionFive2 Board"
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select BOARD_LATE_INIT
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config TARGET_TH1520_LPI4A
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bool "Support Sipeed's TH1520 Lichee PI 4A Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_SIPEED_MAIX
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bool "Support Sipeed Maix Board"
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select SYS_CACHE_SHIFT_6
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config TARGET_OPENPITON_RISCV64
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bool "Support RISC-V cores on OpenPiton SoC"
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endchoice
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config SYS_ICACHE_OFF
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bool "Do not enable icache"
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help
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Do not enable instruction cache in U-Boot.
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config SPL_SYS_ICACHE_OFF
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bool "Do not enable icache in SPL"
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depends on SPL
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default SYS_ICACHE_OFF
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help
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Do not enable instruction cache in SPL.
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config SYS_DCACHE_OFF
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bool "Do not enable dcache"
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help
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Do not enable data cache in U-Boot.
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config SPL_SYS_DCACHE_OFF
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bool "Do not enable dcache in SPL"
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depends on SPL
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default SYS_DCACHE_OFF
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help
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Do not enable data cache in SPL.
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config SPL_ZERO_MEM_BEFORE_USE
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bool "Zero memory before use"
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depends on SPL
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help
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Zero stack/GD/malloc area in SPL before using them, this is needed for
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Sifive core devices that uses L2 cache to store SPL.
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# board-specific options below
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source "board/AndesTech/ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/microchip/mpfs_icicle/Kconfig"
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source "board/sifive/unleashed/Kconfig"
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source "board/sifive/unmatched/Kconfig"
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source "board/thead/th1520_lpi4a/Kconfig"
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source "board/openpiton/riscv64/Kconfig"
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source "board/sipeed/maix/Kconfig"
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source "board/starfive/visionfive2/Kconfig"
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# platform-specific options below
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source "arch/riscv/cpu/andesv5/Kconfig"
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source "arch/riscv/cpu/fu540/Kconfig"
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source "arch/riscv/cpu/fu740/Kconfig"
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source "arch/riscv/cpu/generic/Kconfig"
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source "arch/riscv/cpu/jh7110/Kconfig"
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# architecture-specific options below
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choice
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prompt "Base ISA"
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default ARCH_RV32I
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config ARCH_RV32I
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bool "RV32I"
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select 32BIT
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help
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Choose this option to target the RV32I base integer instruction set.
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config ARCH_RV64I
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bool "RV64I"
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select 64BIT
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select PHYS_64BIT
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help
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Choose this option to target the RV64I base integer instruction set.
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endchoice
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choice
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prompt "Code Model"
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default CMODEL_MEDLOW
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config CMODEL_MEDLOW
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bool "medium low code model"
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help
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U-Boot and its statically defined symbols must lie within a single 2 GiB
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address range and must lie between absolute addresses -2 GiB and +2 GiB.
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config CMODEL_MEDANY
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bool "medium any code model"
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help
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U-Boot and its statically defined symbols must be within any single 2 GiB
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address range.
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endchoice
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choice
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prompt "Run Mode"
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default RISCV_MMODE
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config RISCV_MMODE
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bool "Machine"
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help
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Choose this option to build U-Boot for RISC-V M-Mode.
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config RISCV_SMODE
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bool "Supervisor"
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imply DEBUG_UART
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help
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Choose this option to build U-Boot for RISC-V S-Mode.
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endchoice
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choice
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prompt "SPL Run Mode"
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default SPL_RISCV_MMODE
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depends on SPL
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config SPL_RISCV_MMODE
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bool "Machine"
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help
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Choose this option to build U-Boot SPL for RISC-V M-Mode.
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config SPL_RISCV_SMODE
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bool "Supervisor"
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help
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Choose this option to build U-Boot SPL for RISC-V S-Mode.
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endchoice
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config RISCV_ISA_C
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bool "Emit compressed instructions"
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default y
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help
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Adds "C" to the ISA subsets that the toolchain is allowed to emit
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when building U-Boot, which results in compressed instructions in the
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U-Boot binary.
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config RISCV_ISA_F
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bool "Standard extension for Single-Precision Floating Point"
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default y
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help
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Adds "F" to the ISA string passed to the compiler.
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config RISCV_ISA_D
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bool "Standard extension for Double-Precision Floating Point"
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depends on RISCV_ISA_F
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default y
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help
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Adds "D" to the ISA string passed to the compiler and changes the
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riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to
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lp64d.
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config RISCV_ISA_ZBB
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bool "Zbb extension support for bit manipulation instructions"
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help
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Adds ZBB extension (basic bit manipulation) to the ISA subsets
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that the toolchain is allowed to emit when building U-Boot.
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The Zbb extension provides instructions to accelerate a number
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of bit-specific operations (count bit population, sign extending,
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bitrotation, etc) and enables optimized string routines.
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menu "Use assembly optimized implementation of string routines"
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config USE_ARCH_STRLEN
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bool "Use an assembly optimized implementation of strlen"
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default y
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depends on RISCV_ISA_ZBB
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help
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Enable the generation of an optimized version of strlen using
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Zbb extension.
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config SPL_USE_ARCH_STRLEN
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bool "Use an assembly optimized implementation of strlen for SPL"
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default y if USE_ARCH_STRLEN
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depends on RISCV_ISA_ZBB
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depends on SPL
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help
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Enable the generation of an optimized version of strlen using
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Zbb extension.
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config TPL_USE_ARCH_STRLEN
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bool "Use an assembly optimized implementation of strlen for TPL"
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default y if USE_ARCH_STRLEN
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depends on RISCV_ISA_ZBB
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depends on TPL
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help
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Enable the generation of an optimized version of strlen using
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Zbb extension.
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config USE_ARCH_STRCMP
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bool "Use an assembly optimized implementation of strcmp"
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default y
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depends on RISCV_ISA_ZBB
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help
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Enable the generation of an optimized version of strcmp using
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Zbb extension.
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config SPL_USE_ARCH_STRCMP
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bool "Use an assembly optimized implementation of strcmp for SPL"
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default y if USE_ARCH_STRCMP
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depends on RISCV_ISA_ZBB
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depends on SPL
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help
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Enable the generation of an optimized version of strcmp using
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Zbb extension.
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config TPL_USE_ARCH_STRCMP
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bool "Use an assembly optimized implementation of strcmp for TPL"
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default y if USE_ARCH_STRCMP
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depends on RISCV_ISA_ZBB
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depends on TPL
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help
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Enable the generation of an optimized version of strcmp using
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Zbb extension.
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config USE_ARCH_STRNCMP
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bool "Use an assembly optimized implementation of strncmp"
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default y
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depends on RISCV_ISA_ZBB
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help
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Enable the generation of an optimized version of strncmp using
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Zbb extension.
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config SPL_USE_ARCH_STRNCMP
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bool "Use an assembly optimized implementation of strncmp for SPL"
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default y if USE_ARCH_STRNCMP
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depends on RISCV_ISA_ZBB
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depends on SPL
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help
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Enable the generation of an optimized version of strncmp using
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Zbb extension.
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config TPL_USE_ARCH_STRNCMP
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bool "Use an assembly optimized implementation of strncmp for TPL"
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default y if USE_ARCH_STRNCMP
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depends on RISCV_ISA_ZBB
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depends on TPL
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help
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Enable the generation of an optimized version of strncmp using
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Zbb extension.
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endmenu
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config RISCV_ISA_A
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def_bool y
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config 32BIT
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bool
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config 64BIT
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bool
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config DMA_ADDR_T_64BIT
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bool
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default y if 64BIT
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config RISCV_ACLINT
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bool
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depends on RISCV_MMODE
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select REGMAP
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select SYSCON
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help
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The RISC-V ACLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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config SPL_RISCV_ACLINT
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bool
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depends on SPL_RISCV_MMODE
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select SPL_REGMAP
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select SPL_SYSCON
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help
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The RISC-V ACLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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config SIFIVE_CACHE
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bool
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help
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This enables the operations to configure SiFive cache
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config ANDES_PLICSW
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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help
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The Andes PLICSW block holds memory-mapped claim and pending
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registers associated with software interrupt.
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config SMP
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bool "Symmetric Multi-Processing"
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depends on SBI_V01 || !RISCV_SMODE
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help
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This enables support for systems with more than one CPU. If
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you say N here, U-Boot will run on single and multiprocessor
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machines, but will use only one CPU of a multiprocessor
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machine. If you say Y here, U-Boot will run on many, but not
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all, single processor machines.
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config SPL_SMP
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bool "Symmetric Multi-Processing in SPL"
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depends on SPL && SPL_RISCV_MMODE
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default y
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help
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This enables support for systems with more than one CPU in SPL.
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If you say N here, U-Boot SPL will run on single and multiprocessor
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machines, but will use only one CPU of a multiprocessor
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machine. If you say Y here, U-Boot SPL will run on many, but not
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all, single processor machines.
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config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP || SPL_SMP
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default 8
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help
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On multiprocessor machines, U-Boot sets up a stack for each CPU.
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Stack memory is pre-allocated. U-Boot must therefore know the
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maximum number of CPUs that may be present.
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config SBI
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bool
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default y if RISCV_SMODE || SPL_RISCV_SMODE
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choice
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prompt "SBI support"
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default SBI_V02
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config SBI_V01
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bool "SBI v0.1 support"
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depends on SBI
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help
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This config allows kernel to use SBI v0.1 APIs. This will be
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deprecated in future once legacy M-mode software are no longer in use.
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config SBI_V02
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bool "SBI v0.2 or later support"
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depends on SBI
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help
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The SBI specification introduced the concept of extensions in version
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v0.2. With this configuration option U-Boot can detect and use SBI
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extensions. With the HSM extension introduced in SBI 0.2, only a
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single hart needs to boot and enter the operating system. The booting
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hart can bring up secondary harts one by one afterwards.
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Choose this option if OpenSBI release v0.7 or above is used together
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with U-Boot.
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endchoice
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config SBI_IPI
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bool
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depends on SBI
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default y if RISCV_SMODE || SPL_RISCV_SMODE
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depends on SMP
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config XIP
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bool "XIP mode"
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help
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XIP (eXecute In Place) is a method for executing code directly
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from a NOR flash memory without copying the code to ram.
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Say yes here if U-Boot boots from flash directly.
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config SPL_XIP
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bool "Enable XIP mode for SPL"
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help
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If SPL starts in read-only memory (XIP for example) then we shouldn't
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rely on lock variables (for example hart_lottery and available_harts_lock),
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this affects only SPL, other stages should proceed as non-XIP.
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config AVAILABLE_HARTS
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bool "Send IPI by available harts"
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default y
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help
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By default, IPI sending mechanism will depend on available_harts.
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If disable this, it will send IPI by CPUs node numbers of device tree.
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config SHOW_REGS
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bool "Show registers on unhandled exception"
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config RISCV_PRIV_1_9
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bool "Use version 1.9 of the RISC-V priviledged specification"
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help
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Older versions of the RISC-V priviledged specification had
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separate counter enable CSRs for each privilege mode. Writing
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to the unified mcounteren CSR on a processor implementing the
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old specification will result in an illegal instruction
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exception. In addition to counter CSR changes, the way virtual
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memory is configured was also changed.
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config STACK_SIZE_SHIFT
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int
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default 14
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config OF_BOARD_FIXUP
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default y if OF_SEPARATE && RISCV_SMODE
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menu "Use assembly optimized implementation of memory routines"
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config USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy"
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default y
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy for SPL"
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default y if USE_ARCH_MEMCPY
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depends on SPL
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMCPY
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bool "Use an assembly optimized implementation of memcpy for TPL"
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default y if USE_ARCH_MEMCPY
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depends on TPL
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help
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Enable the generation of an optimized version of memcpy.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove"
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default y
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove for SPL"
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default y if USE_ARCH_MEMCPY
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depends on SPL
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMMOVE
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bool "Use an assembly optimized implementation of memmove for TPL"
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default y if USE_ARCH_MEMCPY
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depends on TPL
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help
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Enable the generation of an optimized version of memmove.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset"
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default y
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config SPL_USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset for SPL"
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default y if USE_ARCH_MEMSET
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depends on SPL
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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config TPL_USE_ARCH_MEMSET
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bool "Use an assembly optimized implementation of memset for TPL"
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default y if USE_ARCH_MEMSET
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depends on TPL
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help
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Enable the generation of an optimized version of memset.
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Such an implementation may be faster under some conditions
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but may increase the binary size.
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endmenu
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config SPL_LOAD_FIT_OPENSBI_OS_BOOT
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bool "Enable SPL (OpenSBI OS boot mode) applying linux from FIT"
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depends on SPL_LOAD_FIT
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help
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Use fw_dynamic from the FIT image, and u-boot SPL will invoke it directly.
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This is a shortcut boot flow, from u-boot SPL -> OpenSBI -> u-boot proper
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-> linux to u-boot SPL -> OpenSBI -> linux.
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endmenu
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