72 lines
1.8 KiB
YAML
72 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Functional Clock Controller for MT8188
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maintainers:
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- Garmin Chang <garmin.chang@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices provide clock gate control in different IP blocks.
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properties:
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compatible:
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enum:
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- mediatek,mt8188-adsp-audio26m
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- mediatek,mt8188-camsys
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- mediatek,mt8188-camsys-rawa
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- mediatek,mt8188-camsys-rawb
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- mediatek,mt8188-camsys-yuva
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- mediatek,mt8188-camsys-yuvb
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- mediatek,mt8188-ccusys
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- mediatek,mt8188-imgsys
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- mediatek,mt8188-imgsys-wpe1
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- mediatek,mt8188-imgsys-wpe2
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- mediatek,mt8188-imgsys-wpe3
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- mediatek,mt8188-imgsys1-dip-nr
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- mediatek,mt8188-imgsys1-dip-top
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- mediatek,mt8188-imp-iic-wrap-c
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- mediatek,mt8188-imp-iic-wrap-en
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- mediatek,mt8188-imp-iic-wrap-w
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- mediatek,mt8188-ipesys
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- mediatek,mt8188-mfgcfg
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- mediatek,mt8188-vdecsys
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- mediatek,mt8188-vdecsys-soc
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- mediatek,mt8188-vencsys
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- mediatek,mt8188-vppsys0
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- mediatek,mt8188-vppsys1
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- mediatek,mt8188-wpesys
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- mediatek,mt8188-wpesys-vpp0
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@11283000 {
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compatible = "mediatek,mt8188-imp-iic-wrap-c";
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reg = <0x11283000 0x1000>;
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#clock-cells = <1>;
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};
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