499 lines
12 KiB
C
499 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2023 Yilin Sun <imi415@imi.moe>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/sizes.h>
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#define CVI_SPIF_BUS_WIDTH_1 0x00
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#define CVI_SPIF_BUS_WIDTH_2 0x01
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#define CVI_SPIF_BUS_WIDTH_4 0x02
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#define CVI_SPIF_FIFO_DEPTH 8U
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/**
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* SPIF SPI_CTRL register
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*
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*/
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#define CVI_SPIF_SPI_CTRL_SCK_DIV_SHIFT 0
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#define CVI_SPIF_SPI_CTRL_SCK_DIV_MASK GENMASK(10, 0) /* Clock divider, assume F/(x+1) */
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#define CVI_SPIF_SPI_CTRL_CPHA_SHIFT 12
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#define CVI_SPIF_SPI_CTRL_CPHA_MASK BIT(12) /* Clock phase */
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#define CVI_SPIF_SPI_CTRL_CPOL_SHIFT 13
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#define CVI_SPIF_SPI_CTRL_CPOL_MASK BIT(13) /* Clock polarity */
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#define CVI_SPIF_SPI_CTRL_HOLD_OL_MASK BIT(14) /* HOLD output low?*/
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#define CVI_SPIF_SPI_CTRL_WP_OL_MASK BIT(15) /* WP output low? */
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#define CVI_SPIF_SPI_CTRL_FRAME_LEN_MASK BIT(16) /* Frame length */
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#define CVI_SPIF_SPI_CTRL_LSB_FIRST_MASK BIT(20) /* LSB first SPI */
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#define CVI_SPIF_SPI_CTRL_SRST_MASK BIT(21) /* Software Reset? */
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/**
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* SPIF CE_CTRL register
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*
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*/
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#define CVI_SPIF_CE_CTRL_CEMANUAL_MASK BIT(0) /* Manual CE control value */
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#define CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK BIT(1) /* Manual CE control enable */
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/**
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* SPIF DLY_CTRL register
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*
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*/
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#define CVI_SPIF_DLY_CTRL_CET_MASK GENMASK(9, 8)
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#define CVI_SPIF_DLY_CTRL_NEG_SAMPLE_MASK BIT(14)
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/**
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* SPIF DMMR register
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*
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*/
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#define CVI_SPIF_DMMR_EN_MASK BIT(0) /* Direct memory-mapped mode enable */
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/**
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* SPIF TRANS_CSR register
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*
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*/
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#define CVI_SPIF_TRANS_CSR_MODE_SHIFT 0
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#define CVI_SPIF_TRANS_CSR_MODE_MASK GENMASK(1, 0) /* Mode, 01: Read, 10: Write */
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#define CVI_SPIF_TRANS_CSR_MODE(x) \
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((x << CVI_SPIF_TRANS_CSR_MODE_SHIFT) & CVI_SPIF_TRANS_CSR_MODE_MASK)
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#define CVI_SPIF_TRANS_CSR_CONT_READ_MASK BIT(2) /* Continous mode read? */
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#define CVI_SPIF_TRANS_CSR_FAST_MODE_MASK BIT(3) /* Fast mode (which)? */
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#define CVI_SPIF_TRANS_CSR_BUS_WIDTH_SHIFT 4
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#define CVI_SPIF_TRANS_CSR_BUS_WIDTH_MASK GENMASK(5, 4) /* Bus width, 2^x bits */
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#define CVI_SPIF_TRANS_CSR_BUS_WIDTH(x) \
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((x << CVI_SPIF_TRANS_CSR_BUS_WIDTH_SHIFT) & CVI_SPIF_TRANS_CSR_BUS_WIDTH_MASK)
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#define CVI_SPIF_TRANS_CSR_DMA_EN_MASK BIT(6) /* DMA request enable? */
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#define CVI_SPIF_TRANS_CSR_MISO_LVL_MASK BIT(7) /* Read MISO level? */
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#define CVI_SPIF_TRANS_CSR_ADDR_BYTES_MASK GENMASK(10, 8) /* Address bytes? */
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#define CVI_SPIF_TRANS_CSR_WITH_CMD_MASK BIT(11) /* ??? */
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#define CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_SHIFT 12
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#define CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_MASK GENMASK(13, 12) /* FIFO (IRQ?) trigger level, 2^x bytes */
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#define CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL(x) \
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((x << CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_SHIFT) & CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL_MASK)
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#define CVI_SPIF_TRANS_CSR_GO_BUSY_MASK BIT(15) /* Write 1 to GO? Self-cleared bit? */
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#define CVI_SPIF_TRANS_CSR_DUMMY_MASK GENMASK(19, 16) /* Dummy count? */
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#define CVI_SPIF_TRANS_CSR_4B_ADDR_MASK BIT(20) /* 4 bytes address */
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#define CVI_SPIF_TRANS_CSR_4B_CMD_MASK BIT(21) /* 4 bytes command */
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/**
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* SPIF INT_STS register
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*
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*/
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#define CVI_SPIF_INT_STS_TRANS_DONE_MASK BIT(0)
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#define CVI_SPIF_INT_STS_RD_FIFO_MASK BIT(2)
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/*
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* Note: All registers are mapped into the XIP space:
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* Read access:
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* - If DMMR_EN = 1: Memory contents
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* - If DMMR_EN = 0: Register contents
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* Write access: Register contents (DMMR_EN ignored)
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*
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*/
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struct cvitek_spif_regs {
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u32 spi_ctrl; /* Offset: 0x00 */
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u32 ce_ctrl; /* Offset: 0x04 */
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u32 dly_ctrl; /* Offset: 0x08 */
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u32 dmmr; /* Offset: 0x0C */
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u32 trans_csr; /* Offset: 0x10 */
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u32 trans_num; /* Offset: 0x14 */
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u32 ff_port; /* Offset: 0x18 */
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u32 reserved0; /* Offset: 0x1C */
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u32 ff_pt; /* Offset: 0x20 */
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u32 reserved1; /* Offset: 0x24 */
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u32 int_sts; /* Offset: 0x28 */
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u32 int_en; /* Offset: 0x2C */
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};
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struct cvitek_spif_xfer {
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u8 width; /* Bus width, 0: 1bit, 1: 2bits, 2: 4bits */
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union {
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u8 *in;
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const u8 *out;
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} data;
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u32 length; /* Length in bytes */
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};
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struct cvitek_spif_priv {
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struct cvitek_spif_regs *regs;
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u32 clk_rate;
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unsigned int cs;
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};
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static int cvitek_spif_claim_bus(struct udevice *dev)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(dev->parent);
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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priv->cs = slave_plat->cs;
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if(priv->cs > 0)
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return -ENODEV;
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clrbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK);
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dev_dbg(dev, "claim_bus cs: %d\n", priv->cs);
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return 0;
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}
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static int cvitek_spif_release_bus(struct udevice *dev)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(dev->parent);
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clrbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK);
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dev_dbg(dev, "release_bus cs: %d\n", priv->cs);
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return 0;
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}
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static int cvitek_spif_set_speed(struct udevice *bus, uint speed)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(bus);
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u8 div_val = DIV_ROUND_UP(priv->clk_rate, speed) - 1;
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u32 dly_ctrl = CVI_SPIF_DLY_CTRL_CET_MASK;
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clrsetbits_le32(&priv->regs->spi_ctrl,
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CVI_SPIF_SPI_CTRL_SCK_DIV_MASK,
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(div_val << CVI_SPIF_SPI_CTRL_SCK_DIV_SHIFT));
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if(speed > 30000000)
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dly_ctrl |= CVI_SPIF_DLY_CTRL_NEG_SAMPLE_MASK;
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writel(dly_ctrl, &priv->regs->dly_ctrl);
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dev_dbg(bus, "set_speed to %dHz, div: %d\n", speed, div_val);
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return 0;
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}
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static int cvitek_spif_set_mode(struct udevice *bus, uint mode)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(bus);
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u32 mode_mask = 0U;
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if(mode & SPI_CPHA)
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mode_mask |= CVI_SPIF_SPI_CTRL_CPHA_MASK;
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if(mode & SPI_CPOL)
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mode_mask |= CVI_SPIF_SPI_CTRL_CPOL_MASK;
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clrsetbits_le32(&priv->regs->spi_ctrl,
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(CVI_SPIF_SPI_CTRL_CPOL_MASK | CVI_SPIF_SPI_CTRL_CPHA_MASK),
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mode_mask);
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dev_dbg(bus, "set_mode to %d\n", mode);
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return 0;
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}
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static int cvitek_spif_read(struct cvitek_spif_priv *priv, struct cvitek_spif_xfer *xfer)
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{
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u32 trans_ctrl;
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u32 i;
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u8 width;
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switch(xfer->width)
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{
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case 1:
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width = CVI_SPIF_BUS_WIDTH_1;
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break;
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case 2:
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width = CVI_SPIF_BUS_WIDTH_2;
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break;
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case 4:
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width = CVI_SPIF_BUS_WIDTH_4;
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break;
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default:
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return -EINVAL;
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}
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trans_ctrl |= CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL(3);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_BUS_WIDTH(width);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_MODE(1); /* RX mode */
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/* Set up transfer mode */
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writel(trans_ctrl, &priv->regs->trans_csr);
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/* Write transfer length in bytes */
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writel(xfer->length, &priv->regs->trans_num);
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/* Reset FIFO pointer */
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writel(0U, &priv->regs->ff_pt);
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/* Start transfer */
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setbits_le32(&priv->regs->trans_csr, CVI_SPIF_TRANS_CSR_GO_BUSY_MASK);
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for(i = 0; i < xfer->length; i++)
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{
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/* Wait for FIFO not empty */
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while((readl(&priv->regs->ff_pt) & 0x0F) == 0U)
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;
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xfer->data.in[i] = readb(&priv->regs->ff_port);
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}
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while((readl(&priv->regs->int_sts) & CVI_SPIF_INT_STS_TRANS_DONE_MASK) == 0U)
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;
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/* Clear interrupt status */
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writeb(0U, &priv->regs->int_sts);
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return 0;
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}
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static int cvitek_spif_write(struct cvitek_spif_priv *priv, struct cvitek_spif_xfer *xfer)
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{
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u32 trans_ctrl;
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u32 i;
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u8 width;
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switch(xfer->width)
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{
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case 1:
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width = CVI_SPIF_BUS_WIDTH_1;
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break;
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case 2:
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width = CVI_SPIF_BUS_WIDTH_2;
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break;
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case 4:
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width = CVI_SPIF_BUS_WIDTH_4;
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break;
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default:
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return -EINVAL;
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}
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trans_ctrl |= CVI_SPIF_TRANS_CSR_FIFO_TRIG_LVL(3);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_BUS_WIDTH(width);
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trans_ctrl |= CVI_SPIF_TRANS_CSR_MODE(2); /* TX mode */
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/* Set up transfer mode */
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writel(trans_ctrl, &priv->regs->trans_csr);
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/* Write transfer length in bytes */
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writel(xfer->length, &priv->regs->trans_num);
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/* Reset FIFO pointer */
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writel(0U, &priv->regs->ff_pt);
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/* Start transfer */
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setbits_le32(&priv->regs->trans_csr, CVI_SPIF_TRANS_CSR_GO_BUSY_MASK);
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for(i = 0; i < xfer->length; i++)
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{
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/* Wait for FIFO not full */
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while((readl(&priv->regs->ff_pt) & 0x0F) >= CVI_SPIF_FIFO_DEPTH)
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;
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writeb(xfer->data.out[i], &priv->regs->ff_port);
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}
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while((readl(&priv->regs->int_sts) & CVI_SPIF_INT_STS_TRANS_DONE_MASK) == 0U)
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;
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/* Clear interrupt status */
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writeb(0U, &priv->regs->int_sts);
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return 0;
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}
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static int cvitek_spif_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
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{
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struct cvitek_spif_priv *priv = dev_get_priv(slave->dev->parent);
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struct cvitek_spif_xfer xfer;
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u8 buf[4];
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int ret;
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int i;
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/* Use manual CE control mode */
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writel((CVI_SPIF_CE_CTRL_CEMANUAL_MASK | CVI_SPIF_CE_CTRL_CEMANUAL_EN_MASK), &priv->regs->ce_ctrl);
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clrbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_MASK);
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if(op->cmd.nbytes)
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{
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if(op->cmd.nbytes == 1U)
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buf[0] = op->cmd.opcode & 0xFFU;
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else
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{
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buf[0] = (op->cmd.opcode >> 8U) & 0xFFU;
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buf[1] = op->cmd.opcode & 0xFFU;
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}
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xfer.data.out = buf;
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xfer.length = op->cmd.nbytes;
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xfer.width = op->cmd.buswidth;
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ret = cvitek_spif_write(priv, &xfer);
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if(ret < 0)
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return ret;
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}
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if(op->addr.nbytes)
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{
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if(op->addr.nbytes == 3U)
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{
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buf[0] = (op->addr.val >> 16U) & 0xFFU;
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buf[1] = (op->addr.val >> 8U) & 0xFFU;
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buf[2] = op->addr.val & 0xFFU;
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}
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else if(op->addr.nbytes == 4U)
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{
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buf[0] = (op->addr.val >> 24U) & 0xFFU;
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buf[1] = (op->addr.val >> 16U) & 0xFFU;
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buf[2] = (op->addr.val >> 8U) & 0xFFU;
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buf[3] = op->addr.val & 0xFFU;
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}
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else
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return -EINVAL;
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xfer.data.out = buf;
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xfer.length = op->addr.nbytes;
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xfer.width = op->addr.buswidth;
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ret = cvitek_spif_write(priv, &xfer);
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if(ret < 0)
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return ret;
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}
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if(op->dummy.nbytes)
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{
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xfer.data.in = buf;
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xfer.length = 1;
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xfer.width = op->dummy.buswidth;
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for(i = 0; i < op->dummy.nbytes; i++)
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{
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ret = cvitek_spif_write(priv, &xfer);
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if(ret < 0)
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return ret;
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}
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}
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if(op->data.nbytes && (op->data.dir != SPI_MEM_NO_DATA))
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{
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xfer.length = op->data.nbytes;
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xfer.width = op->data.buswidth;
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if(op->data.dir == SPI_MEM_DATA_IN)
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{
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xfer.data.in = op->data.buf.in;
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ret = cvitek_spif_read(priv, &xfer);
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}
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if(op->data.dir == SPI_MEM_DATA_OUT)
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{
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xfer.data.out = op->data.buf.out;
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ret = cvitek_spif_write(priv, &xfer);
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}
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if(ret < 0)
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return ret;
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}
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setbits_le32(&priv->regs->ce_ctrl, CVI_SPIF_CE_CTRL_CEMANUAL_MASK);
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return 0;
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}
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static int cvitek_spif_probe(struct udevice *bus)
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{
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int ret;
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struct clk clk;
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struct cvitek_spif_priv *priv = dev_get_priv(bus);
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priv->regs = dev_read_addr_ptr(bus);
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if(!priv->regs)
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return -EINVAL;
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ret = clk_get_by_index(bus, 0, &clk);
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if(ret < 0)
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return ret;
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ret = clk_enable(&clk);
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if(ret)
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{
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dev_err(bus, "failed to enable clock\n");
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return ret;
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}
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priv->clk_rate = clk_get_rate(&clk);
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if(!priv->clk_rate)
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{
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dev_err(bus, "failed to get clock rate\n");
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clk_disable(&clk);
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return -EINVAL;
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}
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/* Disable direct memory-mapped mode */
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writeb(0U, &priv->regs->dmmr);
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dev_dbg(bus, "cvitek-spi probed on addr %p\r\n", priv->regs);
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return 0;
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}
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static const struct spi_controller_mem_ops cvitek_spif_mem_ops = {
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.exec_op = cvitek_spif_exec_op,
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};
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static const struct dm_spi_ops cvitek_spif_ops = {
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.claim_bus = cvitek_spif_claim_bus,
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.release_bus = cvitek_spif_release_bus,
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.set_speed = cvitek_spif_set_speed,
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.set_mode = cvitek_spif_set_mode,
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.mem_ops = &cvitek_spif_mem_ops,
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};
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static const struct udevice_id cvitek_spif_ids[] = {
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{ .compatible = "cvitek,cvitek-spif" },
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{ }
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};
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U_BOOT_DRIVER(cvitek_spif) = {
|
|
.name = "cvitek_spif",
|
|
.id = UCLASS_SPI,
|
|
.of_match = cvitek_spif_ids,
|
|
.ops = &cvitek_spif_ops,
|
|
.priv_auto = sizeof(struct cvitek_spif_priv),
|
|
.probe = cvitek_spif_probe,
|
|
}; |