645ee3c25d
Add support for F1C100s internal dram controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* suniv DRAM controller register definition
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*
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* Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
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*
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* Based on xboot's arch/arm32/mach-f1c100s/sys-dram.c, which is:
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*
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* Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
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*/
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#define PIO_SDRAM_DRV (0x2c0)
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#define PIO_SDRAM_PULL (0x2c4)
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#define DRAM_SCONR (0x00)
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#define DRAM_STMG0R (0x04)
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#define DRAM_STMG1R (0x08)
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#define DRAM_SCTLR (0x0c)
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#define DRAM_SREFR (0x10)
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#define DRAM_SEXTMR (0x14)
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#define DRAM_DDLYR (0x24)
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#define DRAM_DADRR (0x28)
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#define DRAM_DVALR (0x2c)
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#define DRAM_DRPTR0 (0x30)
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#define DRAM_DRPTR1 (0x34)
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#define DRAM_DRPTR2 (0x38)
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#define DRAM_DRPTR3 (0x3c)
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#define DRAM_SEFR (0x40)
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#define DRAM_MAE (0x44)
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#define DRAM_ASPR (0x48)
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#define DRAM_SDLY0 (0x4C)
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#define DRAM_SDLY1 (0x50)
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#define DRAM_SDLY2 (0x54)
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#define DRAM_MCR0 (0x100)
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#define DRAM_MCR1 (0x104)
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#define DRAM_MCR2 (0x108)
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#define DRAM_MCR3 (0x10c)
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#define DRAM_MCR4 (0x110)
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#define DRAM_MCR5 (0x114)
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#define DRAM_MCR6 (0x118)
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#define DRAM_MCR7 (0x11c)
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#define DRAM_MCR8 (0x120)
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#define DRAM_MCR9 (0x124)
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#define DRAM_MCR10 (0x128)
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#define DRAM_MCR11 (0x12c)
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#define DRAM_BWCR (0x140)
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