1772771ac0
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now that we know what they are, let's replace magic offsets with proper register names. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
58 lines
1.5 KiB
C
58 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Sunxi H6 Power Management Unit register definition.
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*
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* (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#ifndef _SUN50I_PRCM_H
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#define _SUN50I_PRCM_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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struct sunxi_prcm_reg {
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u32 cpus_cfg; /* 0x000 */
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u8 res0[0x8]; /* 0x004 */
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u32 apbs1_cfg; /* 0x00c */
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u32 apbs2_cfg; /* 0x010 */
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u8 res1[0x108]; /* 0x014 */
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u32 tmr_gate_reset; /* 0x11c */
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u8 res2[0xc]; /* 0x120 */
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u32 twd_gate_reset; /* 0x12c */
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u8 res3[0xc]; /* 0x130 */
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u32 pwm_gate_reset; /* 0x13c */
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u8 res4[0x4c]; /* 0x140 */
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u32 uart_gate_reset; /* 0x18c */
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u8 res5[0xc]; /* 0x190 */
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u32 twi_gate_reset; /* 0x19c */
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u8 res6[0x1c]; /* 0x1a0 */
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u32 rsb_gate_reset; /* 0x1bc */
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u32 cir_cfg; /* 0x1c0 */
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u8 res7[0x8]; /* 0x1c4 */
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u32 cir_gate_reset; /* 0x1cc */
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u8 res8[0x10]; /* 0x1d0 */
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u32 w1_cfg; /* 0x1e0 */
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u8 res9[0x8]; /* 0x1e4 */
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u32 w1_gate_reset; /* 0x1ec */
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u8 res10[0x1c]; /* 0x1f0 */
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u32 rtc_gate_reset; /* 0x20c */
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u8 res11[0x34]; /* 0x210 */
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u32 pll_ldo_cfg; /* 0x244 */
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u8 res12[0x8]; /* 0x248 */
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u32 sys_pwroff_gating; /* 0x250 */
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u8 res13[0xbc]; /* 0x254 */
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u32 res_cal_ctrl; /* 0x310 */
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u32 ohms200; /* 0x314 */
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u32 ohms240; /* 0x318 */
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u32 res_cal_status; /* 0x31c */
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};
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check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
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check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
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#define PRCM_TWI_GATE (1 << 0)
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#define PRCM_TWI_RESET (1 << 16)
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#endif /* __ASSEMBLY__ */
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#endif /* _PRCM_H */
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