558378a4cd
Add support for new SoC sama7g5 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Chip-specific header file for the SAMA7G5 SoC
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*
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* Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
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* Eugen Hristev <eugen.hristev@microchip.com>
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*/
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#ifndef __SAMA7G5_H__
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#define __SAMA7G5_H__
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define ATMEL_ID_FLEXCOM0 38
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#define ATMEL_ID_FLEXCOM1 39
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#define ATMEL_ID_FLEXCOM2 40
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#define ATMEL_ID_FLEXCOM3 41
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#define ATMEL_ID_SDMMC0 80
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#define ATMEL_ID_SDMMC1 81
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#define ATMEL_ID_PIT64B0 70
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#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0
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#define ATMEL_CHIPID_CIDR 0xe0020000
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#define ATMEL_CHIPID_EXID 0xe0020004
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/*
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* User Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_PIOA 0xe0014000
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#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
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#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
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#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40)
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#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40)
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#define ATMEL_PIO_PORTS 5
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#define CPU_HAS_PCR
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#define ATMEL_BASE_PMC 0xe0018000
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#define ATMEL_BASE_WDT 0xe001c000
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#define ATMEL_BASE_RSTC 0xe001d000
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#define ATMEL_BASE_WDTS 0xe001d180
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#define ATMEL_BASE_SCKCR 0xe001d050
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#define ATMEL_BASE_SDMMC0 0xe1204000
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#define ATMEL_BASE_SDMMC1 0xe1208000
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#define ATMEL_BASE_PIT64B0 0xe1800000
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#define ATMEL_BASE_FLEXCOM0 0xe1818000
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#define ATMEL_BASE_FLEXCOM1 0xe181c000
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#define ATMEL_BASE_FLEXCOM2 0xe1820000
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#define ATMEL_BASE_FLEXCOM3 0xe1824000
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#define ATMEL_BASE_FLEXCOM4 0xe2018000
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#define ATMEL_BASE_TZC400 0xe3000000
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#define ATMEL_BASE_UMCTL2 0xe3800000
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#define ATMEL_BASE_UMCTL2_MP 0xe38003f8
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#define ATMEL_BASE_PUBL 0xe3804000
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#define ATMEL_NUM_FLEXCOM 12
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#define ATMEL_PIO_PORTS 5
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#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0
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#ifndef __ASSEMBLY__
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char *get_cpu_name(void);
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#endif
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#endif /* #ifndef __SAMA7G5_H__ */
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