323 lines
7.3 KiB
Plaintext
323 lines
7.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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*/
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/dts-v1/;
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#include "imx93.dtsi"
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/ {
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model = "NXP i.MX93 11X11 EVK board";
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compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
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chosen {
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stdout-path = &lpuart1;
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};
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reg_vref_1v8: regulator-adc-vref {
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compatible = "regulator-fixed";
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regulator-name = "vref_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&mu1 {
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status = "okay";
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};
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&mu2 {
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status = "okay";
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <5000000>;
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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eee-broken-1000t;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy2>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <5000000>;
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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eee-broken-1000t;
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};
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};
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};
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&lpi2c2 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c2>;
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pinctrl-1 = <&pinctrl_lpi2c2>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9451a";
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reg = <0x25>;
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interrupt-parent = <&pcal6524>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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buck1: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <650000>;
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regulator-max-microvolt = <2237500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4{
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regulator-name = "BUCK4";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5{
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regulator-name = "BUCK5";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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pcal6524: gpio@22 {
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compatible = "nxp,pcal6524";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcal6524>;
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&gpio3>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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};
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adp5585gpio: gpio@34 {
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compatible = "adp5585";
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reg = <0x34>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&lpuart1 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1>;
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pinctrl-2 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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no-sdio;
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no-mmc;
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};
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&iomuxc {
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pinctrl_lpi2c2: lpi2c2grp {
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fsl,pins = <
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MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
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MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
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>;
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};
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pinctrl_pcal6524: pcal6524grp {
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fsl,pins = <
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MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
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MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
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MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
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MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
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MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
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MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
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MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
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MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
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MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
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MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
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MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
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MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
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MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
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MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
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MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
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MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
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MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
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MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
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MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
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MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
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MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
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MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
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MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
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MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
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MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
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MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
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MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
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MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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};
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