e3e01a6f94
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. This patch is based on the corresponding Linux v6.5 device tree (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
145 lines
2.4 KiB
Plaintext
145 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
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#define PMOD1_SER0 1
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/ {
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aliases {
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serial1 = &scif2;
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i2c3 = &i2c3;
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};
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osc1: cec-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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hdmi-out {
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compatible = "hdmi-connector";
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type = "d";
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port {
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hdmi_con_out: endpoint {
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remote-endpoint = <&adv7535_out>;
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};
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};
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};
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};
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&cpu_dai {
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sound-dai = <&ssi0>;
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};
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&dsi {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&adv7535_in>;
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};
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};
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};
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};
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&i2c1 {
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adv7535: hdmi@3d {
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compatible = "adi,adv7535";
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reg = <0x3d>;
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interrupt-parent = <&pinctrl>;
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interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
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clocks = <&osc1>;
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clock-names = "cec";
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avdd-supply = <®_1p8v>;
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dvdd-supply = <®_1p8v>;
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pvdd-supply = <®_1p8v>;
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a2vdd-supply = <®_1p8v>;
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v3p3-supply = <®_3p3v>;
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v1p2-supply = <®_1p8v>;
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adi,dsi-lanes = <4>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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adv7535_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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adv7535_out: endpoint {
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remote-endpoint = <&hdmi_con_out>;
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};
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};
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};
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};
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};
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&i2c3 {
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pinctrl-0 = <&i2c3_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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wm8978: codec@1a {
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compatible = "wlf,wm8978";
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#sound-dai-cells = <0>;
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reg = <0x1a>;
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};
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};
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/*
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* To enable SCIF2 (SER0) on PMOD1 (CN7)
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* SW1 should be at position 2->3 so that SER0_CTS# line is activated
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* SW2 should be at position 2->3 so that SER0_TX line is activated
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* SW3 should be at position 2->3 so that SER0_RX line is activated
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* SW4 should be at position 2->3 so that SER0_RTS# line is activated
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*/
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#if PMOD1_SER0
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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#endif
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&ssi0 {
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pinctrl-0 = <&ssi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&vccq_sdhi1 {
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gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
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};
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